[llvm] [AMDGPU][Scheduler] Support for rematerializing SGPRs and AGPRs (PR #140036)

[Matt Arsenault via llvm-commits]

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@@ -1705,28 +1707,35 @@ struct ExcessRP {
   bool HasAGPRs = false;
   /// Whether the subtarget has a unified RF.
   bool UnifiedRF;
+  /// Whether we consider that ArchVGPRs can be spilled to AGPRs and the other
+  /// way around.
+  bool AllowVGPRToVGPRSpill;
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arsenm wrote:

The name is inaccurate and this is always true. It is not spilling. The register allocator will create a combined AV_ class during live range splitting in some cases. Copy to a compatible super register class is not a spill

https://github.com/llvm/llvm-project/pull/140036