[llvm] [AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (PR #140694)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 24 05:14:15 PDT 2025
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@@ -4056,6 +4056,53 @@ SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
SDLoc SL(N);
SelectionDAG &DAG = DCI.DAG;
+ // When the shl64_reduce optimisation code is passed through vector
+ // legalization some scalarising occurs. After ISD::AND was legalised, this
+ // resulted in the AND instructions no longer being elided, as mentioned
+ // below. The following code should make sure this takes place.
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arsenm wrote:
This is explaining some historical debugging and not directly what this is doing (dag style comments are also helpful)
This also feels like it's working around a generic combiner issue
https://github.com/llvm/llvm-project/pull/140694
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