[llvm] [X86] combineEXTRACT_SUBVECTOR - remove unnecessary bitcast handling. (PR #145496)
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Tue Jun 24 04:07:07 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-x86
Author: Simon Pilgrim (RKSimon)
<details>
<summary>Changes</summary>
We already aggressively fold extract_subvector(bitcast()) -> bitcast(extract_subvector())
---
Full diff: https://github.com/llvm/llvm-project/pull/145496.diff
1 Files Affected:
- (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+6-7)
``````````diff
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index d5837ab938d4e..7c26dd6e2dc2f 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -59577,7 +59577,6 @@ static SDValue combineEXTRACT_SUBVECTOR(SDNode *N, SelectionDAG &DAG,
MVT VT = N->getSimpleValueType(0);
SDValue InVec = N->getOperand(0);
unsigned IdxVal = N->getConstantOperandVal(1);
- SDValue InVecBC = peekThroughBitcasts(InVec);
EVT InVecVT = InVec.getValueType();
unsigned SizeInBits = VT.getSizeInBits();
unsigned InSizeInBits = InVecVT.getSizeInBits();
@@ -59594,7 +59593,7 @@ static SDValue combineEXTRACT_SUBVECTOR(SDNode *N, SelectionDAG &DAG,
// This pattern emerges during AVX1 legalization. We handle it before lowering
// to avoid complications like splitting constant vector loads.
if (Subtarget.hasAVX() && !Subtarget.hasAVX2() && TLI.isTypeLegal(InVecVT) &&
- InSizeInBits == 256 && InVecBC.getOpcode() == ISD::AND) {
+ InSizeInBits == 256 && InVec.getOpcode() == ISD::AND) {
auto isConcatenatedNot = [](SDValue V) {
V = peekThroughBitcasts(V);
if (!isBitwiseNot(V))
@@ -59602,12 +59601,12 @@ static SDValue combineEXTRACT_SUBVECTOR(SDNode *N, SelectionDAG &DAG,
SDValue NotOp = V->getOperand(0);
return peekThroughBitcasts(NotOp).getOpcode() == ISD::CONCAT_VECTORS;
};
- if (isConcatenatedNot(InVecBC.getOperand(0)) ||
- isConcatenatedNot(InVecBC.getOperand(1))) {
+ if (isConcatenatedNot(InVec.getOperand(0)) ||
+ isConcatenatedNot(InVec.getOperand(1))) {
// extract (and v4i64 X, (not (concat Y1, Y2))), n -> andnp v2i64 X(n), Y1
- SDValue Concat = splitVectorIntBinary(InVecBC, DAG, SDLoc(InVecBC));
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT,
- DAG.getBitcast(InVecVT, Concat), N->getOperand(1));
+ splitVectorIntBinary(InVec, DAG, DL),
+ N->getOperand(1));
}
}
@@ -59691,7 +59690,7 @@ static SDValue combineEXTRACT_SUBVECTOR(SDNode *N, SelectionDAG &DAG,
SmallVector<SDValue, 2> ShuffleInputs;
unsigned NumSubVecs = InSizeInBits / SizeInBits;
// Decode the shuffle mask and scale it so its shuffling subvectors.
- if (getTargetShuffleInputs(InVecBC, ShuffleInputs, ShuffleMask, DAG) &&
+ if (getTargetShuffleInputs(InVec, ShuffleInputs, ShuffleMask, DAG) &&
scaleShuffleElements(ShuffleMask, NumSubVecs, ScaledMask)) {
unsigned SubVecIdx = IdxVal / NumSubElts;
if (ScaledMask[SubVecIdx] == SM_SentinelUndef)
``````````
</details>
https://github.com/llvm/llvm-project/pull/145496
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