[llvm] [DAG] Add `SDPatternMatch::m_Load` (PR #145481)

[Simon Pilgrim via llvm-commits]

================
@@ -513,6 +513,12 @@ m_VSelect(const T0_P &Cond, const T1_P &T, const T2_P &F) {
   return TernaryOpc_match<T0_P, T1_P, T2_P>(ISD::VSELECT, Cond, T, F);
 }
 
+template <typename T0_P, typename T1_P, typename T2_P>
+inline TernaryOpc_match<T0_P, T1_P, T2_P>
+m_Load(const T0_P &Ch, const T1_P &Ptr, const T2_P &Offset) {
+  return TernaryOpc_match<T0_P, T1_P, T2_P>(ISD::LOAD, Ch, Ptr, Offset);
----------------
RKSimon wrote:

Should this match for both Load.getValue(0) (the loaded value) and Load.getValue(1) (the out chain)? Or should we have a template/run arg to match?

https://github.com/llvm/llvm-project/pull/145481