[llvm] [RISCV][NFC] Zce always implies/requires Zca (PR #145442)

[Sam Elliott via llvm-commits]

https://github.com/lenary created https://github.com/llvm/llvm-project/pull/145442

According to the spec, Zce:
- On RV32 without F: includes Zca, Zcb, Zcmp, Zcmt
- On RV32 with F: includes Zca, Zcb, Zcmp, Zcmt and Zcf
- On RV64: Zca, Zcb, Zcmp, Zcmt.

In these cases, Zce always implies Zca, Zcb, Zcmp, and Zcmt, so I have added it to the list of Implied/Required extensions, where it wasn't included before. The RV32f rule is implemented in RISCVISAInfo.cpp already.

This is NFC, because TableGen expands these implications transitively, which was eventually picking up Zca via any of the other three.

>From 462b96663fe499b1ec48c64b58785429372d7d50 Mon Sep 17 00:00:00 2001
From: Sam Elliott <quic_aelliott at quicinc.com>
Date: Mon, 23 Jun 2025 17:13:12 -0700
Subject: [PATCH] [RISCV][NFC] Zce always implies/requires Zca

According to the spec, Zce:
- On RV32 without F: includes Zca, Zcb, Zcmp, Zcmt
- On RV32 with F: includes Zca, Zcb, Zcmp, Zcmt and Zcf
- On RV64: Zca, Zcb, Zcmp, Zcmt.

In these cases, Zce always implies Zca, Zcb, Zcmp, and Zcmt, so I have
added it to the list of Implied/Required extensions, where it wasn't
included before. The RV32f rule is implemented in RISCVISAInfo.cpp
already.

This is NFC, because TableGen expands these implications transitively,
which was eventually picking up Zca via any of the other three.
---
 llvm/lib/Target/RISCV/RISCVFeatures.td | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index e2204eba4c23f..36b3aff51cda9 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -455,7 +455,8 @@ def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt()">,
 def FeatureStdExtZce
     : RISCVExtension<1, 0,
                      "Compressed extensions for microcontrollers",
-                     [FeatureStdExtZcb, FeatureStdExtZcmp, FeatureStdExtZcmt]>;
+                     [FeatureStdExtZca, FeatureStdExtZcb, FeatureStdExtZcmp,
+                      FeatureStdExtZcmt]>;
 
 def HasStdExtCOrZcfOrZce
     : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf() ||"