[llvm] f8e0518 - MC: Adjust -show-inst output for MCExpr
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Sun Jun 15 21:46:14 PDT 2025
Author: Fangrui Song
Date: 2025-06-15T21:46:09-07:00
New Revision: f8e0518120cd2850a7f674322bf428bc7d7d3326
URL: https://github.com/llvm/llvm-project/commit/f8e0518120cd2850a7f674322bf428bc7d7d3326
DIFF: https://github.com/llvm/llvm-project/commit/f8e0518120cd2850a7f674322bf428bc7d7d3326.diff
LOG: MC: Adjust -show-inst output for MCExpr
This dump feature does not pass MCAsmInfo to the printer function.
When we remove MCSpecifierExpr subclasses (and the printImpl overrides),
we will not be able to print target-specific specifier strings.
Just print a textual representation.
Added:
Modified:
llvm/lib/MC/MCExpr.cpp
llvm/lib/MC/MCInst.cpp
llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll
llvm/test/CodeGen/Mips/llvm-ir/load.ll
llvm/test/CodeGen/Mips/llvm-ir/store.ll
llvm/test/MC/Lanai/conditional_inst.s
llvm/test/MC/Lanai/memory.s
Removed:
################################################################################
diff --git a/llvm/lib/MC/MCExpr.cpp b/llvm/lib/MC/MCExpr.cpp
index 5ccad6d487973..89191294f3ed3 100644
--- a/llvm/lib/MC/MCExpr.cpp
+++ b/llvm/lib/MC/MCExpr.cpp
@@ -173,10 +173,15 @@ void MCExpr::print(raw_ostream &OS, const MCAsmInfo *MAI,
return;
}
- case MCExpr::Specifier:
- // TODO: Remove after all targets that use MCSpecifierExpr migrate to
- // MCAsmInfo::printSpecifierExpr.
- return cast<MCSpecifierExpr>(this)->printImpl(OS, MAI);
+ case MCExpr::Specifier: {
+ auto &SE = cast<MCSpecifierExpr>(*this);
+ if (MAI)
+ return MAI->printSpecifierExpr(OS, SE);
+ // Used by dump features like -show-inst. Regular MCAsmStreamer output must
+ // set MAI.
+ OS << "specifier(" << SE.getSpecifier() << ',' << *SE.getSubExpr() << ')';
+ return;
+ }
}
llvm_unreachable("Invalid expression kind!");
diff --git a/llvm/lib/MC/MCInst.cpp b/llvm/lib/MC/MCInst.cpp
index 639619fe4e991..832d25060f880 100644
--- a/llvm/lib/MC/MCInst.cpp
+++ b/llvm/lib/MC/MCInst.cpp
@@ -35,7 +35,7 @@ void MCOperand::print(raw_ostream &OS, const MCRegisterInfo *RegInfo) const {
else if (isDFPImm())
OS << "DFPImm:" << bit_cast<double>(getDFPImm());
else if (isExpr()) {
- OS << "Expr:(" << *getExpr() << ")";
+ OS << "Expr:" << *getExpr();
} else if (isInst()) {
OS << "Inst:(";
if (const auto *Inst = getInst())
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll b/llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll
index 3bf17abc7965e..79fe2fd26a6e2 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll
@@ -38,189 +38,189 @@
define i32 @test1(float %t) {
; M32-LABEL: test1:
; M32: # %bb.0: # %entry
-; M32-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
-; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; M32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; M32-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
-; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; M32-NEXT: trunc.w.s $f0, $f12 # <MCInst #[[#MCINST1:]] TRUNC_W_S
+; M32-NEXT: # <MCOperand Reg:[[#MCREG1:]]>
+; M32-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>
+; M32-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
+; M32-NEXT: # <MCOperand Reg:[[#MCREG3:]]>>
+; M32-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1
+; M32-NEXT: # <MCOperand Reg:[[#MCREG4:]]>
+; M32-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
;
; M32R2-FP64-LABEL: test1:
; M32R2-FP64: # %bb.0: # %entry
-; M32R2-FP64-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
-; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; M32R2-FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; M32R2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
-; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; M32R2-FP64-NEXT: trunc.w.s $f0, $f12 # <MCInst #[[#MCINST1:]] TRUNC_W_S
+; M32R2-FP64-NEXT: # <MCOperand Reg:[[#MCREG1:]]>
+; M32R2-FP64-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>
+; M32R2-FP64-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
+; M32R2-FP64-NEXT: # <MCOperand Reg:[[#MCREG3:]]>>
+; M32R2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1
+; M32R2-FP64-NEXT: # <MCOperand Reg:[[#MCREG4:]]>
+; M32R2-FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
;
; M32R2-SF-LABEL: test1:
; M32R2-SF: # %bb.0: # %entry
-; M32R2-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #{{[0-9]+}} ADDiu
-; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; M32R2-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #[[#MCINST4:]] ADDiu
+; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5:]]>
+; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; M32R2-SF-NEXT: # <MCOperand Imm:-24>>
; M32R2-SF-NEXT: .cfi_def_cfa_offset 24
; M32R2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
-; M32R2-SF-NEXT: # <MCInst #{{[0-9]+}} SW
-; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; M32R2-SF-NEXT: # <MCInst #[[#MCINST5:]] SW
+; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG3:]]>
+; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; M32R2-SF-NEXT: # <MCOperand Imm:20>>
; M32R2-SF-NEXT: .cfi_offset 31, -4
-; M32R2-SF-NEXT: jal __fixsfsi # <MCInst #{{[0-9]+}} JAL
-; M32R2-SF-NEXT: # <MCOperand Expr:(__fixsfsi)>>
-; M32R2-SF-NEXT: nop # <MCInst #{{[0-9]+}} SLL
-; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; M32R2-SF-NEXT: jal __fixsfsi # <MCInst #[[#MCINST6:]] JAL
+; M32R2-SF-NEXT: # <MCOperand Expr:__fixsfsi>>
+; M32R2-SF-NEXT: nop # <MCInst #[[#MCINST7:]] SLL
+; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG6:]]>
+; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG6]]>
; M32R2-SF-NEXT: # <MCOperand Imm:0>>
; M32R2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
-; M32R2-SF-NEXT: # <MCInst #{{[0-9]+}} LW
-; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; M32R2-SF-NEXT: # <MCInst #[[#MCINST8:]] LW
+; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; M32R2-SF-NEXT: # <MCOperand Imm:20>>
-; M32R2-SF-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; M32R2-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #{{[0-9]+}} ADDiu
-; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; M32R2-SF-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
+; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>>
+; M32R2-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #[[#MCINST4]] ADDiu
+; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; M32R2-SF-NEXT: # <MCOperand Imm:24>>
;
; M32R3R5-LABEL: test1:
; M32R3R5: # %bb.0: # %entry
-; M32R3R5-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
-; M32R3R5-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M32R3R5-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; M32R3R5-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; M32R3R5-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; M32R3R5-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
-; M32R3R5-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M32R3R5-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; M32R3R5-NEXT: trunc.w.s $f0, $f12 # <MCInst #[[#MCINST1:]] TRUNC_W_S
+; M32R3R5-NEXT: # <MCOperand Reg:[[#MCREG1:]]>
+; M32R3R5-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>
+; M32R3R5-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
+; M32R3R5-NEXT: # <MCOperand Reg:[[#MCREG3:]]>>
+; M32R3R5-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1
+; M32R3R5-NEXT: # <MCOperand Reg:[[#MCREG4:]]>
+; M32R3R5-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
;
; M32R6-LABEL: test1:
; M32R6: # %bb.0: # %entry
-; M32R6-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
-; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; M32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
-; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; M32R6-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
-; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; M32R6-NEXT: trunc.w.s $f0, $f12 # <MCInst #[[#MCINST1:]] TRUNC_W_S
+; M32R6-NEXT: # <MCOperand Reg:[[#MCREG1:]]>
+; M32R6-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>
+; M32R6-NEXT: jr $ra # <MCInst #[[#MCINST9:]] JALR
+; M32R6-NEXT: # <MCOperand Reg:[[#MCREG6:]]>
+; M32R6-NEXT: # <MCOperand Reg:[[#MCREG3:]]>>
+; M32R6-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1
+; M32R6-NEXT: # <MCOperand Reg:[[#MCREG4:]]>
+; M32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
;
; M64-LABEL: test1:
; M64: # %bb.0: # %entry
-; M64-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
-; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; M64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; M64-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
-; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; M64-NEXT: trunc.w.s $f0, $f12 # <MCInst #[[#MCINST1:]] TRUNC_W_S
+; M64-NEXT: # <MCOperand Reg:[[#MCREG1:]]>
+; M64-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>
+; M64-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
+; M64-NEXT: # <MCOperand Reg:[[#MCREG7:]]>>
+; M64-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1
+; M64-NEXT: # <MCOperand Reg:[[#MCREG4:]]>
+; M64-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
;
; M64R6-LABEL: test1:
; M64R6: # %bb.0: # %entry
-; M64R6-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
-; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; M64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
-; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; M64R6-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
-; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; M64R6-NEXT: trunc.w.s $f0, $f12 # <MCInst #[[#MCINST1:]] TRUNC_W_S
+; M64R6-NEXT: # <MCOperand Reg:[[#MCREG1:]]>
+; M64R6-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>
+; M64R6-NEXT: jr $ra # <MCInst #[[#MCINST10:]] JALR64
+; M64R6-NEXT: # <MCOperand Reg:[[#MCREG8:]]>
+; M64R6-NEXT: # <MCOperand Reg:[[#MCREG7:]]>>
+; M64R6-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1
+; M64R6-NEXT: # <MCOperand Reg:[[#MCREG4:]]>
+; M64R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
;
; MMR2-FP32-LABEL: test1:
; MMR2-FP32: # %bb.0: # %entry
-; MMR2-FP32-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S_MM
-; MMR2-FP32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR2-FP32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR2-FP32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR2-FP32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR2-FP32-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
-; MMR2-FP32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR2-FP32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; MMR2-FP32-NEXT: trunc.w.s $f0, $f12 # <MCInst #[[#MCINST11:]] TRUNC_W_S_MM
+; MMR2-FP32-NEXT: # <MCOperand Reg:[[#MCREG1:]]>
+; MMR2-FP32-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>
+; MMR2-FP32-NEXT: jr $ra # <MCInst #[[#MCINST12:]] JR_MM
+; MMR2-FP32-NEXT: # <MCOperand Reg:[[#MCREG3:]]>>
+; MMR2-FP32-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST13:]] MFC1_MM
+; MMR2-FP32-NEXT: # <MCOperand Reg:[[#MCREG4:]]>
+; MMR2-FP32-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
;
; MMR2-FP64-LABEL: test1:
; MMR2-FP64: # %bb.0: # %entry
-; MMR2-FP64-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S_MM
-; MMR2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR2-FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
-; MMR2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; MMR2-FP64-NEXT: trunc.w.s $f0, $f12 # <MCInst #[[#MCINST11:]] TRUNC_W_S_MM
+; MMR2-FP64-NEXT: # <MCOperand Reg:[[#MCREG1:]]>
+; MMR2-FP64-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>
+; MMR2-FP64-NEXT: jr $ra # <MCInst #[[#MCINST12:]] JR_MM
+; MMR2-FP64-NEXT: # <MCOperand Reg:[[#MCREG3:]]>>
+; MMR2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST13:]] MFC1_MM
+; MMR2-FP64-NEXT: # <MCOperand Reg:[[#MCREG4:]]>
+; MMR2-FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
;
; MMR2-SF-LABEL: test1:
; MMR2-SF: # %bb.0: # %entry
-; MMR2-SF-NEXT: addiusp -24 # <MCInst #{{[0-9]+}} ADDIUSP_MM
+; MMR2-SF-NEXT: addiusp -24 # <MCInst #[[#MCINST14:]] ADDIUSP_MM
; MMR2-SF-NEXT: # <MCOperand Imm:-24>>
; MMR2-SF-NEXT: .cfi_def_cfa_offset 24
; MMR2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
-; MMR2-SF-NEXT: # <MCInst #{{[0-9]+}} SWSP_MM
-; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MMR2-SF-NEXT: # <MCInst #[[#MCINST15:]] SWSP_MM
+; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG3:]]>
+; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG5:]]>
; MMR2-SF-NEXT: # <MCOperand Imm:20>>
; MMR2-SF-NEXT: .cfi_offset 31, -4
-; MMR2-SF-NEXT: jal __fixsfsi # <MCInst #{{[0-9]+}} JAL_MM
-; MMR2-SF-NEXT: # <MCOperand Expr:(__fixsfsi)>>
-; MMR2-SF-NEXT: nop # <MCInst #{{[0-9]+}} SLL
-; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MMR2-SF-NEXT: jal __fixsfsi # <MCInst #[[#MCINST16:]] JAL_MM
+; MMR2-SF-NEXT: # <MCOperand Expr:__fixsfsi>>
+; MMR2-SF-NEXT: nop # <MCInst #[[#MCINST17:]] SLL_MM
+; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG6:]]>
+; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG6]]>
; MMR2-SF-NEXT: # <MCOperand Imm:0>>
; MMR2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
-; MMR2-SF-NEXT: # <MCInst #{{[0-9]+}} LWSP_MM
-; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MMR2-SF-NEXT: # <MCInst #[[#MCINST18:]] LWSP_MM
+; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MMR2-SF-NEXT: # <MCOperand Imm:20>>
-; MMR2-SF-NEXT: addiusp 24 # <MCInst #{{[0-9]+}} ADDIUSP_MM
+; MMR2-SF-NEXT: addiusp 24 # <MCInst #[[#MCINST14]] ADDIUSP_MM
; MMR2-SF-NEXT: # <MCOperand Imm:24>>
-; MMR2-SF-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; MMR2-SF-NEXT: jrc $ra # <MCInst #[[#MCINST19:]] JRC16_MM
+; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>>
;
; MMR6-LABEL: test1:
; MMR6: # %bb.0: # %entry
-; MMR6-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S_MMR6
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR6-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; MMR6-NEXT: trunc.w.s $f0, $f12 # <MCInst #[[#MCINST20:]] TRUNC_W_S_MMR6
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1:]]>
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>
+; MMR6-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST13:]] MFC1_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG4:]]>
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
+; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST19:]] JRC16_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3:]]>>
;
; MMR6-SF-LABEL: test1:
; MMR6-SF: # %bb.0: # %entry
-; MMR6-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #{{[0-9]+}} ADDiu
-; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #[[#MCINST4:]] ADDiu
+; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5:]]>
+; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MMR6-SF-NEXT: # <MCOperand Imm:-24>>
; MMR6-SF-NEXT: .cfi_def_cfa_offset 24
; MMR6-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
-; MMR6-SF-NEXT: # <MCInst #{{[0-9]+}} SW
-; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-SF-NEXT: # <MCInst #[[#MCINST5:]] SW
+; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG3:]]>
+; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MMR6-SF-NEXT: # <MCOperand Imm:20>>
; MMR6-SF-NEXT: .cfi_offset 31, -4
-; MMR6-SF-NEXT: balc __fixsfsi # <MCInst #{{[0-9]+}} BALC_MMR6
-; MMR6-SF-NEXT: # <MCOperand Expr:(__fixsfsi)>>
+; MMR6-SF-NEXT: balc __fixsfsi # <MCInst #[[#MCINST21:]] BALC_MMR6
+; MMR6-SF-NEXT: # <MCOperand Expr:__fixsfsi>>
; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
-; MMR6-SF-NEXT: # <MCInst #{{[0-9]+}} LW
-; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-SF-NEXT: # <MCInst #[[#MCINST8:]] LW
+; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MMR6-SF-NEXT: # <MCOperand Imm:20>>
-; MMR6-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #{{[0-9]+}} ADDiu
-; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #[[#MCINST4]] ADDiu
+; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MMR6-SF-NEXT: # <MCOperand Imm:24>>
-; MMR6-SF-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; MMR6-SF-NEXT: jrc $ra # <MCInst #[[#MCINST19:]] JRC16_MM
+; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>>
entry:
%conv = fptosi float %t to i32
ret i32 %conv
@@ -229,189 +229,189 @@ entry:
define i32 @test2(double %t) {
; M32-LABEL: test2:
; M32: # %bb.0: # %entry
-; M32-NEXT: trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D32
-; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; M32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; M32-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
-; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; M32-NEXT: trunc.w.d $f0, $f12 # <MCInst #[[#MCINST22:]] TRUNC_W_D32
+; M32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; M32-NEXT: # <MCOperand Reg:[[#MCREG9:]]>>
+; M32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; M32-NEXT: # <MCOperand Reg:[[#MCREG3]]>>
+; M32-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1
+; M32-NEXT: # <MCOperand Reg:[[#MCREG4]]>
+; M32-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
;
; M32R2-FP64-LABEL: test2:
; M32R2-FP64: # %bb.0: # %entry
-; M32R2-FP64-NEXT: trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D64
-; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; M32R2-FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; M32R2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
-; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; M32R2-FP64-NEXT: trunc.w.d $f0, $f12 # <MCInst #[[#MCINST23:]] TRUNC_W_D64
+; M32R2-FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; M32R2-FP64-NEXT: # <MCOperand Reg:[[#MCREG10:]]>>
+; M32R2-FP64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; M32R2-FP64-NEXT: # <MCOperand Reg:[[#MCREG3]]>>
+; M32R2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1
+; M32R2-FP64-NEXT: # <MCOperand Reg:[[#MCREG4]]>
+; M32R2-FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
;
; M32R2-SF-LABEL: test2:
; M32R2-SF: # %bb.0: # %entry
-; M32R2-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #{{[0-9]+}} ADDiu
-; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; M32R2-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #[[#MCINST4]] ADDiu
+; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; M32R2-SF-NEXT: # <MCOperand Imm:-24>>
; M32R2-SF-NEXT: .cfi_def_cfa_offset 24
; M32R2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
-; M32R2-SF-NEXT: # <MCInst #{{[0-9]+}} SW
-; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; M32R2-SF-NEXT: # <MCInst #[[#MCINST5]] SW
+; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; M32R2-SF-NEXT: # <MCOperand Imm:20>>
; M32R2-SF-NEXT: .cfi_offset 31, -4
-; M32R2-SF-NEXT: jal __fixdfsi # <MCInst #{{[0-9]+}} JAL
-; M32R2-SF-NEXT: # <MCOperand Expr:(__fixdfsi)>>
-; M32R2-SF-NEXT: nop # <MCInst #{{[0-9]+}} SLL
-; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; M32R2-SF-NEXT: jal __fixdfsi # <MCInst #[[#MCINST6]] JAL
+; M32R2-SF-NEXT: # <MCOperand Expr:__fixdfsi>>
+; M32R2-SF-NEXT: nop # <MCInst #[[#MCINST7]] SLL
+; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG6]]>
+; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG6]]>
; M32R2-SF-NEXT: # <MCOperand Imm:0>>
; M32R2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
-; M32R2-SF-NEXT: # <MCInst #{{[0-9]+}} LW
-; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; M32R2-SF-NEXT: # <MCInst #[[#MCINST8]] LW
+; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; M32R2-SF-NEXT: # <MCOperand Imm:20>>
-; M32R2-SF-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; M32R2-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #{{[0-9]+}} ADDiu
-; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; M32R2-SF-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>>
+; M32R2-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #[[#MCINST4]] ADDiu
+; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; M32R2-SF-NEXT: # <MCOperand Imm:24>>
;
; M32R3R5-LABEL: test2:
; M32R3R5: # %bb.0: # %entry
-; M32R3R5-NEXT: trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D32
-; M32R3R5-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M32R3R5-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; M32R3R5-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; M32R3R5-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; M32R3R5-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
-; M32R3R5-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M32R3R5-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; M32R3R5-NEXT: trunc.w.d $f0, $f12 # <MCInst #[[#MCINST22:]] TRUNC_W_D32
+; M32R3R5-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; M32R3R5-NEXT: # <MCOperand Reg:[[#MCREG9:]]>>
+; M32R3R5-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; M32R3R5-NEXT: # <MCOperand Reg:[[#MCREG3]]>>
+; M32R3R5-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1
+; M32R3R5-NEXT: # <MCOperand Reg:[[#MCREG4]]>
+; M32R3R5-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
;
; M32R6-LABEL: test2:
; M32R6: # %bb.0: # %entry
-; M32R6-NEXT: trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D64
-; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; M32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
-; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; M32R6-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
-; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; M32R6-NEXT: trunc.w.d $f0, $f12 # <MCInst #[[#MCINST23:]] TRUNC_W_D64
+; M32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; M32R6-NEXT: # <MCOperand Reg:[[#MCREG10:]]>>
+; M32R6-NEXT: jr $ra # <MCInst #[[#MCINST9]] JALR
+; M32R6-NEXT: # <MCOperand Reg:[[#MCREG6]]>
+; M32R6-NEXT: # <MCOperand Reg:[[#MCREG3]]>>
+; M32R6-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1
+; M32R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>
+; M32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
;
; M64-LABEL: test2:
; M64: # %bb.0: # %entry
-; M64-NEXT: trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D64
-; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; M64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; M64-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
-; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; M64-NEXT: trunc.w.d $f0, $f12 # <MCInst #[[#MCINST23:]] TRUNC_W_D64
+; M64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; M64-NEXT: # <MCOperand Reg:[[#MCREG10:]]>>
+; M64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; M64-NEXT: # <MCOperand Reg:[[#MCREG7]]>>
+; M64-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1
+; M64-NEXT: # <MCOperand Reg:[[#MCREG4]]>
+; M64-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
;
; M64R6-LABEL: test2:
; M64R6: # %bb.0: # %entry
-; M64R6-NEXT: trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D64
-; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; M64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
-; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; M64R6-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
-; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; M64R6-NEXT: trunc.w.d $f0, $f12 # <MCInst #[[#MCINST23:]] TRUNC_W_D64
+; M64R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; M64R6-NEXT: # <MCOperand Reg:[[#MCREG10:]]>>
+; M64R6-NEXT: jr $ra # <MCInst #[[#MCINST10]] JALR64
+; M64R6-NEXT: # <MCOperand Reg:[[#MCREG8]]>
+; M64R6-NEXT: # <MCOperand Reg:[[#MCREG7]]>>
+; M64R6-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1
+; M64R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>
+; M64R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
;
; MMR2-FP32-LABEL: test2:
; MMR2-FP32: # %bb.0: # %entry
-; MMR2-FP32-NEXT: trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_MM
-; MMR2-FP32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR2-FP32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR2-FP32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR2-FP32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR2-FP32-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
-; MMR2-FP32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR2-FP32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; MMR2-FP32-NEXT: trunc.w.d $f0, $f12 # <MCInst #[[#MCINST24:]] TRUNC_W_MM
+; MMR2-FP32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR2-FP32-NEXT: # <MCOperand Reg:[[#MCREG9:]]>>
+; MMR2-FP32-NEXT: jr $ra # <MCInst #[[#MCINST12]] JR_MM
+; MMR2-FP32-NEXT: # <MCOperand Reg:[[#MCREG3]]>>
+; MMR2-FP32-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST13]] MFC1_MM
+; MMR2-FP32-NEXT: # <MCOperand Reg:[[#MCREG4]]>
+; MMR2-FP32-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
;
; MMR2-FP64-LABEL: test2:
; MMR2-FP64: # %bb.0: # %entry
-; MMR2-FP64-NEXT: cvt.w.d $f0, $f12 # <MCInst #{{[0-9]+}} CVT_W_D64_MM
-; MMR2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR2-FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
-; MMR2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; MMR2-FP64-NEXT: cvt.w.d $f0, $f12 # <MCInst #[[#MCINST25:]] CVT_W_D64_MM
+; MMR2-FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR2-FP64-NEXT: # <MCOperand Reg:[[#MCREG10:]]>>
+; MMR2-FP64-NEXT: jr $ra # <MCInst #[[#MCINST12]] JR_MM
+; MMR2-FP64-NEXT: # <MCOperand Reg:[[#MCREG3]]>>
+; MMR2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST13]] MFC1_MM
+; MMR2-FP64-NEXT: # <MCOperand Reg:[[#MCREG4]]>
+; MMR2-FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
;
; MMR2-SF-LABEL: test2:
; MMR2-SF: # %bb.0: # %entry
-; MMR2-SF-NEXT: addiusp -24 # <MCInst #{{[0-9]+}} ADDIUSP_MM
+; MMR2-SF-NEXT: addiusp -24 # <MCInst #[[#MCINST14]] ADDIUSP_MM
; MMR2-SF-NEXT: # <MCOperand Imm:-24>>
; MMR2-SF-NEXT: .cfi_def_cfa_offset 24
; MMR2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
-; MMR2-SF-NEXT: # <MCInst #{{[0-9]+}} SWSP_MM
-; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MMR2-SF-NEXT: # <MCInst #[[#MCINST15]] SWSP_MM
+; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MMR2-SF-NEXT: # <MCOperand Imm:20>>
; MMR2-SF-NEXT: .cfi_offset 31, -4
-; MMR2-SF-NEXT: jal __fixdfsi # <MCInst #{{[0-9]+}} JAL_MM
-; MMR2-SF-NEXT: # <MCOperand Expr:(__fixdfsi)>>
-; MMR2-SF-NEXT: nop # <MCInst #{{[0-9]+}} SLL
-; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MMR2-SF-NEXT: jal __fixdfsi # <MCInst #[[#MCINST16]] JAL_MM
+; MMR2-SF-NEXT: # <MCOperand Expr:__fixdfsi>>
+; MMR2-SF-NEXT: nop # <MCInst #[[#MCINST17]] SLL_MM
+; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG6]]>
+; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG6]]>
; MMR2-SF-NEXT: # <MCOperand Imm:0>>
; MMR2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
-; MMR2-SF-NEXT: # <MCInst #{{[0-9]+}} LWSP_MM
-; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MMR2-SF-NEXT: # <MCInst #[[#MCINST18]] LWSP_MM
+; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MMR2-SF-NEXT: # <MCOperand Imm:20>>
-; MMR2-SF-NEXT: addiusp 24 # <MCInst #{{[0-9]+}} ADDIUSP_MM
+; MMR2-SF-NEXT: addiusp 24 # <MCInst #[[#MCINST14]] ADDIUSP_MM
; MMR2-SF-NEXT: # <MCOperand Imm:24>>
-; MMR2-SF-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; MMR2-SF-NEXT: jrc $ra # <MCInst #[[#MCINST19]] JRC16_MM
+; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>>
;
; MMR6-LABEL: test2:
; MMR6: # %bb.0: # %entry
-; MMR6-NEXT: trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D_MMR6
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR6-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; MMR6-NEXT: trunc.w.d $f0, $f12 # <MCInst #[[#MCINST26:]] TRUNC_W_D_MMR6
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG10:]]>>
+; MMR6-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST13]] MFC1_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG4]]>
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>>
+; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST19]] JRC16_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3]]>>
;
; MMR6-SF-LABEL: test2:
; MMR6-SF: # %bb.0: # %entry
-; MMR6-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #{{[0-9]+}} ADDiu
-; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #[[#MCINST4]] ADDiu
+; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MMR6-SF-NEXT: # <MCOperand Imm:-24>>
; MMR6-SF-NEXT: .cfi_def_cfa_offset 24
; MMR6-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
-; MMR6-SF-NEXT: # <MCInst #{{[0-9]+}} SW
-; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-SF-NEXT: # <MCInst #[[#MCINST5]] SW
+; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MMR6-SF-NEXT: # <MCOperand Imm:20>>
; MMR6-SF-NEXT: .cfi_offset 31, -4
-; MMR6-SF-NEXT: balc __fixdfsi # <MCInst #{{[0-9]+}} BALC_MMR6
-; MMR6-SF-NEXT: # <MCOperand Expr:(__fixdfsi)>>
+; MMR6-SF-NEXT: balc __fixdfsi # <MCInst #[[#MCINST21]] BALC_MMR6
+; MMR6-SF-NEXT: # <MCOperand Expr:__fixdfsi>>
; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
-; MMR6-SF-NEXT: # <MCInst #{{[0-9]+}} LW
-; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-SF-NEXT: # <MCInst #[[#MCINST8]] LW
+; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MMR6-SF-NEXT: # <MCOperand Imm:20>>
-; MMR6-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #{{[0-9]+}} ADDiu
-; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #[[#MCINST4]] ADDiu
+; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MMR6-SF-NEXT: # <MCOperand Imm:24>>
-; MMR6-SF-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; MMR6-SF-NEXT: jrc $ra # <MCInst #[[#MCINST19]] JRC16_MM
+; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>>
entry:
%conv = fptosi double %t to i32
ret i32 %conv
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/load.ll b/llvm/test/CodeGen/Mips/llvm-ir/load.ll
index b96bdff227cae..ee858ac94aed6 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/load.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/load.ll
@@ -25,161 +25,161 @@
define i8 @f1() {
; MIPS32-LABEL: f1:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Expr:(%hi(a))>>
-; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32-NEXT: lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Expr:(%lo(a))>>
+; MIPS32-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST1:]] LUi
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1:]]>
+; MIPS32-NEXT: # <MCOperand Expr:specifier(4028,a)>>
+; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>
+; MIPS32-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST3:]] LBu
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG3:]]>
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32-NEXT: # <MCOperand Expr:specifier(4031,a)>>
;
; MMR3-LABEL: f1:
; MMR3: # %bb.0: # %entry
-; MMR3-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Expr:(%hi(a))>>
-; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR3-NEXT: lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Expr:(%lo(a))>>
+; MMR3-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST4:]] LUi_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1:]]>
+; MMR3-NEXT: # <MCOperand Expr:specifier(4028,a)>>
+; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5:]] JR_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>
+; MMR3-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST6:]] LBu_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG3:]]>
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR3-NEXT: # <MCOperand Expr:specifier(4031,a)>>
;
; MIPS32R6-LABEL: f1:
; MIPS32R6: # %bb.0: # %entry
-; MIPS32R6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(a))>>
-; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32R6-NEXT: lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(a))>>
+; MIPS32R6-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST1:]] LUi
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1:]]>
+; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4028,a)>>
+; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7:]] JALR
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG4:]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>
+; MIPS32R6-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST3:]] LBu
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG3:]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4031,a)>>
;
; MMR6-LABEL: f1:
; MMR6: # %bb.0: # %entry
-; MMR6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Expr:(%hi(a))>>
-; MMR6-NEXT: lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Expr:(%lo(a))>>
-; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; MMR6-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST4:]] LUi_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1:]]>
+; MMR6-NEXT: # <MCOperand Expr:specifier(4028,a)>>
+; MMR6-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST6:]] LBu_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3:]]>
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR6-NEXT: # <MCOperand Expr:specifier(4031,a)>>
+; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8:]] JRC16_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>
;
; MIPS3-LABEL: f1:
; MIPS3: # %bb.0: # %entry
-; MIPS3-NEXT: lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%highest(a))>>
-; MIPS3-NEXT: daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%higher(a))>>
-; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT: lui $1, %highest(a) # <MCInst #[[#MCINST9:]] LUi64
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5:]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4030,a)>>
+; MIPS3-NEXT: daddiu $1, $1, %higher(a) # <MCInst #[[#MCINST10:]] DADDiu
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4029,a)>>
+; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11:]] DSLL
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS3-NEXT: # <MCOperand Imm:16>>
-; MIPS3-NEXT: daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%hi(a))>>
-; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT: daddiu $1, $1, %hi(a) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4028,a)>>
+; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS3-NEXT: # <MCOperand Imm:16>>
-; MIPS3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS3-NEXT: lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%lo(a))>>
+; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG6:]]>>
+; MIPS3-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST3:]] LBu
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG3:]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4031,a)>>
;
; MIPS64-LABEL: f1:
; MIPS64: # %bb.0: # %entry
-; MIPS64-NEXT: lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%highest(a))>>
-; MIPS64-NEXT: daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%higher(a))>>
-; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT: lui $1, %highest(a) # <MCInst #[[#MCINST9:]] LUi64
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5:]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4030,a)>>
+; MIPS64-NEXT: daddiu $1, $1, %higher(a) # <MCInst #[[#MCINST10:]] DADDiu
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4029,a)>>
+; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11:]] DSLL
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64-NEXT: # <MCOperand Imm:16>>
-; MIPS64-NEXT: daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%hi(a))>>
-; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT: daddiu $1, $1, %hi(a) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4028,a)>>
+; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64-NEXT: # <MCOperand Imm:16>>
-; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS64-NEXT: lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%lo(a))>>
+; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG6:]]>>
+; MIPS64-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST3:]] LBu
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG3:]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4031,a)>>
;
; MIPS64R6-LABEL: f1:
; MIPS64R6: # %bb.0: # %entry
-; MIPS64R6-NEXT: lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(a))>>
-; MIPS64R6-NEXT: daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(a))>>
-; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT: lui $1, %highest(a) # <MCInst #[[#MCINST9:]] LUi64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5:]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4030,a)>>
+; MIPS64R6-NEXT: daddiu $1, $1, %higher(a) # <MCInst #[[#MCINST10:]] DADDiu
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4029,a)>>
+; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11:]] DSLL
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
-; MIPS64R6-NEXT: daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(a))>>
-; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT: daddiu $1, $1, %hi(a) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4028,a)>>
+; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
-; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS64R6-NEXT: lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(a))>>
+; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST12:]] JALR64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG7:]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG6:]]>>
+; MIPS64R6-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST3:]] LBu
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG3:]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4031,a)>>
;
; MMR5FP64-LABEL: f1:
; MMR5FP64: # %bb.0: # %entry
-; MMR5FP64-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Expr:(%hi(a))>>
-; MMR5FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR5FP64-NEXT: lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Expr:(%lo(a))>>
+; MMR5FP64-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST4:]] LUi_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1:]]>
+; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4028,a)>>
+; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5:]] JR_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>
+; MMR5FP64-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST6:]] LBu_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG3:]]>
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4031,a)>>
;
; MIPS32R5FP643-LABEL: f1:
; MIPS32R5FP643: # %bb.0: # %entry
-; MIPS32R5FP643-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Expr:(%hi(a))>>
-; MIPS32R5FP643-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32R5FP643-NEXT: lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Expr:(%lo(a))>>
+; MIPS32R5FP643-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST1:]] LUi
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1:]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4028,a)>>
+; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>
+; MIPS32R5FP643-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST3:]] LBu
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG3:]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4031,a)>>
entry:
%0 = load i8, ptr @a
ret i8 %0
@@ -188,161 +188,161 @@ entry:
define i32 @f2() {
; MIPS32-LABEL: f2:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Expr:(%hi(a))>>
-; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32-NEXT: lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Expr:(%lo(a))>>
+; MIPS32-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST1]] LUi
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32-NEXT: # <MCOperand Expr:specifier(4028,a)>>
+; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST13:]] LB
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32-NEXT: # <MCOperand Expr:specifier(4031,a)>>
;
; MMR3-LABEL: f2:
; MMR3: # %bb.0: # %entry
-; MMR3-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Expr:(%hi(a))>>
-; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR3-NEXT: lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Expr:(%lo(a))>>
+; MMR3-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR3-NEXT: # <MCOperand Expr:specifier(4028,a)>>
+; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MMR3-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST14:]] LB_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR3-NEXT: # <MCOperand Expr:specifier(4031,a)>>
;
; MIPS32R6-LABEL: f2:
; MIPS32R6: # %bb.0: # %entry
-; MIPS32R6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(a))>>
-; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32R6-NEXT: lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(a))>>
+; MIPS32R6-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST1]] LUi
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4028,a)>>
+; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32R6-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST13:]] LB
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4031,a)>>
;
; MMR6-LABEL: f2:
; MMR6: # %bb.0: # %entry
-; MMR6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Expr:(%hi(a))>>
-; MMR6-NEXT: lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Expr:(%lo(a))>>
-; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; MMR6-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR6-NEXT: # <MCOperand Expr:specifier(4028,a)>>
+; MMR6-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST14:]] LB_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR6-NEXT: # <MCOperand Expr:specifier(4031,a)>>
+; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
;
; MIPS3-LABEL: f2:
; MIPS3: # %bb.0: # %entry
-; MIPS3-NEXT: lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%highest(a))>>
-; MIPS3-NEXT: daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%higher(a))>>
-; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT: lui $1, %highest(a) # <MCInst #[[#MCINST9]] LUi64
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4030,a)>>
+; MIPS3-NEXT: daddiu $1, $1, %higher(a) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4029,a)>>
+; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS3-NEXT: # <MCOperand Imm:16>>
-; MIPS3-NEXT: daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%hi(a))>>
-; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT: daddiu $1, $1, %hi(a) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4028,a)>>
+; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS3-NEXT: # <MCOperand Imm:16>>
-; MIPS3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS3-NEXT: lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%lo(a))>>
+; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS3-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST13:]] LB
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4031,a)>>
;
; MIPS64-LABEL: f2:
; MIPS64: # %bb.0: # %entry
-; MIPS64-NEXT: lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%highest(a))>>
-; MIPS64-NEXT: daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%higher(a))>>
-; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT: lui $1, %highest(a) # <MCInst #[[#MCINST9]] LUi64
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4030,a)>>
+; MIPS64-NEXT: daddiu $1, $1, %higher(a) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4029,a)>>
+; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64-NEXT: # <MCOperand Imm:16>>
-; MIPS64-NEXT: daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%hi(a))>>
-; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT: daddiu $1, $1, %hi(a) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4028,a)>>
+; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64-NEXT: # <MCOperand Imm:16>>
-; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS64-NEXT: lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%lo(a))>>
+; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS64-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST13:]] LB
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4031,a)>>
;
; MIPS64R6-LABEL: f2:
; MIPS64R6: # %bb.0: # %entry
-; MIPS64R6-NEXT: lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(a))>>
-; MIPS64R6-NEXT: daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(a))>>
-; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT: lui $1, %highest(a) # <MCInst #[[#MCINST9]] LUi64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4030,a)>>
+; MIPS64R6-NEXT: daddiu $1, $1, %higher(a) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4029,a)>>
+; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
-; MIPS64R6-NEXT: daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(a))>>
-; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT: daddiu $1, $1, %hi(a) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4028,a)>>
+; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
-; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS64R6-NEXT: lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(a))>>
+; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST12]] JALR64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG7]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS64R6-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST13:]] LB
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4031,a)>>
;
; MMR5FP64-LABEL: f2:
; MMR5FP64: # %bb.0: # %entry
-; MMR5FP64-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Expr:(%hi(a))>>
-; MMR5FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR5FP64-NEXT: lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Expr:(%lo(a))>>
+; MMR5FP64-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4028,a)>>
+; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MMR5FP64-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST14:]] LB_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4031,a)>>
;
; MIPS32R5FP643-LABEL: f2:
; MIPS32R5FP643: # %bb.0: # %entry
-; MIPS32R5FP643-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Expr:(%hi(a))>>
-; MIPS32R5FP643-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32R5FP643-NEXT: lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Expr:(%lo(a))>>
+; MIPS32R5FP643-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST1]] LUi
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4028,a)>>
+; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32R5FP643-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST13:]] LB
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4031,a)>>
entry:
%0 = load i8, ptr @a
%1 = sext i8 %0 to i32
@@ -352,161 +352,161 @@ entry:
define i16 @f3() {
; MIPS32-LABEL: f3:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Expr:(%hi(b))>>
-; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32-NEXT: lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Expr:(%lo(b))>>
+; MIPS32-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST1]] LUi
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32-NEXT: # <MCOperand Expr:specifier(4028,b)>>
+; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST15:]] LHu
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32-NEXT: # <MCOperand Expr:specifier(4031,b)>>
;
; MMR3-LABEL: f3:
; MMR3: # %bb.0: # %entry
-; MMR3-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Expr:(%hi(b))>>
-; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR3-NEXT: lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Expr:(%lo(b))>>
+; MMR3-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR3-NEXT: # <MCOperand Expr:specifier(4028,b)>>
+; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MMR3-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST16:]] LHu_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR3-NEXT: # <MCOperand Expr:specifier(4031,b)>>
;
; MIPS32R6-LABEL: f3:
; MIPS32R6: # %bb.0: # %entry
-; MIPS32R6-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(b))>>
-; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32R6-NEXT: lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(b))>>
+; MIPS32R6-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST1]] LUi
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4028,b)>>
+; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32R6-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST15:]] LHu
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4031,b)>>
;
; MMR6-LABEL: f3:
; MMR6: # %bb.0: # %entry
-; MMR6-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Expr:(%hi(b))>>
-; MMR6-NEXT: lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Expr:(%lo(b))>>
-; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; MMR6-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR6-NEXT: # <MCOperand Expr:specifier(4028,b)>>
+; MMR6-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST16:]] LHu_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR6-NEXT: # <MCOperand Expr:specifier(4031,b)>>
+; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
;
; MIPS3-LABEL: f3:
; MIPS3: # %bb.0: # %entry
-; MIPS3-NEXT: lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%highest(b))>>
-; MIPS3-NEXT: daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%higher(b))>>
-; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT: lui $1, %highest(b) # <MCInst #[[#MCINST9]] LUi64
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4030,b)>>
+; MIPS3-NEXT: daddiu $1, $1, %higher(b) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4029,b)>>
+; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS3-NEXT: # <MCOperand Imm:16>>
-; MIPS3-NEXT: daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%hi(b))>>
-; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT: daddiu $1, $1, %hi(b) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4028,b)>>
+; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS3-NEXT: # <MCOperand Imm:16>>
-; MIPS3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS3-NEXT: lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%lo(b))>>
+; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS3-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST15:]] LHu
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4031,b)>>
;
; MIPS64-LABEL: f3:
; MIPS64: # %bb.0: # %entry
-; MIPS64-NEXT: lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%highest(b))>>
-; MIPS64-NEXT: daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%higher(b))>>
-; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT: lui $1, %highest(b) # <MCInst #[[#MCINST9]] LUi64
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4030,b)>>
+; MIPS64-NEXT: daddiu $1, $1, %higher(b) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4029,b)>>
+; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64-NEXT: # <MCOperand Imm:16>>
-; MIPS64-NEXT: daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%hi(b))>>
-; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT: daddiu $1, $1, %hi(b) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4028,b)>>
+; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64-NEXT: # <MCOperand Imm:16>>
-; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS64-NEXT: lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%lo(b))>>
+; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS64-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST15:]] LHu
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4031,b)>>
;
; MIPS64R6-LABEL: f3:
; MIPS64R6: # %bb.0: # %entry
-; MIPS64R6-NEXT: lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(b))>>
-; MIPS64R6-NEXT: daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(b))>>
-; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT: lui $1, %highest(b) # <MCInst #[[#MCINST9]] LUi64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4030,b)>>
+; MIPS64R6-NEXT: daddiu $1, $1, %higher(b) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4029,b)>>
+; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
-; MIPS64R6-NEXT: daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(b))>>
-; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT: daddiu $1, $1, %hi(b) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4028,b)>>
+; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
-; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS64R6-NEXT: lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(b))>>
+; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST12]] JALR64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG7]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS64R6-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST15:]] LHu
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4031,b)>>
;
; MMR5FP64-LABEL: f3:
; MMR5FP64: # %bb.0: # %entry
-; MMR5FP64-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Expr:(%hi(b))>>
-; MMR5FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR5FP64-NEXT: lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Expr:(%lo(b))>>
+; MMR5FP64-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4028,b)>>
+; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MMR5FP64-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST16:]] LHu_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4031,b)>>
;
; MIPS32R5FP643-LABEL: f3:
; MIPS32R5FP643: # %bb.0: # %entry
-; MIPS32R5FP643-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Expr:(%hi(b))>>
-; MIPS32R5FP643-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32R5FP643-NEXT: lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Expr:(%lo(b))>>
+; MIPS32R5FP643-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST1]] LUi
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4028,b)>>
+; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32R5FP643-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST15:]] LHu
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4031,b)>>
entry:
%0 = load i16, ptr @b
ret i16 %0
@@ -515,161 +515,161 @@ entry:
define i32 @f4() {
; MIPS32-LABEL: f4:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Expr:(%hi(b))>>
-; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32-NEXT: lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Expr:(%lo(b))>>
+; MIPS32-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST1]] LUi
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32-NEXT: # <MCOperand Expr:specifier(4028,b)>>
+; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST17:]] LH
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32-NEXT: # <MCOperand Expr:specifier(4031,b)>>
;
; MMR3-LABEL: f4:
; MMR3: # %bb.0: # %entry
-; MMR3-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Expr:(%hi(b))>>
-; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR3-NEXT: lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Expr:(%lo(b))>>
+; MMR3-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR3-NEXT: # <MCOperand Expr:specifier(4028,b)>>
+; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MMR3-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST18:]] LH_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR3-NEXT: # <MCOperand Expr:specifier(4031,b)>>
;
; MIPS32R6-LABEL: f4:
; MIPS32R6: # %bb.0: # %entry
-; MIPS32R6-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(b))>>
-; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32R6-NEXT: lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(b))>>
+; MIPS32R6-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST1]] LUi
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4028,b)>>
+; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32R6-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST17:]] LH
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4031,b)>>
;
; MMR6-LABEL: f4:
; MMR6: # %bb.0: # %entry
-; MMR6-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Expr:(%hi(b))>>
-; MMR6-NEXT: lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Expr:(%lo(b))>>
-; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; MMR6-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR6-NEXT: # <MCOperand Expr:specifier(4028,b)>>
+; MMR6-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST18:]] LH_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR6-NEXT: # <MCOperand Expr:specifier(4031,b)>>
+; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
;
; MIPS3-LABEL: f4:
; MIPS3: # %bb.0: # %entry
-; MIPS3-NEXT: lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%highest(b))>>
-; MIPS3-NEXT: daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%higher(b))>>
-; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT: lui $1, %highest(b) # <MCInst #[[#MCINST9]] LUi64
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4030,b)>>
+; MIPS3-NEXT: daddiu $1, $1, %higher(b) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4029,b)>>
+; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS3-NEXT: # <MCOperand Imm:16>>
-; MIPS3-NEXT: daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%hi(b))>>
-; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT: daddiu $1, $1, %hi(b) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4028,b)>>
+; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS3-NEXT: # <MCOperand Imm:16>>
-; MIPS3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS3-NEXT: lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%lo(b))>>
+; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS3-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST17:]] LH
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4031,b)>>
;
; MIPS64-LABEL: f4:
; MIPS64: # %bb.0: # %entry
-; MIPS64-NEXT: lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%highest(b))>>
-; MIPS64-NEXT: daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%higher(b))>>
-; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT: lui $1, %highest(b) # <MCInst #[[#MCINST9]] LUi64
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4030,b)>>
+; MIPS64-NEXT: daddiu $1, $1, %higher(b) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4029,b)>>
+; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64-NEXT: # <MCOperand Imm:16>>
-; MIPS64-NEXT: daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%hi(b))>>
-; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT: daddiu $1, $1, %hi(b) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4028,b)>>
+; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64-NEXT: # <MCOperand Imm:16>>
-; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS64-NEXT: lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%lo(b))>>
+; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS64-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST17:]] LH
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4031,b)>>
;
; MIPS64R6-LABEL: f4:
; MIPS64R6: # %bb.0: # %entry
-; MIPS64R6-NEXT: lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(b))>>
-; MIPS64R6-NEXT: daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(b))>>
-; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT: lui $1, %highest(b) # <MCInst #[[#MCINST9]] LUi64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4030,b)>>
+; MIPS64R6-NEXT: daddiu $1, $1, %higher(b) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4029,b)>>
+; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
-; MIPS64R6-NEXT: daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(b))>>
-; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT: daddiu $1, $1, %hi(b) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4028,b)>>
+; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
-; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS64R6-NEXT: lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(b))>>
+; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST12]] JALR64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG7]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS64R6-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST17:]] LH
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4031,b)>>
;
; MMR5FP64-LABEL: f4:
; MMR5FP64: # %bb.0: # %entry
-; MMR5FP64-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Expr:(%hi(b))>>
-; MMR5FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR5FP64-NEXT: lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Expr:(%lo(b))>>
+; MMR5FP64-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4028,b)>>
+; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MMR5FP64-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST18:]] LH_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4031,b)>>
;
; MIPS32R5FP643-LABEL: f4:
; MIPS32R5FP643: # %bb.0: # %entry
-; MIPS32R5FP643-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Expr:(%hi(b))>>
-; MIPS32R5FP643-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32R5FP643-NEXT: lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Expr:(%lo(b))>>
+; MIPS32R5FP643-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST1]] LUi
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4028,b)>>
+; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32R5FP643-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST17:]] LH
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4031,b)>>
entry:
%0 = load i16, ptr @b
%1 = sext i16 %0 to i32
@@ -679,161 +679,161 @@ entry:
define i32 @f5() {
; MIPS32-LABEL: f5:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Expr:(%lo(c))>>
+; MIPS32-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST19:]] LW
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32-NEXT: # <MCOperand Expr:specifier(4031,c)>>
;
; MMR3-LABEL: f5:
; MMR3: # %bb.0: # %entry
-; MMR3-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR3-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Expr:(%lo(c))>>
+; MMR3-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR3-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MMR3-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST20:]] LW_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR3-NEXT: # <MCOperand Expr:specifier(4031,c)>>
;
; MIPS32R6-LABEL: f5:
; MIPS32R6: # %bb.0: # %entry
-; MIPS32R6-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32R6-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(c))>>
+; MIPS32R6-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32R6-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST19:]] LW
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4031,c)>>
;
; MMR6-LABEL: f5:
; MMR6: # %bb.0: # %entry
-; MMR6-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MMR6-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Expr:(%lo(c))>>
-; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; MMR6-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR6-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MMR6-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST20:]] LW_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR6-NEXT: # <MCOperand Expr:specifier(4031,c)>>
+; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
;
; MIPS3-LABEL: f5:
; MIPS3: # %bb.0: # %entry
-; MIPS3-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%highest(c))>>
-; MIPS3-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%higher(c))>>
-; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT: lui $1, %highest(c) # <MCInst #[[#MCINST9]] LUi64
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4030,c)>>
+; MIPS3-NEXT: daddiu $1, $1, %higher(c) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4029,c)>>
+; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS3-NEXT: # <MCOperand Imm:16>>
-; MIPS3-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT: daddiu $1, $1, %hi(c) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS3-NEXT: # <MCOperand Imm:16>>
-; MIPS3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS3-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%lo(c))>>
+; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS3-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST19:]] LW
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4031,c)>>
;
; MIPS64-LABEL: f5:
; MIPS64: # %bb.0: # %entry
-; MIPS64-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%highest(c))>>
-; MIPS64-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%higher(c))>>
-; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT: lui $1, %highest(c) # <MCInst #[[#MCINST9]] LUi64
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4030,c)>>
+; MIPS64-NEXT: daddiu $1, $1, %higher(c) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4029,c)>>
+; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64-NEXT: # <MCOperand Imm:16>>
-; MIPS64-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT: daddiu $1, $1, %hi(c) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64-NEXT: # <MCOperand Imm:16>>
-; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS64-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%lo(c))>>
+; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS64-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST19:]] LW
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4031,c)>>
;
; MIPS64R6-LABEL: f5:
; MIPS64R6: # %bb.0: # %entry
-; MIPS64R6-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(c))>>
-; MIPS64R6-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(c))>>
-; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT: lui $1, %highest(c) # <MCInst #[[#MCINST9]] LUi64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4030,c)>>
+; MIPS64R6-NEXT: daddiu $1, $1, %higher(c) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4029,c)>>
+; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
-; MIPS64R6-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT: daddiu $1, $1, %hi(c) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
-; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS64R6-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(c))>>
+; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST12]] JALR64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG7]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS64R6-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST19:]] LW
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4031,c)>>
;
; MMR5FP64-LABEL: f5:
; MMR5FP64: # %bb.0: # %entry
-; MMR5FP64-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MMR5FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR5FP64-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Expr:(%lo(c))>>
+; MMR5FP64-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MMR5FP64-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST20:]] LW_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4031,c)>>
;
; MIPS32R5FP643-LABEL: f5:
; MIPS32R5FP643: # %bb.0: # %entry
-; MIPS32R5FP643-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MIPS32R5FP643-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32R5FP643-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Expr:(%lo(c))>>
+; MIPS32R5FP643-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32R5FP643-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST19:]] LW
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4031,c)>>
entry:
%0 = load i32, ptr @c
ret i32 %0
@@ -842,181 +842,181 @@ entry:
define i64 @f6() {
; MIPS32-LABEL: f6:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MIPS32-NEXT: lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Expr:(%lo(c))>>
-; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32-NEXT: addiu $2, $zero, 0 # <MCInst #{{[0-9]+}} ADDiu
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MIPS32-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST19]] LW
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG8:]]>
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32-NEXT: # <MCOperand Expr:specifier(4031,c)>>
+; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32-NEXT: addiu $2, $zero, 0 # <MCInst #[[#MCINST21:]] ADDiu
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG4:]]>
; MIPS32-NEXT: # <MCOperand Imm:0>>
;
; MMR3-LABEL: f6:
; MMR3: # %bb.0: # %entry
-; MMR3-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MMR3-NEXT: li16 $2, 0 # <MCInst #{{[0-9]+}} LI16_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MMR3-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR3-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MMR3-NEXT: li16 $2, 0 # <MCInst #[[#MCINST22:]] LI16_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG3]]>
; MMR3-NEXT: # <MCOperand Imm:0>>
-; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR3-NEXT: lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Expr:(%lo(c))>>
+; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MMR3-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST20]] LW_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG8:]]>
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR3-NEXT: # <MCOperand Expr:specifier(4031,c)>>
;
; MIPS32R6-LABEL: f6:
; MIPS32R6: # %bb.0: # %entry
-; MIPS32R6-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MIPS32R6-NEXT: lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(c))>>
-; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32R6-NEXT: addiu $2, $zero, 0 # <MCInst #{{[0-9]+}} ADDiu
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R6-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MIPS32R6-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST19]] LW
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG8:]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4031,c)>>
+; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32R6-NEXT: addiu $2, $zero, 0 # <MCInst #[[#MCINST21:]] ADDiu
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>
; MIPS32R6-NEXT: # <MCOperand Imm:0>>
;
; MMR6-LABEL: f6:
; MMR6: # %bb.0: # %entry
-; MMR6-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MMR6-NEXT: lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Expr:(%lo(c))>>
-; MMR6-NEXT: li16 $2, 0 # <MCInst #{{[0-9]+}} LI16_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR6-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MMR6-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST20]] LW_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG8:]]>
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR6-NEXT: # <MCOperand Expr:specifier(4031,c)>>
+; MMR6-NEXT: li16 $2, 0 # <MCInst #[[#MCINST22:]] LI16_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3]]>
; MMR6-NEXT: # <MCOperand Imm:0>>
-; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
;
; MIPS3-LABEL: f6:
; MIPS3: # %bb.0: # %entry
-; MIPS3-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%highest(c))>>
-; MIPS3-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%higher(c))>>
-; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT: lui $1, %highest(c) # <MCInst #[[#MCINST9]] LUi64
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4030,c)>>
+; MIPS3-NEXT: daddiu $1, $1, %higher(c) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4029,c)>>
+; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS3-NEXT: # <MCOperand Imm:16>>
-; MIPS3-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT: daddiu $1, $1, %hi(c) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS3-NEXT: # <MCOperand Imm:16>>
-; MIPS3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS3-NEXT: lwu $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LWu
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%lo(c))>>
+; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS3-NEXT: lwu $2, %lo(c)($1) # <MCInst #[[#MCINST23:]] LWu
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG9:]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4031,c)>>
;
; MIPS64-LABEL: f6:
; MIPS64: # %bb.0: # %entry
-; MIPS64-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%highest(c))>>
-; MIPS64-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%higher(c))>>
-; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT: lui $1, %highest(c) # <MCInst #[[#MCINST9]] LUi64
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4030,c)>>
+; MIPS64-NEXT: daddiu $1, $1, %higher(c) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4029,c)>>
+; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64-NEXT: # <MCOperand Imm:16>>
-; MIPS64-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT: daddiu $1, $1, %hi(c) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64-NEXT: # <MCOperand Imm:16>>
-; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS64-NEXT: lwu $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LWu
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%lo(c))>>
+; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS64-NEXT: lwu $2, %lo(c)($1) # <MCInst #[[#MCINST23:]] LWu
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG9:]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4031,c)>>
;
; MIPS64R6-LABEL: f6:
; MIPS64R6: # %bb.0: # %entry
-; MIPS64R6-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(c))>>
-; MIPS64R6-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(c))>>
-; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT: lui $1, %highest(c) # <MCInst #[[#MCINST9]] LUi64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4030,c)>>
+; MIPS64R6-NEXT: daddiu $1, $1, %higher(c) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4029,c)>>
+; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
-; MIPS64R6-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT: daddiu $1, $1, %hi(c) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
-; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS64R6-NEXT: lwu $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LWu
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(c))>>
+; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST12]] JALR64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG7]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS64R6-NEXT: lwu $2, %lo(c)($1) # <MCInst #[[#MCINST23:]] LWu
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG9:]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4031,c)>>
;
; MMR5FP64-LABEL: f6:
; MMR5FP64: # %bb.0: # %entry
-; MMR5FP64-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MMR5FP64-NEXT: li16 $2, 0 # <MCInst #{{[0-9]+}} LI16_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MMR5FP64-NEXT: li16 $2, 0 # <MCInst #[[#MCINST22:]] LI16_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG3]]>
; MMR5FP64-NEXT: # <MCOperand Imm:0>>
-; MMR5FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR5FP64-NEXT: lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Expr:(%lo(c))>>
+; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MMR5FP64-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST20]] LW_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG8:]]>
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4031,c)>>
;
; MIPS32R5FP643-LABEL: f6:
; MIPS32R5FP643: # %bb.0: # %entry
-; MIPS32R5FP643-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MIPS32R5FP643-NEXT: lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Expr:(%lo(c))>>
-; MIPS32R5FP643-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32R5FP643-NEXT: addiu $2, $zero, 0 # <MCInst #{{[0-9]+}} ADDiu
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MIPS32R5FP643-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST19]] LW
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG8:]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4031,c)>>
+; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32R5FP643-NEXT: addiu $2, $zero, 0 # <MCInst #[[#MCINST21:]] ADDiu
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG4:]]>
; MIPS32R5FP643-NEXT: # <MCOperand Imm:0>>
entry:
%0 = load i32, ptr @c
@@ -1027,184 +1027,184 @@ entry:
define i64 @f7() {
; MIPS32-LABEL: f7:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MIPS32-NEXT: lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Expr:(%lo(c))>>
-; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32-NEXT: sra $2, $3, 31 # <MCInst #{{[0-9]+}} SRA
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MIPS32-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST19]] LW
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG8]]>
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32-NEXT: # <MCOperand Expr:specifier(4031,c)>>
+; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32-NEXT: sra $2, $3, 31 # <MCInst #[[#MCINST24:]] SRA
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG8]]>
; MIPS32-NEXT: # <MCOperand Imm:31>>
;
; MMR3-LABEL: f7:
; MMR3: # %bb.0: # %entry
-; MMR3-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MMR3-NEXT: lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Expr:(%lo(c))>>
-; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR3-NEXT: sra $2, $3, 31 # <MCInst #{{[0-9]+}} SRA_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MMR3-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR3-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MMR3-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST20]] LW_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG8]]>
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR3-NEXT: # <MCOperand Expr:specifier(4031,c)>>
+; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MMR3-NEXT: sra $2, $3, 31 # <MCInst #[[#MCINST25:]] SRA_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG8]]>
; MMR3-NEXT: # <MCOperand Imm:31>>
;
; MIPS32R6-LABEL: f7:
; MIPS32R6: # %bb.0: # %entry
-; MIPS32R6-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MIPS32R6-NEXT: lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(c))>>
-; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32R6-NEXT: sra $2, $3, 31 # <MCInst #{{[0-9]+}} SRA
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R6-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MIPS32R6-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST19]] LW
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG8]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4031,c)>>
+; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32R6-NEXT: sra $2, $3, 31 # <MCInst #[[#MCINST24:]] SRA
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG8]]>
; MIPS32R6-NEXT: # <MCOperand Imm:31>>
;
; MMR6-LABEL: f7:
; MMR6: # %bb.0: # %entry
-; MMR6-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MMR6-NEXT: lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Expr:(%lo(c))>>
-; MMR6-NEXT: sra $2, $3, 31 # <MCInst #{{[0-9]+}} SRA_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR6-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MMR6-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST20]] LW_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG8]]>
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR6-NEXT: # <MCOperand Expr:specifier(4031,c)>>
+; MMR6-NEXT: sra $2, $3, 31 # <MCInst #[[#MCINST25:]] SRA_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG8]]>
; MMR6-NEXT: # <MCOperand Imm:31>>
-; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
;
; MIPS3-LABEL: f7:
; MIPS3: # %bb.0: # %entry
-; MIPS3-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%highest(c))>>
-; MIPS3-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%higher(c))>>
-; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT: lui $1, %highest(c) # <MCInst #[[#MCINST9]] LUi64
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4030,c)>>
+; MIPS3-NEXT: daddiu $1, $1, %higher(c) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4029,c)>>
+; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS3-NEXT: # <MCOperand Imm:16>>
-; MIPS3-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT: daddiu $1, $1, %hi(c) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS3-NEXT: # <MCOperand Imm:16>>
-; MIPS3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS3-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW64
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%lo(c))>>
+; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS3-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST26:]] LW64
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG9]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4031,c)>>
;
; MIPS64-LABEL: f7:
; MIPS64: # %bb.0: # %entry
-; MIPS64-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%highest(c))>>
-; MIPS64-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%higher(c))>>
-; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT: lui $1, %highest(c) # <MCInst #[[#MCINST9]] LUi64
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4030,c)>>
+; MIPS64-NEXT: daddiu $1, $1, %higher(c) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4029,c)>>
+; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64-NEXT: # <MCOperand Imm:16>>
-; MIPS64-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT: daddiu $1, $1, %hi(c) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64-NEXT: # <MCOperand Imm:16>>
-; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS64-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW64
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%lo(c))>>
+; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS64-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST26:]] LW64
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG9]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4031,c)>>
;
; MIPS64R6-LABEL: f7:
; MIPS64R6: # %bb.0: # %entry
-; MIPS64R6-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(c))>>
-; MIPS64R6-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(c))>>
-; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT: lui $1, %highest(c) # <MCInst #[[#MCINST9]] LUi64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4030,c)>>
+; MIPS64R6-NEXT: daddiu $1, $1, %higher(c) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4029,c)>>
+; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
-; MIPS64R6-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT: daddiu $1, $1, %hi(c) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
-; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS64R6-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(c))>>
+; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST12]] JALR64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG7]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS64R6-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST26:]] LW64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG9]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4031,c)>>
;
; MMR5FP64-LABEL: f7:
; MMR5FP64: # %bb.0: # %entry
-; MMR5FP64-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MMR5FP64-NEXT: lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Expr:(%lo(c))>>
-; MMR5FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR5FP64-NEXT: sra $2, $3, 31 # <MCInst #{{[0-9]+}} SRA_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MMR5FP64-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST20]] LW_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG8]]>
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4031,c)>>
+; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MMR5FP64-NEXT: sra $2, $3, 31 # <MCInst #[[#MCINST25:]] SRA_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG8]]>
; MMR5FP64-NEXT: # <MCOperand Imm:31>>
;
; MIPS32R5FP643-LABEL: f7:
; MIPS32R5FP643: # %bb.0: # %entry
-; MIPS32R5FP643-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MIPS32R5FP643-NEXT: lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Expr:(%lo(c))>>
-; MIPS32R5FP643-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32R5FP643-NEXT: sra $2, $3, 31 # <MCInst #{{[0-9]+}} SRA
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MIPS32R5FP643-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST19]] LW
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG8]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4031,c)>>
+; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32R5FP643-NEXT: sra $2, $3, 31 # <MCInst #[[#MCINST24:]] SRA
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG8]]>
; MIPS32R5FP643-NEXT: # <MCOperand Imm:31>>
entry:
%0 = load i32, ptr @c
@@ -1215,161 +1215,161 @@ entry:
define float @f8() {
; MIPS32-LABEL: f8:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Expr:(%hi(e))>>
-; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Expr:(%lo(e))>>
+; MIPS32-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST1]] LUi
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32-NEXT: # <MCOperand Expr:specifier(4028,e)>>
+; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #[[#MCINST27:]] LWC1
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG10:]]>
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32-NEXT: # <MCOperand Expr:specifier(4031,e)>>
;
; MMR3-LABEL: f8:
; MMR3: # %bb.0: # %entry
-; MMR3-NEXT: lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Expr:(%hi(e))>>
-; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR3-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Expr:(%lo(e))>>
+; MMR3-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR3-NEXT: # <MCOperand Expr:specifier(4028,e)>>
+; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MMR3-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #[[#MCINST28:]] LWC1_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG10:]]>
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR3-NEXT: # <MCOperand Expr:specifier(4031,e)>>
;
; MIPS32R6-LABEL: f8:
; MIPS32R6: # %bb.0: # %entry
-; MIPS32R6-NEXT: lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(e))>>
-; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32R6-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(e))>>
+; MIPS32R6-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST1]] LUi
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4028,e)>>
+; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32R6-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #[[#MCINST27:]] LWC1
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG10:]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4031,e)>>
;
; MMR6-LABEL: f8:
; MMR6: # %bb.0: # %entry
-; MMR6-NEXT: lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Expr:(%hi(e))>>
-; MMR6-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Expr:(%lo(e))>>
-; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; MMR6-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR6-NEXT: # <MCOperand Expr:specifier(4028,e)>>
+; MMR6-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #[[#MCINST28:]] LWC1_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG10:]]>
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR6-NEXT: # <MCOperand Expr:specifier(4031,e)>>
+; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
;
; MIPS3-LABEL: f8:
; MIPS3: # %bb.0: # %entry
-; MIPS3-NEXT: lui $1, %highest(e) # <MCInst #{{[0-9]+}} LUi64
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%highest(e))>>
-; MIPS3-NEXT: daddiu $1, $1, %higher(e) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%higher(e))>>
-; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT: lui $1, %highest(e) # <MCInst #[[#MCINST9]] LUi64
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4030,e)>>
+; MIPS3-NEXT: daddiu $1, $1, %higher(e) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4029,e)>>
+; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS3-NEXT: # <MCOperand Imm:16>>
-; MIPS3-NEXT: daddiu $1, $1, %hi(e) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%hi(e))>>
-; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT: daddiu $1, $1, %hi(e) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4028,e)>>
+; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS3-NEXT: # <MCOperand Imm:16>>
-; MIPS3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS3-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%lo(e))>>
+; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS3-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #[[#MCINST27:]] LWC1
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG10:]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4031,e)>>
;
; MIPS64-LABEL: f8:
; MIPS64: # %bb.0: # %entry
-; MIPS64-NEXT: lui $1, %highest(e) # <MCInst #{{[0-9]+}} LUi64
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%highest(e))>>
-; MIPS64-NEXT: daddiu $1, $1, %higher(e) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%higher(e))>>
-; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT: lui $1, %highest(e) # <MCInst #[[#MCINST9]] LUi64
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4030,e)>>
+; MIPS64-NEXT: daddiu $1, $1, %higher(e) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4029,e)>>
+; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64-NEXT: # <MCOperand Imm:16>>
-; MIPS64-NEXT: daddiu $1, $1, %hi(e) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%hi(e))>>
-; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT: daddiu $1, $1, %hi(e) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4028,e)>>
+; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64-NEXT: # <MCOperand Imm:16>>
-; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS64-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%lo(e))>>
+; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS64-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #[[#MCINST27:]] LWC1
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG10:]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4031,e)>>
;
; MIPS64R6-LABEL: f8:
; MIPS64R6: # %bb.0: # %entry
-; MIPS64R6-NEXT: lui $1, %highest(e) # <MCInst #{{[0-9]+}} LUi64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(e))>>
-; MIPS64R6-NEXT: daddiu $1, $1, %higher(e) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(e))>>
-; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT: lui $1, %highest(e) # <MCInst #[[#MCINST9]] LUi64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4030,e)>>
+; MIPS64R6-NEXT: daddiu $1, $1, %higher(e) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4029,e)>>
+; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
-; MIPS64R6-NEXT: daddiu $1, $1, %hi(e) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(e))>>
-; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT: daddiu $1, $1, %hi(e) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4028,e)>>
+; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
-; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS64R6-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(e))>>
+; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST12]] JALR64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG7]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS64R6-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #[[#MCINST27:]] LWC1
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG10:]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4031,e)>>
;
; MMR5FP64-LABEL: f8:
; MMR5FP64: # %bb.0: # %entry
-; MMR5FP64-NEXT: lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Expr:(%hi(e))>>
-; MMR5FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR5FP64-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Expr:(%lo(e))>>
+; MMR5FP64-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4028,e)>>
+; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MMR5FP64-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #[[#MCINST28:]] LWC1_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG10:]]>
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4031,e)>>
;
; MIPS32R5FP643-LABEL: f8:
; MIPS32R5FP643: # %bb.0: # %entry
-; MIPS32R5FP643-NEXT: lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Expr:(%hi(e))>>
-; MIPS32R5FP643-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32R5FP643-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Expr:(%lo(e))>>
+; MIPS32R5FP643-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST1]] LUi
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4028,e)>>
+; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32R5FP643-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #[[#MCINST27:]] LWC1
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG10:]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4031,e)>>
entry:
%0 = load float, ptr @e
ret float %0
@@ -1378,161 +1378,161 @@ entry:
define double @f9() {
; MIPS32-LABEL: f9:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Expr:(%hi(f))>>
-; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC1
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Expr:(%lo(f))>>
+; MIPS32-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST1]] LUi
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32-NEXT: # <MCOperand Expr:specifier(4028,f)>>
+; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #[[#MCINST29:]] LDC1
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG11:]]>
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32-NEXT: # <MCOperand Expr:specifier(4031,f)>>
;
; MMR3-LABEL: f9:
; MMR3: # %bb.0: # %entry
-; MMR3-NEXT: lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Expr:(%hi(f))>>
-; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR3-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC1_MM_D32
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Expr:(%lo(f))>>
+; MMR3-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR3-NEXT: # <MCOperand Expr:specifier(4028,f)>>
+; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MMR3-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #[[#MCINST30:]] LDC1_MM_D32
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG11:]]>
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR3-NEXT: # <MCOperand Expr:specifier(4031,f)>>
;
; MIPS32R6-LABEL: f9:
; MIPS32R6: # %bb.0: # %entry
-; MIPS32R6-NEXT: lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(f))>>
-; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32R6-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC164
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(f))>>
+; MIPS32R6-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST1]] LUi
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4028,f)>>
+; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32R6-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #[[#MCINST31:]] LDC164
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG12:]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4031,f)>>
;
; MMR6-LABEL: f9:
; MMR6: # %bb.0: # %entry
-; MMR6-NEXT: lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Expr:(%hi(f))>>
-; MMR6-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC1_D64_MMR6
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Expr:(%lo(f))>>
-; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; MMR6-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR6-NEXT: # <MCOperand Expr:specifier(4028,f)>>
+; MMR6-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #[[#MCINST32:]] LDC1_D64_MMR6
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG12:]]>
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR6-NEXT: # <MCOperand Expr:specifier(4031,f)>>
+; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
;
; MIPS3-LABEL: f9:
; MIPS3: # %bb.0: # %entry
-; MIPS3-NEXT: lui $1, %highest(f) # <MCInst #{{[0-9]+}} LUi64
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%highest(f))>>
-; MIPS3-NEXT: daddiu $1, $1, %higher(f) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%higher(f))>>
-; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT: lui $1, %highest(f) # <MCInst #[[#MCINST9]] LUi64
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4030,f)>>
+; MIPS3-NEXT: daddiu $1, $1, %higher(f) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4029,f)>>
+; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS3-NEXT: # <MCOperand Imm:16>>
-; MIPS3-NEXT: daddiu $1, $1, %hi(f) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%hi(f))>>
-; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS3-NEXT: daddiu $1, $1, %hi(f) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4028,f)>>
+; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS3-NEXT: # <MCOperand Imm:16>>
-; MIPS3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS3-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC164
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS3-NEXT: # <MCOperand Expr:(%lo(f))>>
+; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS3-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #[[#MCINST31:]] LDC164
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG12:]]>
+; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS3-NEXT: # <MCOperand Expr:specifier(4031,f)>>
;
; MIPS64-LABEL: f9:
; MIPS64: # %bb.0: # %entry
-; MIPS64-NEXT: lui $1, %highest(f) # <MCInst #{{[0-9]+}} LUi64
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%highest(f))>>
-; MIPS64-NEXT: daddiu $1, $1, %higher(f) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%higher(f))>>
-; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT: lui $1, %highest(f) # <MCInst #[[#MCINST9]] LUi64
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4030,f)>>
+; MIPS64-NEXT: daddiu $1, $1, %higher(f) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4029,f)>>
+; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64-NEXT: # <MCOperand Imm:16>>
-; MIPS64-NEXT: daddiu $1, $1, %hi(f) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%hi(f))>>
-; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64-NEXT: daddiu $1, $1, %hi(f) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4028,f)>>
+; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64-NEXT: # <MCOperand Imm:16>>
-; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS64-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC164
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64-NEXT: # <MCOperand Expr:(%lo(f))>>
+; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS64-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #[[#MCINST31:]] LDC164
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG12:]]>
+; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64-NEXT: # <MCOperand Expr:specifier(4031,f)>>
;
; MIPS64R6-LABEL: f9:
; MIPS64R6: # %bb.0: # %entry
-; MIPS64R6-NEXT: lui $1, %highest(f) # <MCInst #{{[0-9]+}} LUi64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(f))>>
-; MIPS64R6-NEXT: daddiu $1, $1, %higher(f) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(f))>>
-; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT: lui $1, %highest(f) # <MCInst #[[#MCINST9]] LUi64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4030,f)>>
+; MIPS64R6-NEXT: daddiu $1, $1, %higher(f) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4029,f)>>
+; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
-; MIPS64R6-NEXT: daddiu $1, $1, %hi(f) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(f))>>
-; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT: daddiu $1, $1, %hi(f) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4028,f)>>
+; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
-; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS64R6-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC164
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(f))>>
+; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST12]] JALR64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG7]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS64R6-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #[[#MCINST31:]] LDC164
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG12:]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4031,f)>>
;
; MMR5FP64-LABEL: f9:
; MMR5FP64: # %bb.0: # %entry
-; MMR5FP64-NEXT: lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Expr:(%hi(f))>>
-; MMR5FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR5FP64-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC1_MM_D64
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Expr:(%lo(f))>>
+; MMR5FP64-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4028,f)>>
+; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MMR5FP64-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #[[#MCINST33:]] LDC1_MM_D64
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG12:]]>
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4031,f)>>
;
; MIPS32R5FP643-LABEL: f9:
; MIPS32R5FP643: # %bb.0: # %entry
-; MIPS32R5FP643-NEXT: lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Expr:(%hi(f))>>
-; MIPS32R5FP643-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32R5FP643-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC164
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Expr:(%lo(f))>>
+; MIPS32R5FP643-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST1]] LUi
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4028,f)>>
+; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32R5FP643-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #[[#MCINST31:]] LDC164
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG12:]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4031,f)>>
entry:
%0 = load double, ptr @f
ret double %0
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/store.ll b/llvm/test/CodeGen/Mips/llvm-ir/store.ll
index 3922db72f2a7c..880a0f522574b 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/store.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/store.ll
@@ -24,133 +24,133 @@
define void @f1(i8 %a) {
; MIPS32-LABEL: f1:
; MIPS32: # %bb.0:
-; MIPS32-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Expr:(%hi(a))>>
-; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Expr:(%lo(a))>>
+; MIPS32-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST1:]] LUi
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1:]]>
+; MIPS32-NEXT: # <MCOperand Expr:specifier(4028,a)>>
+; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>
+; MIPS32-NEXT: sb $4, %lo(a)($1) # <MCInst #[[#MCINST3:]] SB
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG3:]]>
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32-NEXT: # <MCOperand Expr:specifier(4031,a)>>
;
; MMR3-LABEL: f1:
; MMR3: # %bb.0:
-; MMR3-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Expr:(%hi(a))>>
-; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR3-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Expr:(%lo(a))>>
+; MMR3-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST4:]] LUi_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1:]]>
+; MMR3-NEXT: # <MCOperand Expr:specifier(4028,a)>>
+; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5:]] JR_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>
+; MMR3-NEXT: sb $4, %lo(a)($1) # <MCInst #[[#MCINST6:]] SB_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG3:]]>
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR3-NEXT: # <MCOperand Expr:specifier(4031,a)>>
;
; MIPS32R6-LABEL: f1:
; MIPS32R6: # %bb.0:
-; MIPS32R6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(a))>>
-; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32R6-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(a))>>
+; MIPS32R6-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST1:]] LUi
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1:]]>
+; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4028,a)>>
+; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7:]] JALR
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG4:]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>
+; MIPS32R6-NEXT: sb $4, %lo(a)($1) # <MCInst #[[#MCINST3:]] SB
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG3:]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4031,a)>>
;
; MMR6-LABEL: f1:
; MMR6: # %bb.0:
-; MMR6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Expr:(%hi(a))>>
-; MMR6-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Expr:(%lo(a))>>
-; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; MMR6-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST4:]] LUi_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1:]]>
+; MMR6-NEXT: # <MCOperand Expr:specifier(4028,a)>>
+; MMR6-NEXT: sb $4, %lo(a)($1) # <MCInst #[[#MCINST6:]] SB_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3:]]>
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR6-NEXT: # <MCOperand Expr:specifier(4031,a)>>
+; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8:]] JRC16_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>
;
; MIPS4-LABEL: f1:
; MIPS4: # %bb.0:
-; MIPS4-NEXT: lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Expr:(%highest(a))>>
-; MIPS4-NEXT: daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Expr:(%higher(a))>>
-; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT: lui $1, %highest(a) # <MCInst #[[#MCINST9:]] LUi64
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5:]]>
+; MIPS4-NEXT: # <MCOperand Expr:specifier(4030,a)>>
+; MIPS4-NEXT: daddiu $1, $1, %higher(a) # <MCInst #[[#MCINST10:]] DADDiu
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Expr:specifier(4029,a)>>
+; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11:]] DSLL
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS4-NEXT: # <MCOperand Imm:16>>
-; MIPS4-NEXT: daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Expr:(%hi(a))>>
-; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT: daddiu $1, $1, %hi(a) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Expr:specifier(4028,a)>>
+; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS4-NEXT: # <MCOperand Imm:16>>
-; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS4-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB64
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Expr:(%lo(a))>>
+; MIPS4-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG6:]]>>
+; MIPS4-NEXT: sb $4, %lo(a)($1) # <MCInst #[[#MCINST12:]] SB64
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG7:]]>
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Expr:specifier(4031,a)>>
;
; MIPS64R6-LABEL: f1:
; MIPS64R6: # %bb.0:
-; MIPS64R6-NEXT: lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(a))>>
-; MIPS64R6-NEXT: daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(a))>>
-; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT: lui $1, %highest(a) # <MCInst #[[#MCINST9:]] LUi64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5:]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4030,a)>>
+; MIPS64R6-NEXT: daddiu $1, $1, %higher(a) # <MCInst #[[#MCINST10:]] DADDiu
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4029,a)>>
+; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11:]] DSLL
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
-; MIPS64R6-NEXT: daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(a))>>
-; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT: daddiu $1, $1, %hi(a) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4028,a)>>
+; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
-; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS64R6-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(a))>>
+; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST13:]] JALR64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG8:]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG6:]]>>
+; MIPS64R6-NEXT: sb $4, %lo(a)($1) # <MCInst #[[#MCINST12:]] SB64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG7:]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4031,a)>>
;
; MMR5FP64-LABEL: f1:
; MMR5FP64: # %bb.0:
-; MMR5FP64-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Expr:(%hi(a))>>
-; MMR5FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR5FP64-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Expr:(%lo(a))>>
+; MMR5FP64-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST4:]] LUi_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1:]]>
+; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4028,a)>>
+; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5:]] JR_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>
+; MMR5FP64-NEXT: sb $4, %lo(a)($1) # <MCInst #[[#MCINST6:]] SB_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG3:]]>
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4031,a)>>
;
; MIPS32R5FP643-LABEL: f1:
; MIPS32R5FP643: # %bb.0:
-; MIPS32R5FP643-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Expr:(%hi(a))>>
-; MIPS32R5FP643-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32R5FP643-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Expr:(%lo(a))>>
+; MIPS32R5FP643-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST1:]] LUi
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1:]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4028,a)>>
+; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>
+; MIPS32R5FP643-NEXT: sb $4, %lo(a)($1) # <MCInst #[[#MCINST3:]] SB
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG3:]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4031,a)>>
store i8 %a, ptr @a
ret void
}
@@ -158,133 +158,133 @@ define void @f1(i8 %a) {
define void @f2(i16 %a) {
; MIPS32-LABEL: f2:
; MIPS32: # %bb.0:
-; MIPS32-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Expr:(%hi(b))>>
-; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Expr:(%lo(b))>>
+; MIPS32-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST1]] LUi
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32-NEXT: # <MCOperand Expr:specifier(4028,b)>>
+; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32-NEXT: sh $4, %lo(b)($1) # <MCInst #[[#MCINST14:]] SH
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32-NEXT: # <MCOperand Expr:specifier(4031,b)>>
;
; MMR3-LABEL: f2:
; MMR3: # %bb.0:
-; MMR3-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Expr:(%hi(b))>>
-; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR3-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Expr:(%lo(b))>>
+; MMR3-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR3-NEXT: # <MCOperand Expr:specifier(4028,b)>>
+; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MMR3-NEXT: sh $4, %lo(b)($1) # <MCInst #[[#MCINST15:]] SH_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR3-NEXT: # <MCOperand Expr:specifier(4031,b)>>
;
; MIPS32R6-LABEL: f2:
; MIPS32R6: # %bb.0:
-; MIPS32R6-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(b))>>
-; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32R6-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(b))>>
+; MIPS32R6-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST1]] LUi
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4028,b)>>
+; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32R6-NEXT: sh $4, %lo(b)($1) # <MCInst #[[#MCINST14:]] SH
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4031,b)>>
;
; MMR6-LABEL: f2:
; MMR6: # %bb.0:
-; MMR6-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Expr:(%hi(b))>>
-; MMR6-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Expr:(%lo(b))>>
-; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; MMR6-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR6-NEXT: # <MCOperand Expr:specifier(4028,b)>>
+; MMR6-NEXT: sh $4, %lo(b)($1) # <MCInst #[[#MCINST15:]] SH_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR6-NEXT: # <MCOperand Expr:specifier(4031,b)>>
+; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
;
; MIPS4-LABEL: f2:
; MIPS4: # %bb.0:
-; MIPS4-NEXT: lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Expr:(%highest(b))>>
-; MIPS4-NEXT: daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Expr:(%higher(b))>>
-; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT: lui $1, %highest(b) # <MCInst #[[#MCINST9]] LUi64
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Expr:specifier(4030,b)>>
+; MIPS4-NEXT: daddiu $1, $1, %higher(b) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Expr:specifier(4029,b)>>
+; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS4-NEXT: # <MCOperand Imm:16>>
-; MIPS4-NEXT: daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Expr:(%hi(b))>>
-; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT: daddiu $1, $1, %hi(b) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Expr:specifier(4028,b)>>
+; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS4-NEXT: # <MCOperand Imm:16>>
-; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS4-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH64
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Expr:(%lo(b))>>
+; MIPS4-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS4-NEXT: sh $4, %lo(b)($1) # <MCInst #[[#MCINST16:]] SH64
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG7]]>
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Expr:specifier(4031,b)>>
;
; MIPS64R6-LABEL: f2:
; MIPS64R6: # %bb.0:
-; MIPS64R6-NEXT: lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(b))>>
-; MIPS64R6-NEXT: daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(b))>>
-; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT: lui $1, %highest(b) # <MCInst #[[#MCINST9]] LUi64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4030,b)>>
+; MIPS64R6-NEXT: daddiu $1, $1, %higher(b) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4029,b)>>
+; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
-; MIPS64R6-NEXT: daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(b))>>
-; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT: daddiu $1, $1, %hi(b) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4028,b)>>
+; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
-; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS64R6-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(b))>>
+; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST13]] JALR64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG8]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS64R6-NEXT: sh $4, %lo(b)($1) # <MCInst #[[#MCINST16:]] SH64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG7]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4031,b)>>
;
; MMR5FP64-LABEL: f2:
; MMR5FP64: # %bb.0:
-; MMR5FP64-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Expr:(%hi(b))>>
-; MMR5FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR5FP64-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Expr:(%lo(b))>>
+; MMR5FP64-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4028,b)>>
+; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MMR5FP64-NEXT: sh $4, %lo(b)($1) # <MCInst #[[#MCINST15:]] SH_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4031,b)>>
;
; MIPS32R5FP643-LABEL: f2:
; MIPS32R5FP643: # %bb.0:
-; MIPS32R5FP643-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Expr:(%hi(b))>>
-; MIPS32R5FP643-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32R5FP643-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Expr:(%lo(b))>>
+; MIPS32R5FP643-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST1]] LUi
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4028,b)>>
+; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32R5FP643-NEXT: sh $4, %lo(b)($1) # <MCInst #[[#MCINST14:]] SH
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4031,b)>>
store i16 %a, ptr @b
ret void
}
@@ -292,133 +292,133 @@ define void @f2(i16 %a) {
define void @f3(i32 %a) {
; MIPS32-LABEL: f3:
; MIPS32: # %bb.0:
-; MIPS32-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32-NEXT: sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Expr:(%lo(c))>>
+; MIPS32-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32-NEXT: sw $4, %lo(c)($1) # <MCInst #[[#MCINST17:]] SW
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32-NEXT: # <MCOperand Expr:specifier(4031,c)>>
;
; MMR3-LABEL: f3:
; MMR3: # %bb.0:
-; MMR3-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR3-NEXT: sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Expr:(%lo(c))>>
+; MMR3-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR3-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MMR3-NEXT: sw $4, %lo(c)($1) # <MCInst #[[#MCINST18:]] SW_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR3-NEXT: # <MCOperand Expr:specifier(4031,c)>>
;
; MIPS32R6-LABEL: f3:
; MIPS32R6: # %bb.0:
-; MIPS32R6-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32R6-NEXT: sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(c))>>
+; MIPS32R6-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32R6-NEXT: sw $4, %lo(c)($1) # <MCInst #[[#MCINST17:]] SW
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4031,c)>>
;
; MMR6-LABEL: f3:
; MMR6: # %bb.0:
-; MMR6-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MMR6-NEXT: sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Expr:(%lo(c))>>
-; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; MMR6-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR6-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MMR6-NEXT: sw $4, %lo(c)($1) # <MCInst #[[#MCINST18:]] SW_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR6-NEXT: # <MCOperand Expr:specifier(4031,c)>>
+; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
;
; MIPS4-LABEL: f3:
; MIPS4: # %bb.0:
-; MIPS4-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Expr:(%highest(c))>>
-; MIPS4-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Expr:(%higher(c))>>
-; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT: lui $1, %highest(c) # <MCInst #[[#MCINST9]] LUi64
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Expr:specifier(4030,c)>>
+; MIPS4-NEXT: daddiu $1, $1, %higher(c) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Expr:specifier(4029,c)>>
+; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS4-NEXT: # <MCOperand Imm:16>>
-; MIPS4-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT: daddiu $1, $1, %hi(c) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS4-NEXT: # <MCOperand Imm:16>>
-; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS4-NEXT: sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW64
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Expr:(%lo(c))>>
+; MIPS4-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS4-NEXT: sw $4, %lo(c)($1) # <MCInst #[[#MCINST19:]] SW64
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG7]]>
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Expr:specifier(4031,c)>>
;
; MIPS64R6-LABEL: f3:
; MIPS64R6: # %bb.0:
-; MIPS64R6-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(c))>>
-; MIPS64R6-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(c))>>
-; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT: lui $1, %highest(c) # <MCInst #[[#MCINST9]] LUi64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4030,c)>>
+; MIPS64R6-NEXT: daddiu $1, $1, %higher(c) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4029,c)>>
+; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
-; MIPS64R6-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT: daddiu $1, $1, %hi(c) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
-; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS64R6-NEXT: sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(c))>>
+; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST13]] JALR64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG8]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS64R6-NEXT: sw $4, %lo(c)($1) # <MCInst #[[#MCINST19:]] SW64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG7]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4031,c)>>
;
; MMR5FP64-LABEL: f3:
; MMR5FP64: # %bb.0:
-; MMR5FP64-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MMR5FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR5FP64-NEXT: sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Expr:(%lo(c))>>
+; MMR5FP64-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MMR5FP64-NEXT: sw $4, %lo(c)($1) # <MCInst #[[#MCINST18:]] SW_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4031,c)>>
;
; MIPS32R5FP643-LABEL: f3:
; MIPS32R5FP643: # %bb.0:
-; MIPS32R5FP643-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Expr:(%hi(c))>>
-; MIPS32R5FP643-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32R5FP643-NEXT: sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Expr:(%lo(c))>>
+; MIPS32R5FP643-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4028,c)>>
+; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32R5FP643-NEXT: sw $4, %lo(c)($1) # <MCInst #[[#MCINST17:]] SW
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4031,c)>>
store i32 %a, ptr @c
ret void
}
@@ -426,180 +426,180 @@ define void @f3(i32 %a) {
define void @f4(i64 %a) {
; MIPS32-LABEL: f4:
; MIPS32: # %bb.0:
-; MIPS32-NEXT: lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Expr:(%hi(d))>>
-; MIPS32-NEXT: sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Expr:(%lo(d))>>
-; MIPS32-NEXT: addiu $1, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Expr:(%lo(d))>>
-; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32-NEXT: sw $5, 4($1) # <MCInst #{{[0-9]+}} SW
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32-NEXT: lui $1, %hi(d) # <MCInst #[[#MCINST1]] LUi
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32-NEXT: # <MCOperand Expr:specifier(4028,d)>>
+; MIPS32-NEXT: sw $4, %lo(d)($1) # <MCInst #[[#MCINST17]] SW
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32-NEXT: # <MCOperand Expr:specifier(4031,d)>>
+; MIPS32-NEXT: addiu $1, $1, %lo(d) # <MCInst #[[#MCINST20:]] ADDiu
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32-NEXT: # <MCOperand Expr:specifier(4031,d)>>
+; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32-NEXT: sw $5, 4($1) # <MCInst #[[#MCINST17]] SW
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG9:]]>
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
; MIPS32-NEXT: # <MCOperand Imm:4>>
;
; MMR3-LABEL: f4:
; MMR3: # %bb.0:
-; MMR3-NEXT: lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Expr:(%hi(d))>>
-; MMR3-NEXT: sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Expr:(%lo(d))>>
-; MMR3-NEXT: addiu $2, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Expr:(%lo(d))>>
-; MMR3-NEXT: sw16 $5, 4($2) # <MCInst #{{[0-9]+}} SW16_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MMR3-NEXT: lui $1, %hi(d) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR3-NEXT: # <MCOperand Expr:specifier(4028,d)>>
+; MMR3-NEXT: sw $4, %lo(d)($1) # <MCInst #[[#MCINST18]] SW_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR3-NEXT: # <MCOperand Expr:specifier(4031,d)>>
+; MMR3-NEXT: addiu $2, $1, %lo(d) # <MCInst #[[#MCINST21:]] ADDiu_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG10:]]>
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR3-NEXT: # <MCOperand Expr:specifier(4031,d)>>
+; MMR3-NEXT: sw16 $5, 4($2) # <MCInst #[[#MCINST22:]] SW16_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG9:]]>
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG10]]>
; MMR3-NEXT: # <MCOperand Imm:4>>
-; MMR3-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; MMR3-NEXT: jrc $ra # <MCInst #[[#MCINST8:]] JRC16_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
;
; MIPS32R6-LABEL: f4:
; MIPS32R6: # %bb.0:
-; MIPS32R6-NEXT: lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(d))>>
-; MIPS32R6-NEXT: sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(d))>>
-; MIPS32R6-NEXT: addiu $1, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(d))>>
-; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32R6-NEXT: sw $5, 4($1) # <MCInst #{{[0-9]+}} SW
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R6-NEXT: lui $1, %hi(d) # <MCInst #[[#MCINST1]] LUi
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4028,d)>>
+; MIPS32R6-NEXT: sw $4, %lo(d)($1) # <MCInst #[[#MCINST17]] SW
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4031,d)>>
+; MIPS32R6-NEXT: addiu $1, $1, %lo(d) # <MCInst #[[#MCINST20:]] ADDiu
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4031,d)>>
+; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32R6-NEXT: sw $5, 4($1) # <MCInst #[[#MCINST17]] SW
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG9:]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
; MIPS32R6-NEXT: # <MCOperand Imm:4>>
;
; MMR6-LABEL: f4:
; MMR6: # %bb.0:
-; MMR6-NEXT: lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Expr:(%hi(d))>>
-; MMR6-NEXT: sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Expr:(%lo(d))>>
-; MMR6-NEXT: addiu $2, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Expr:(%lo(d))>>
-; MMR6-NEXT: sw16 $5, 4($2) # <MCInst #{{[0-9]+}} SW16_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MMR6-NEXT: lui $1, %hi(d) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR6-NEXT: # <MCOperand Expr:specifier(4028,d)>>
+; MMR6-NEXT: sw $4, %lo(d)($1) # <MCInst #[[#MCINST18]] SW_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR6-NEXT: # <MCOperand Expr:specifier(4031,d)>>
+; MMR6-NEXT: addiu $2, $1, %lo(d) # <MCInst #[[#MCINST21:]] ADDiu_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG10:]]>
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR6-NEXT: # <MCOperand Expr:specifier(4031,d)>>
+; MMR6-NEXT: sw16 $5, 4($2) # <MCInst #[[#MCINST22:]] SW16_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG9:]]>
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG10]]>
; MMR6-NEXT: # <MCOperand Imm:4>>
-; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
;
; MIPS4-LABEL: f4:
; MIPS4: # %bb.0:
-; MIPS4-NEXT: lui $1, %highest(d) # <MCInst #{{[0-9]+}} LUi64
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Expr:(%highest(d))>>
-; MIPS4-NEXT: daddiu $1, $1, %higher(d) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Expr:(%higher(d))>>
-; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT: lui $1, %highest(d) # <MCInst #[[#MCINST9]] LUi64
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Expr:specifier(4030,d)>>
+; MIPS4-NEXT: daddiu $1, $1, %higher(d) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Expr:specifier(4029,d)>>
+; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS4-NEXT: # <MCOperand Imm:16>>
-; MIPS4-NEXT: daddiu $1, $1, %hi(d) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Expr:(%hi(d))>>
-; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT: daddiu $1, $1, %hi(d) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Expr:specifier(4028,d)>>
+; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS4-NEXT: # <MCOperand Imm:16>>
-; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS4-NEXT: sd $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SD
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Expr:(%lo(d))>>
+; MIPS4-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS4-NEXT: sd $4, %lo(d)($1) # <MCInst #[[#MCINST23:]] SD
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG7]]>
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Expr:specifier(4031,d)>>
;
; MIPS64R6-LABEL: f4:
; MIPS64R6: # %bb.0:
-; MIPS64R6-NEXT: lui $1, %highest(d) # <MCInst #{{[0-9]+}} LUi64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(d))>>
-; MIPS64R6-NEXT: daddiu $1, $1, %higher(d) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(d))>>
-; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT: lui $1, %highest(d) # <MCInst #[[#MCINST9]] LUi64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4030,d)>>
+; MIPS64R6-NEXT: daddiu $1, $1, %higher(d) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4029,d)>>
+; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
-; MIPS64R6-NEXT: daddiu $1, $1, %hi(d) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(d))>>
-; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT: daddiu $1, $1, %hi(d) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4028,d)>>
+; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
-; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS64R6-NEXT: sd $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SD
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(d))>>
+; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST13]] JALR64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG8]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS64R6-NEXT: sd $4, %lo(d)($1) # <MCInst #[[#MCINST23:]] SD
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG7]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4031,d)>>
;
; MMR5FP64-LABEL: f4:
; MMR5FP64: # %bb.0:
-; MMR5FP64-NEXT: lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Expr:(%hi(d))>>
-; MMR5FP64-NEXT: sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Expr:(%lo(d))>>
-; MMR5FP64-NEXT: addiu $2, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Expr:(%lo(d))>>
-; MMR5FP64-NEXT: sw16 $5, 4($2) # <MCInst #{{[0-9]+}} SW16_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MMR5FP64-NEXT: lui $1, %hi(d) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4028,d)>>
+; MMR5FP64-NEXT: sw $4, %lo(d)($1) # <MCInst #[[#MCINST18]] SW_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4031,d)>>
+; MMR5FP64-NEXT: addiu $2, $1, %lo(d) # <MCInst #[[#MCINST21:]] ADDiu_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG10:]]>
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4031,d)>>
+; MMR5FP64-NEXT: sw16 $5, 4($2) # <MCInst #[[#MCINST22:]] SW16_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG9:]]>
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG10]]>
; MMR5FP64-NEXT: # <MCOperand Imm:4>>
-; MMR5FP64-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; MMR5FP64-NEXT: jrc $ra # <MCInst #[[#MCINST8:]] JRC16_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
;
; MIPS32R5FP643-LABEL: f4:
; MIPS32R5FP643: # %bb.0:
-; MIPS32R5FP643-NEXT: lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Expr:(%hi(d))>>
-; MIPS32R5FP643-NEXT: sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Expr:(%lo(d))>>
-; MIPS32R5FP643-NEXT: addiu $1, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Expr:(%lo(d))>>
-; MIPS32R5FP643-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32R5FP643-NEXT: sw $5, 4($1) # <MCInst #{{[0-9]+}} SW
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS32R5FP643-NEXT: lui $1, %hi(d) # <MCInst #[[#MCINST1]] LUi
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4028,d)>>
+; MIPS32R5FP643-NEXT: sw $4, %lo(d)($1) # <MCInst #[[#MCINST17]] SW
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG3]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4031,d)>>
+; MIPS32R5FP643-NEXT: addiu $1, $1, %lo(d) # <MCInst #[[#MCINST20:]] ADDiu
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4031,d)>>
+; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32R5FP643-NEXT: sw $5, 4($1) # <MCInst #[[#MCINST17]] SW
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG9:]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>
; MIPS32R5FP643-NEXT: # <MCOperand Imm:4>>
store i64 %a, ptr @d
ret void
@@ -608,133 +608,133 @@ define void @f4(i64 %a) {
define void @f5(float %e) {
; MIPS32-LABEL: f5:
; MIPS32: # %bb.0:
-; MIPS32-NEXT: lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Expr:(%hi(e))>>
-; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #{{[0-9]+}} SWC1
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Expr:(%lo(e))>>
+; MIPS32-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST1]] LUi
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32-NEXT: # <MCOperand Expr:specifier(4028,e)>>
+; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #[[#MCINST24:]] SWC1
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG11:]]>
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32-NEXT: # <MCOperand Expr:specifier(4031,e)>>
;
; MMR3-LABEL: f5:
; MMR3: # %bb.0:
-; MMR3-NEXT: lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Expr:(%hi(e))>>
-; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR3-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #{{[0-9]+}} SWC1_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Expr:(%lo(e))>>
+; MMR3-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR3-NEXT: # <MCOperand Expr:specifier(4028,e)>>
+; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MMR3-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #[[#MCINST25:]] SWC1_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG11:]]>
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR3-NEXT: # <MCOperand Expr:specifier(4031,e)>>
;
; MIPS32R6-LABEL: f5:
; MIPS32R6: # %bb.0:
-; MIPS32R6-NEXT: lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(e))>>
-; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32R6-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #{{[0-9]+}} SWC1
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(e))>>
+; MIPS32R6-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST1]] LUi
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4028,e)>>
+; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32R6-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #[[#MCINST24:]] SWC1
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG11:]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4031,e)>>
;
; MMR6-LABEL: f5:
; MMR6: # %bb.0:
-; MMR6-NEXT: lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Expr:(%hi(e))>>
-; MMR6-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #{{[0-9]+}} SWC1_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Expr:(%lo(e))>>
-; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; MMR6-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR6-NEXT: # <MCOperand Expr:specifier(4028,e)>>
+; MMR6-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #[[#MCINST25:]] SWC1_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG11:]]>
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR6-NEXT: # <MCOperand Expr:specifier(4031,e)>>
+; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
;
; MIPS4-LABEL: f5:
; MIPS4: # %bb.0:
-; MIPS4-NEXT: lui $1, %highest(e) # <MCInst #{{[0-9]+}} LUi64
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Expr:(%highest(e))>>
-; MIPS4-NEXT: daddiu $1, $1, %higher(e) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Expr:(%higher(e))>>
-; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT: lui $1, %highest(e) # <MCInst #[[#MCINST9]] LUi64
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Expr:specifier(4030,e)>>
+; MIPS4-NEXT: daddiu $1, $1, %higher(e) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Expr:specifier(4029,e)>>
+; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS4-NEXT: # <MCOperand Imm:16>>
-; MIPS4-NEXT: daddiu $1, $1, %hi(e) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Expr:(%hi(e))>>
-; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT: daddiu $1, $1, %hi(e) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Expr:specifier(4028,e)>>
+; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS4-NEXT: # <MCOperand Imm:16>>
-; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS4-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #{{[0-9]+}} SWC1
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Expr:(%lo(e))>>
+; MIPS4-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS4-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #[[#MCINST24:]] SWC1
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG11:]]>
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Expr:specifier(4031,e)>>
;
; MIPS64R6-LABEL: f5:
; MIPS64R6: # %bb.0:
-; MIPS64R6-NEXT: lui $1, %highest(e) # <MCInst #{{[0-9]+}} LUi64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(e))>>
-; MIPS64R6-NEXT: daddiu $1, $1, %higher(e) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(e))>>
-; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT: lui $1, %highest(e) # <MCInst #[[#MCINST9]] LUi64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4030,e)>>
+; MIPS64R6-NEXT: daddiu $1, $1, %higher(e) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4029,e)>>
+; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
-; MIPS64R6-NEXT: daddiu $1, $1, %hi(e) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(e))>>
-; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT: daddiu $1, $1, %hi(e) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4028,e)>>
+; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
-; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS64R6-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #{{[0-9]+}} SWC1
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(e))>>
+; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST13]] JALR64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG8]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS64R6-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #[[#MCINST24:]] SWC1
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG11:]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4031,e)>>
;
; MMR5FP64-LABEL: f5:
; MMR5FP64: # %bb.0:
-; MMR5FP64-NEXT: lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Expr:(%hi(e))>>
-; MMR5FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR5FP64-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #{{[0-9]+}} SWC1_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Expr:(%lo(e))>>
+; MMR5FP64-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4028,e)>>
+; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MMR5FP64-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #[[#MCINST25:]] SWC1_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG11:]]>
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4031,e)>>
;
; MIPS32R5FP643-LABEL: f5:
; MIPS32R5FP643: # %bb.0:
-; MIPS32R5FP643-NEXT: lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Expr:(%hi(e))>>
-; MIPS32R5FP643-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32R5FP643-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #{{[0-9]+}} SWC1
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Expr:(%lo(e))>>
+; MIPS32R5FP643-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST1]] LUi
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4028,e)>>
+; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32R5FP643-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #[[#MCINST24:]] SWC1
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG11:]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4031,e)>>
store float %e, ptr @e
ret void
}
@@ -742,133 +742,133 @@ define void @f5(float %e) {
define void @f6(double %f) {
; MIPS32-LABEL: f6:
; MIPS32: # %bb.0:
-; MIPS32-NEXT: lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Expr:(%hi(f))>>
-; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #{{[0-9]+}} SDC1
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32-NEXT: # <MCOperand Expr:(%lo(f))>>
+; MIPS32-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST1]] LUi
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32-NEXT: # <MCOperand Expr:specifier(4028,f)>>
+; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #[[#MCINST26:]] SDC1
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG12:]]>
+; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32-NEXT: # <MCOperand Expr:specifier(4031,f)>>
;
; MMR3-LABEL: f6:
; MMR3: # %bb.0:
-; MMR3-NEXT: lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Expr:(%hi(f))>>
-; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR3-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #{{[0-9]+}} SDC1_MM_D32
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR3-NEXT: # <MCOperand Expr:(%lo(f))>>
+; MMR3-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR3-NEXT: # <MCOperand Expr:specifier(4028,f)>>
+; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MMR3-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #[[#MCINST27:]] SDC1_MM_D32
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG12:]]>
+; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR3-NEXT: # <MCOperand Expr:specifier(4031,f)>>
;
; MIPS32R6-LABEL: f6:
; MIPS32R6: # %bb.0:
-; MIPS32R6-NEXT: lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(f))>>
-; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32R6-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #{{[0-9]+}} SDC164
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(f))>>
+; MIPS32R6-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST1]] LUi
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4028,f)>>
+; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32R6-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #[[#MCINST28:]] SDC164
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG13:]]>
+; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4031,f)>>
;
; MMR6-LABEL: f6:
; MMR6: # %bb.0:
-; MMR6-NEXT: lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Expr:(%hi(f))>>
-; MMR6-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #{{[0-9]+}} SDC1_D64_MMR6
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR6-NEXT: # <MCOperand Expr:(%lo(f))>>
-; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
-; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
+; MMR6-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR6-NEXT: # <MCOperand Expr:specifier(4028,f)>>
+; MMR6-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #[[#MCINST29:]] SDC1_D64_MMR6
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG13:]]>
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR6-NEXT: # <MCOperand Expr:specifier(4031,f)>>
+; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM
+; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
;
; MIPS4-LABEL: f6:
; MIPS4: # %bb.0:
-; MIPS4-NEXT: lui $1, %highest(f) # <MCInst #{{[0-9]+}} LUi64
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Expr:(%highest(f))>>
-; MIPS4-NEXT: daddiu $1, $1, %higher(f) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Expr:(%higher(f))>>
-; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT: lui $1, %highest(f) # <MCInst #[[#MCINST9]] LUi64
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Expr:specifier(4030,f)>>
+; MIPS4-NEXT: daddiu $1, $1, %higher(f) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Expr:specifier(4029,f)>>
+; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS4-NEXT: # <MCOperand Imm:16>>
-; MIPS4-NEXT: daddiu $1, $1, %hi(f) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Expr:(%hi(f))>>
-; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS4-NEXT: daddiu $1, $1, %hi(f) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Expr:specifier(4028,f)>>
+; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS4-NEXT: # <MCOperand Imm:16>>
-; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS4-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #{{[0-9]+}} SDC164
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS4-NEXT: # <MCOperand Expr:(%lo(f))>>
+; MIPS4-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS4-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #[[#MCINST28:]] SDC164
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG13:]]>
+; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS4-NEXT: # <MCOperand Expr:specifier(4031,f)>>
;
; MIPS64R6-LABEL: f6:
; MIPS64R6: # %bb.0:
-; MIPS64R6-NEXT: lui $1, %highest(f) # <MCInst #{{[0-9]+}} LUi64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(f))>>
-; MIPS64R6-NEXT: daddiu $1, $1, %higher(f) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(f))>>
-; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT: lui $1, %highest(f) # <MCInst #[[#MCINST9]] LUi64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4030,f)>>
+; MIPS64R6-NEXT: daddiu $1, $1, %higher(f) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4029,f)>>
+; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
-; MIPS64R6-NEXT: daddiu $1, $1, %hi(f) # <MCInst #{{[0-9]+}} DADDiu
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(f))>>
-; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
+; MIPS64R6-NEXT: daddiu $1, $1, %hi(f) # <MCInst #[[#MCINST10]] DADDiu
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4028,f)>>
+; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
-; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS64R6-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #{{[0-9]+}} SDC164
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(f))>>
+; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST13]] JALR64
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG8]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG6]]>>
+; MIPS64R6-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #[[#MCINST28:]] SDC164
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG13:]]>
+; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>
+; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4031,f)>>
;
; MMR5FP64-LABEL: f6:
; MMR5FP64: # %bb.0:
-; MMR5FP64-NEXT: lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Expr:(%hi(f))>>
-; MMR5FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MMR5FP64-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #{{[0-9]+}} SDC1_MM_D64
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MMR5FP64-NEXT: # <MCOperand Expr:(%lo(f))>>
+; MMR5FP64-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST4]] LUi_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4028,f)>>
+; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MMR5FP64-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #[[#MCINST30:]] SDC1_MM_D64
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG13:]]>
+; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4031,f)>>
;
; MIPS32R5FP643-LABEL: f6:
; MIPS32R5FP643: # %bb.0:
-; MIPS32R5FP643-NEXT: lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Expr:(%hi(f))>>
-; MIPS32R5FP643-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
-; MIPS32R5FP643-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #{{[0-9]+}} SDC164
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Reg:{{[0-9]+}}>
-; MIPS32R5FP643-NEXT: # <MCOperand Expr:(%lo(f))>>
+; MIPS32R5FP643-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST1]] LUi
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4028,f)>>
+; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG2]]>>
+; MIPS32R5FP643-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #[[#MCINST28:]] SDC164
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG13:]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>
+; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4031,f)>>
store double %f, ptr @f
ret void
}
diff --git a/llvm/test/MC/Lanai/conditional_inst.s b/llvm/test/MC/Lanai/conditional_inst.s
index d167d1af00eb3..a0a8caf269fe8 100644
--- a/llvm/test/MC/Lanai/conditional_inst.s
+++ b/llvm/test/MC/Lanai/conditional_inst.s
@@ -27,14 +27,14 @@ jump2:
! CHECK: encoding: [0b1110110A,A,A,0x01'A']
! CHECK-NEXT: fixup A - offset: 0, value: jump1, kind: FIXUP_LANAI_25
! CHECK-NEXT: <MCInst #{{[0-9]+}} BRCC{{$}}
-! CHECK-NEXT: <MCOperand Expr:(jump1)>
+! CHECK-NEXT: <MCOperand Expr:specifier(0,jump1)>
! CHECK-NEXT: <MCOperand Imm:13>
bpl jump2
! CHECK: encoding: [0b1110101A,A,A,A]
! CHECK-NEXT: fixup A - offset: 0, value: jump2, kind: FIXUP_LANAI_25
! CHECK-NEXT: <MCInst #{{[0-9]+}} BRCC{{$}}
-! CHECK-NEXT: <MCOperand Expr:(jump2)>
+! CHECK-NEXT: <MCOperand Expr:specifier(0,jump2)>
! CHECK-NEXT: <MCOperand Imm:10>
bt .
@@ -43,7 +43,7 @@ jump2:
! CHECK: encoding: [0b1110000A,A,A,A]
! CHECK-NEXT: fixup A - offset: 0, value: .Ltmp0, kind: FIXUP_LANAI_25
! CHECK-NEXT: <MCInst #{{[0-9]+}} BT{{$}}
-! CHECK-NEXT: <MCOperand Expr:(.Ltmp0)>
+! CHECK-NEXT: <MCOperand Expr:.Ltmp0>
! SCC
spl %r19
diff --git a/llvm/test/MC/Lanai/memory.s b/llvm/test/MC/Lanai/memory.s
index 41dc8fba7bf29..0e6234645a80d 100644
--- a/llvm/test/MC/Lanai/memory.s
+++ b/llvm/test/MC/Lanai/memory.s
@@ -235,7 +235,7 @@
! CHECK-NEXT: <MCInst #{{[0-9]+}} ADD_I_HI
! CHECK-NEXT: <MCOperand Reg:11>
! CHECK-NEXT: <MCOperand Reg:7>
-! CHECK-NEXT: <MCOperand Expr:(hi(x))>
+! CHECK-NEXT: <MCOperand Expr:specifier(1,x)>
mov hi(l+4), %r7
! CHECK: encoding: [0x03,0x81,A,A]
@@ -243,5 +243,5 @@
! CHECK-NEXT: <MCInst #{{[0-9]+}} ADD_I_HI
! CHECK-NEXT: <MCOperand Reg:14>
! CHECK-NEXT: <MCOperand Reg:7>
-! CHECK-NEXT: <MCOperand Expr:(hi(l)+4)>
+! CHECK-NEXT: <MCOperand Expr:specifier(1,l)+4>
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