[llvm] 993c158 - MIPS: Reduce MipsMCExpr uses
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Sun Jun 15 18:46:55 PDT 2025
Author: Fangrui Song
Date: 2025-06-15T18:46:51-07:00
New Revision: 993c158a30b9ddc881e55efcd33e33abc10f3a5c
URL: https://github.com/llvm/llvm-project/commit/993c158a30b9ddc881e55efcd33e33abc10f3a5c
DIFF: https://github.com/llvm/llvm-project/commit/993c158a30b9ddc881e55efcd33e33abc10f3a5c.diff
LOG: MIPS: Reduce MipsMCExpr uses
Added:
Modified:
llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h
llvm/lib/Target/Mips/MipsMCInstLower.cpp
llvm/lib/Target/Mips/MipsMCInstLower.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 8d9c3a96b32a1..7ea7c58f1a512 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -3032,7 +3032,7 @@ bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr,
return false;
}
- const MipsMCExpr *GotExpr = nullptr;
+ const MCSpecifierExpr *GotExpr = nullptr;
const MCExpr *LoExpr = nullptr;
if (ABI.IsN32() || ABI.IsN64()) {
// The remaining cases are:
@@ -3097,10 +3097,8 @@ bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr,
return false;
}
- const MipsMCExpr *HiExpr =
- MipsMCExpr::create(Mips::S_HI, SymExpr, getContext());
- const MipsMCExpr *LoExpr =
- MipsMCExpr::create(Mips::S_LO, SymExpr, getContext());
+ const auto *HiExpr = MipsMCExpr::create(Mips::S_HI, SymExpr, getContext());
+ const auto *LoExpr = MipsMCExpr::create(Mips::S_LO, SymExpr, getContext());
// This is the 64-bit symbol address expansion.
if (ABI.ArePtrs64bit() && isGP64bit()) {
@@ -3111,9 +3109,9 @@ bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr,
// If it is not available we exit if the destination is the same as the
// source register.
- const MipsMCExpr *HighestExpr =
+ const auto *HighestExpr =
MipsMCExpr::create(Mips::S_HIGHEST, SymExpr, getContext());
- const MipsMCExpr *HigherExpr =
+ const auto *HigherExpr =
MipsMCExpr::create(Mips::S_HIGHER, SymExpr, getContext());
bool RdRegIsRsReg =
@@ -3312,8 +3310,7 @@ bool MipsAsmParser::emitPartialAddress(MipsTargetStreamer &TOut, SMLoc IDLoc,
if(IsPicEnabled) {
const MCExpr *GotSym = MCSymbolRefExpr::create(Sym, getContext());
- const MipsMCExpr *GotExpr =
- MipsMCExpr::create(Mips::S_GOT, GotSym, getContext());
+ const auto *GotExpr = MipsMCExpr::create(Mips::S_GOT, GotSym, getContext());
if(isABI_O32() || isABI_N32()) {
TOut.emitRRX(Mips::LW, ATReg, GPReg, MCOperand::createExpr(GotExpr),
@@ -3324,8 +3321,7 @@ bool MipsAsmParser::emitPartialAddress(MipsTargetStreamer &TOut, SMLoc IDLoc,
}
} else { //!IsPicEnabled
const MCExpr *HiSym = MCSymbolRefExpr::create(Sym, getContext());
- const MipsMCExpr *HiExpr =
- MipsMCExpr::create(Mips::S_HI, HiSym, getContext());
+ const auto *HiExpr = MipsMCExpr::create(Mips::S_HI, HiSym, getContext());
// FIXME: This is technically correct but gives a
diff erent result to gas,
// but gas is incomplete there (it has a fixme noting it doesn't work with
@@ -3337,10 +3333,10 @@ bool MipsAsmParser::emitPartialAddress(MipsTargetStreamer &TOut, SMLoc IDLoc,
TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HiExpr), IDLoc, STI);
} else { //isABI_N64()
const MCExpr *HighestSym = MCSymbolRefExpr::create(Sym, getContext());
- const MipsMCExpr *HighestExpr =
+ const auto *HighestExpr =
MipsMCExpr::create(Mips::S_HIGHEST, HighestSym, getContext());
const MCExpr *HigherSym = MCSymbolRefExpr::create(Sym, getContext());
- const MipsMCExpr *HigherExpr =
+ const auto *HigherExpr =
MipsMCExpr::create(Mips::S_HIGHER, HigherSym, getContext());
TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HighestExpr), IDLoc,
@@ -3428,8 +3424,7 @@ bool MipsAsmParser::expandLoadSingleImmToFPR(MCInst &Inst, SMLoc IDLoc,
MCSymbol *Sym = getContext().createTempSymbol();
const MCExpr *LoSym = MCSymbolRefExpr::create(Sym, getContext());
- const MipsMCExpr *LoExpr =
- MipsMCExpr::create(Mips::S_LO, LoSym, getContext());
+ const auto *LoExpr = MipsMCExpr::create(Mips::S_LO, LoSym, getContext());
getStreamer().switchSection(ReadOnlySection);
getStreamer().emitLabel(Sym, IDLoc);
@@ -3479,8 +3474,7 @@ bool MipsAsmParser::expandLoadDoubleImmToGPR(MCInst &Inst, SMLoc IDLoc,
MCSymbol *Sym = getContext().createTempSymbol();
const MCExpr *LoSym = MCSymbolRefExpr::create(Sym, getContext());
- const MipsMCExpr *LoExpr =
- MipsMCExpr::create(Mips::S_LO, LoSym, getContext());
+ const auto *LoExpr = MipsMCExpr::create(Mips::S_LO, LoSym, getContext());
getStreamer().switchSection(ReadOnlySection);
getStreamer().emitLabel(Sym, IDLoc);
@@ -3560,8 +3554,7 @@ bool MipsAsmParser::expandLoadDoubleImmToFPR(MCInst &Inst, bool Is64FPU,
MCSymbol *Sym = getContext().createTempSymbol();
const MCExpr *LoSym = MCSymbolRefExpr::create(Sym, getContext());
- const MipsMCExpr *LoExpr =
- MipsMCExpr::create(Mips::S_LO, LoSym, getContext());
+ const auto *LoExpr = MipsMCExpr::create(Mips::S_LO, LoSym, getContext());
getStreamer().switchSection(ReadOnlySection);
getStreamer().emitLabel(Sym, IDLoc);
@@ -6353,7 +6346,7 @@ MCRegister MipsAsmParser::getReg(int RC, int RegNo) {
// e.g. "%lo foo", "(%lo(foo))", "%lo(foo)+1".
const MCExpr *MipsAsmParser::parseRelocExpr() {
auto getOp = [](StringRef Op) {
- return StringSwitch<MipsMCExpr::Specifier>(Op)
+ return StringSwitch<Mips::Specifier>(Op)
.Case("call16", Mips::S_GOT_CALL)
.Case("call_hi", Mips::S_CALL_HI16)
.Case("call_lo", Mips::S_CALL_LO16)
@@ -6384,7 +6377,7 @@ const MCExpr *MipsAsmParser::parseRelocExpr() {
MCAsmParser &Parser = getParser();
StringRef Name;
const MCExpr *Res = nullptr;
- SmallVector<MipsMCExpr::Specifier, 0> Ops;
+ SmallVector<Mips::Specifier, 0> Ops;
while (parseOptionalToken(AsmToken::Percent)) {
if (Parser.parseIdentifier(Name) ||
Parser.parseToken(AsmToken::LParen, "expected '('"))
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
index 9b2b25c60c946..b64f86f382974 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
@@ -157,8 +157,8 @@ static void printImpl(const MCAsmInfo &MAI, raw_ostream &OS,
bool Mips::isGpOff(const MCSpecifierExpr &E) {
if (E.getSpecifier() == Mips::S_HI || E.getSpecifier() == Mips::S_LO) {
- if (const MipsMCExpr *S1 = dyn_cast<const MipsMCExpr>(E.getSubExpr())) {
- if (const MipsMCExpr *S2 = dyn_cast<const MipsMCExpr>(S1->getSubExpr())) {
+ if (const auto *S1 = dyn_cast<const MCSpecifierExpr>(E.getSubExpr())) {
+ if (const auto *S2 = dyn_cast<const MCSpecifierExpr>(S1->getSubExpr())) {
if (S1->getSpecifier() == Mips::S_NEG &&
S2->getSpecifier() == Mips::S_GPREL) {
// S = E.getSpecifier();
@@ -176,7 +176,8 @@ static bool evaluate(const MCSpecifierExpr &Expr, MCValue &Res,
// special cases.
if (Mips::isGpOff(Expr)) {
const MCExpr *SubExpr =
- cast<MipsMCExpr>(cast<MipsMCExpr>(Expr.getSubExpr())->getSubExpr())
+ cast<MCSpecifierExpr>(
+ cast<MCSpecifierExpr>(Expr.getSubExpr())->getSubExpr())
->getSubExpr();
if (!SubExpr->evaluateAsRelocatable(Res, Asm))
return false;
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h
index 39699fdb98272..0975116328fc1 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h
@@ -45,6 +45,7 @@ class MipsCOFFMCAsmInfo : public MCAsmInfoGNUCOFF {
};
namespace Mips {
+using Specifier = uint16_t;
enum {
S_None,
S_CALL_HI16 = FirstTargetFixupKind,
diff --git a/llvm/lib/Target/Mips/MipsMCInstLower.cpp b/llvm/lib/Target/Mips/MipsMCInstLower.cpp
index 3c3690a7f983d..935fcd8fa7154 100644
--- a/llvm/lib/Target/Mips/MipsMCInstLower.cpp
+++ b/llvm/lib/Target/Mips/MipsMCInstLower.cpp
@@ -35,7 +35,7 @@ void MipsMCInstLower::Initialize(MCContext *C) {
MCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
MachineOperandType MOTy,
int64_t Offset) const {
- MipsMCExpr::Specifier TargetKind = Mips::S_None;
+ Mips::Specifier TargetKind = Mips::S_None;
bool IsGpOff = false;
const MCSymbol *Symbol;
SmallString<128> Name;
@@ -211,7 +211,7 @@ MCOperand MipsMCInstLower::LowerOperand(const MachineOperand &MO,
MCOperand MipsMCInstLower::createSub(MachineBasicBlock *BB1,
MachineBasicBlock *BB2,
- MipsMCExpr::Specifier Kind) const {
+ Mips::Specifier Kind) const {
const MCSymbolRefExpr *Sym1 = MCSymbolRefExpr::create(BB1->getSymbol(), *Ctx);
const MCSymbolRefExpr *Sym2 = MCSymbolRefExpr::create(BB2->getSymbol(), *Ctx);
const MCBinaryExpr *Sub = MCBinaryExpr::createSub(Sym1, Sym2, *Ctx);
@@ -226,7 +226,7 @@ lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const {
// Lower register operand.
OutMI.addOperand(LowerOperand(MI->getOperand(0)));
- MipsMCExpr::Specifier Spec;
+ Mips::Specifier Spec;
unsigned TargetFlags = MI->getOperand(1).getTargetFlags();
switch (TargetFlags) {
case MipsII::MO_HIGHEST:
@@ -248,7 +248,7 @@ lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const {
if (MI->getNumOperands() == 2) {
const MCExpr *Expr =
MCSymbolRefExpr::create(MI->getOperand(1).getMBB()->getSymbol(), *Ctx);
- const MipsMCExpr *MipsExpr = MipsMCExpr::create(Spec, Expr, *Ctx);
+ const auto *MipsExpr = MipsMCExpr::create(Spec, Expr, *Ctx);
OutMI.addOperand(MCOperand::createExpr(MipsExpr));
} else if (MI->getNumOperands() == 3) {
// Create %hi($tgt-$baltgt).
@@ -261,7 +261,7 @@ void MipsMCInstLower::lowerLongBranchADDiu(const MachineInstr *MI,
MCInst &OutMI, int Opcode) const {
OutMI.setOpcode(Opcode);
- MipsMCExpr::Specifier Spec;
+ Mips::Specifier Spec;
unsigned TargetFlags = MI->getOperand(2).getTargetFlags();
switch (TargetFlags) {
case MipsII::MO_HIGHEST:
@@ -290,7 +290,7 @@ void MipsMCInstLower::lowerLongBranchADDiu(const MachineInstr *MI,
// Lower register operand.
const MCExpr *Expr =
MCSymbolRefExpr::create(MI->getOperand(2).getMBB()->getSymbol(), *Ctx);
- const MipsMCExpr *MipsExpr = MipsMCExpr::create(Spec, Expr, *Ctx);
+ const auto *MipsExpr = MipsMCExpr::create(Spec, Expr, *Ctx);
OutMI.addOperand(MCOperand::createExpr(MipsExpr));
} else if (MI->getNumOperands() == 4) {
// Create %lo($tgt-$baltgt) or %hi($tgt-$baltgt).
diff --git a/llvm/lib/Target/Mips/MipsMCInstLower.h b/llvm/lib/Target/Mips/MipsMCInstLower.h
index b6ddbe98955d1..a618c6fb7bfab 100644
--- a/llvm/lib/Target/Mips/MipsMCInstLower.h
+++ b/llvm/lib/Target/Mips/MipsMCInstLower.h
@@ -9,7 +9,7 @@
#ifndef LLVM_LIB_TARGET_MIPS_MIPSMCINSTLOWER_H
#define LLVM_LIB_TARGET_MIPS_MIPSMCINSTLOWER_H
-#include "MCTargetDesc/MipsMCExpr.h"
+#include "MCTargetDesc/MipsMCAsmInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/Support/Compiler.h"
@@ -41,7 +41,7 @@ class LLVM_LIBRARY_VISIBILITY MipsMCInstLower {
MCOperand LowerSymbolOperand(const MachineOperand &MO,
MachineOperandType MOTy, int64_t Offset) const;
MCOperand createSub(MachineBasicBlock *BB1, MachineBasicBlock *BB2,
- MipsMCExpr::Specifier Kind) const;
+ Mips::Specifier Kind) const;
void lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const;
void lowerLongBranchADDiu(const MachineInstr *MI, MCInst &OutMI,
int Opcode) const;
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