[llvm] [SelectionDAG][x86] Ensure vector reduction optimization (PR #144231)

[Simon Pilgrim via llvm-commits]

Suhajda =?utf-8?q?Tamás?= <sutajo at gmail.com>,
Suhajda =?utf-8?q?Tamás?= <sutajo at gmail.com>
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In-Reply-To: <llvm.org/llvm/llvm-project/pull/144231 at github.com>


RKSimon wrote:

@sutajo - thanks for the patch, but it'd be a lot more useful if you could investigate adding Custom lowering of ISD::VECREDUCE MIN/MAX opcodes for vXi8/vXi16 types to SSE41 PHMINPOS instructions - refactoring `combineMinMaxReduction` into a `lowerMinMaxReduction` method. 

https://github.com/llvm/llvm-project/pull/144231