[clang] [llvm] [RISCV] Fix incorrect predicates for fp16 permutation intrinsics (PR #144063)

[Jim Lin via llvm-commits]

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@@ -7405,8 +7405,12 @@ defm : VPatTernaryV_VX_VI<"int_riscv_vslidedown", "PseudoVSLIDEDOWN", AllInteger
 defm : VPatBinaryV_VX<"int_riscv_vslide1up", "PseudoVSLIDE1UP", AllIntegerVectors>;
 defm : VPatBinaryV_VX<"int_riscv_vslide1down", "PseudoVSLIDE1DOWN", AllIntegerVectors>;
 
-defm : VPatTernaryV_VX_VI<"int_riscv_vslideup", "PseudoVSLIDEUP", AllFloatVectors, uimm5>;
-defm : VPatTernaryV_VX_VI<"int_riscv_vslidedown", "PseudoVSLIDEDOWN", AllFloatVectors, uimm5>;
+defm : VPatTernaryV_VX_VI<"int_riscv_vslideup", "PseudoVSLIDEUP", AllFloatVectorsExceptFP16, uimm5>;
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tclin914 wrote:

> I think we need a backend test for this change

I changed `+zvfh` specified in -mattr= to `+zvfhmin` in `vrgatherei16.ll/vslidedown.ll/vslideup.ll` to make sure that vrgatherei16/vslidedown/vslideup can work for zvfhmin with fp16 vector type

https://github.com/llvm/llvm-project/pull/144063