[llvm] [NVPTX] add combiner rule for final packed op in reduction (PR #143943)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

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``````````bash
git-clang-format --diff HEAD~1 HEAD --extensions cpp -- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 075bfcc81..edbee99ab 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1357,8 +1357,8 @@ SDValue DAGCombiner::foldReductionWithUndefLane(SDNode *N) {
   const EVT VectorVT = N->getValueType(0);
 
   // Only support 2-packed vectors for now.
-  if (!VectorVT.isVector() || VectorVT.isScalableVector()
-        || VectorVT.getVectorNumElements() != 2)
+  if (!VectorVT.isVector() || VectorVT.isScalableVector() ||
+      VectorVT.getVectorNumElements() != 2)
     return SDValue();
 
   // If the operation is already unsupported, we don't need to do this
@@ -1369,7 +1369,7 @@ SDValue DAGCombiner::foldReductionWithUndefLane(SDNode *N) {
   // If vector shuffle is supported on the target, this optimization may
   // increase register pressure.
   if (TLI.isOperationLegalOrCustomOrPromote(ISD::VECTOR_SHUFFLE, VectorVT))
-      return SDValue();
+    return SDValue();
 
   SDLoc DL(N);
 

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https://github.com/llvm/llvm-project/pull/143943