[llvm] [RISCV] Use RISCVII::getVecPolicyOpNum instead of making assumptions. NFC (PR #144175)
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Fri Jun 13 18:06:14 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Craig Topper (topperc)
<details>
<summary>Changes</summary>
---
Full diff: https://github.com/llvm/llvm-project/pull/144175.diff
1 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+6-3)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index e5d29e1a8b476..0c4069c062ca8 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -3696,7 +3696,8 @@ bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
case CASE_VMA_OPCODE_LMULS(NMSAC, VV): {
// If the tail policy is undisturbed we can't commute.
assert(RISCVII::hasVecPolicyOp(MI.getDesc().TSFlags));
- if ((MI.getOperand(MI.getNumExplicitOperands() - 1).getImm() & 1) == 0)
+ if ((MI.getOperand(RISCVII::getVecPolicyOpNum(MI.getDesc())).getImm() &
+ 1) == 0)
return false;
// For these instructions we can only swap operand 1 and operand 3 by
@@ -3716,7 +3717,8 @@ bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
case CASE_VMA_OPCODE_LMULS(NMSUB, VV): {
// If the tail policy is undisturbed we can't commute.
assert(RISCVII::hasVecPolicyOp(MI.getDesc().TSFlags));
- if ((MI.getOperand(MI.getNumExplicitOperands() - 1).getImm() & 1) == 0)
+ if ((MI.getOperand(RISCVII::getVecPolicyOpNum(MI.getDesc())).getImm() &
+ 1) == 0)
return false;
// For these instructions we have more freedom. We can commute with the
@@ -4331,7 +4333,8 @@ MachineInstr *RISCVInstrInfo::convertToThreeAddress(MachineInstr &MI,
// If the tail policy is undisturbed we can't convert.
assert(RISCVII::hasVecPolicyOp(MI.getDesc().TSFlags) &&
MI.getNumExplicitOperands() == 6);
- if ((MI.getOperand(5).getImm() & 1) == 0)
+ if ((MI.getOperand(RISCVII::getVecPolicyOpNum(MI.getDesc())).getImm() &
+ 1) == 0)
return nullptr;
// clang-format off
``````````
</details>
https://github.com/llvm/llvm-project/pull/144175
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