[clang] [llvm] [RISCV] Remove B and Zbc extension from Andes series cpus. (PR #144022)

[Craig Topper via llvm-commits]

topperc wrote:

> I think this feature is really tough, the arm/aarch64 backends have got too much complexity from similar features, mostly because their cpus have all their optional features enabled by default.
> 
> I think if you can only enable additional extensions, that proposed syntax would probably work.
> 
> Previously, we mostly punted on this for e.g. hazard3, by only adding a `-mcpu=` option for what was actually taped out, rather than adding the configurable option. I don't know how that works for sifive/andes products that are also configurable.

The SiFive processors in LLVM are closer to a "standard" configuration than a "minimal" configuration.

https://github.com/llvm/llvm-project/pull/144022