[llvm] [TableGen] Avoid evaluating RHS of a BinOp until short-circuit is complete (PR #144021)

[Min-Yih Hsu via llvm-commits]

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@@ -67,13 +67,18 @@ def rec7 {
   bits<3> flags = { true, false, true };
 }
 
-// `!and` and `!or` should be short-circuit such that `!tail` on empty list will never
-// be evaluated.
+// `!and` and `!or` should be short-circuit such that any of the `!head` or
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mshockwave wrote:

Fixed.

https://github.com/llvm/llvm-project/pull/144021