[llvm] [TableGen] Avoid evaluating RHS of a BinOp until short-circuit is complete (PR #144021)

[Chenguang Wang via llvm-commits]

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@@ -67,13 +67,18 @@ def rec7 {
   bits<3> flags = { true, false, true };
 }
 
-// `!and` and `!or` should be short-circuit such that `!tail` on empty list will never
-// be evaluated.
+// `!and` and `!or` should be short-circuit such that any of the `!head` or
+// `!tail` on empty list below will never be evaluated.
 // CHECK: def rec8
+// CHECK:   bit v = 0;
+// CHECK:   int v2 = -1;
 // CHECK:   list<int> newSeq = [];
 // CHECK:   list<int> newSeq2 = [];
 
 class Foo <list<int> seq = []> {
+  bit v = !and(false, !head(seq));
+  int v2 = !or(-1, !head(seq));
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wecing wrote:

The last time I tried, `!if(1, 42, !head([]<int>))` did fail on HEAD. I guess this is more like a constant folding issue? But now I am fine with this commit as-is.

https://github.com/llvm/llvm-project/pull/144021