[llvm] [RISCV] Add GetVTypeMinimalPredicates for the operation supported by zvfhmin. NFC. (PR #143847)

[Luke Lau via llvm-commits]

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@@ -783,6 +783,15 @@ class GetVTypePredicates<VTypeInfo vti> {
                                      true : [HasVInstructions]);
 }
 
+class GetVTypeMinimalPredicates<VTypeInfo vti> {
+  list<Predicate> Predicates = !cond(!eq(vti.Scalar, f16) : [HasVInstructionsF16Minimal],
+                                     !eq(vti.Scalar, bf16) : [HasVInstructionsBF16Minimal],
+                                     !eq(vti.Scalar, f32) : [HasVInstructionsAnyF],
+                                     !eq(vti.Scalar, f64) : [HasVInstructionsF64],
+                                     !eq(vti.SEW, 64) : [HasVInstructionsI64],
+                                     true : [HasVInstructions]);
+}
+
----------------
lukel97 wrote:

Maybe for a separate PR, I think for anything that's not a widening/converting instruction e.g. vmerge/vrgather/vcompress/vle/vse, we can just use the integer predicate, maybe something like:

```
class GetVTypeIntPredicates<VTypeInfo vti> {
   defvar ivti = GetIntVTypeInfo<vti>;
   list<Predicate> Predicates = GetVTypePredicates<ivti>;
 }
```

Since vmerge.vvm with a fp16 vector isn't really a zvfhmin instruction, it only requires zve32x.

https://github.com/llvm/llvm-project/pull/143847