[llvm] [X86][APX] Exclusively emit setzucc to avoid false dependency (PR #142092)
Feng Zou via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 13 00:54:14 PDT 2025
https://github.com/fzou1 updated https://github.com/llvm/llvm-project/pull/142092
>From 30b8975d747ec05f7ffef4a0e1523ce28b107fda Mon Sep 17 00:00:00 2001
From: Feng Zou <feng.zou at intel.com>
Date: Thu, 29 May 2025 22:40:22 +0800
Subject: [PATCH 1/6] [X86][APX] Exclusively emit setzucc to avoid false
dependency
1. Added pattern to emit SetZUCC instruction with APX NDD enabled to avoid
false dependency with SetCC. SetCC is emitted with APX NDD disabled.
2. Reverted part of https://github.com/llvm/llvm-project/pull/129506 (changing
setzucc back to setcc + zext). Keeping the check of SetZUCC instruction will
call rewriteSetCC for SetZUCC instruction and remove redundant test after
SetZUCC in X86 Flags Copy Lowering pass.
3. Also added SetZUCC support in FixupSetCC pass to eliminate zext instruction
after SetZUCC.
---
llvm/lib/Target/X86/X86FixupSetCC.cpp | 8 +-
llvm/lib/Target/X86/X86FlagsCopyLowering.cpp | 29 +-
llvm/lib/Target/X86/X86InstrCMovSetCC.td | 8 +-
llvm/test/CodeGen/X86/apx/add.ll | 4 +-
llvm/test/CodeGen/X86/apx/and.ll | 60 +-
llvm/test/CodeGen/X86/apx/ccmp.ll | 12 +-
llvm/test/CodeGen/X86/apx/ctest.ll | 16 +-
.../CodeGen/X86/apx/flags-copy-lowering.mir | 710 ++++--
llvm/test/CodeGen/X86/apx/memfold-nd2rmw.mir | 2 +-
llvm/test/CodeGen/X86/apx/mul-i1024.ll | 70 +-
llvm/test/CodeGen/X86/apx/neg.ll | 164 +-
llvm/test/CodeGen/X86/apx/or.ll | 60 +-
llvm/test/CodeGen/X86/apx/setzucc.ll | 12 +-
llvm/test/CodeGen/X86/apx/xor.ll | 60 +-
llvm/test/CodeGen/X86/cmp.ll | 668 ++++--
llvm/test/CodeGen/X86/is_fpclass.ll | 1911 +++++++++++------
llvm/test/CodeGen/X86/select_const_i128.ll | 16 +-
17 files changed, 2631 insertions(+), 1179 deletions(-)
diff --git a/llvm/lib/Target/X86/X86FixupSetCC.cpp b/llvm/lib/Target/X86/X86FixupSetCC.cpp
index 2de89947c4519..8ea5ed695c356 100644
--- a/llvm/lib/Target/X86/X86FixupSetCC.cpp
+++ b/llvm/lib/Target/X86/X86FixupSetCC.cpp
@@ -79,10 +79,11 @@ bool X86FixupSetCCPass::runOnMachineFunction(MachineFunction &MF) {
if (MI.definesRegister(X86::EFLAGS, /*TRI=*/nullptr))
FlagsDefMI = &MI;
- // Find a setcc that is used by a zext.
+ // Find a setcc/setzucc (if ZU is enabled) that is used by a zext.
// This doesn't have to be the only use, the transformation is safe
// regardless.
- if (MI.getOpcode() != X86::SETCCr)
+ if (MI.getOpcode() != X86::SETCCr &&
+ (!ST->hasZU() || MI.getOpcode() != X86::SETZUCCr))
continue;
MachineInstr *ZExt = nullptr;
@@ -122,7 +123,8 @@ bool X86FixupSetCCPass::runOnMachineFunction(MachineFunction &MF) {
// register.
Register ZeroReg = MRI->createVirtualRegister(RC);
if (ST->hasZU()) {
- MI.setDesc(TII->get(X86::SETZUCCr));
+ if (MI.getOpcode() != X86::SETZUCCr)
+ MI.setDesc(TII->get(X86::SETZUCCr));
BuildMI(*ZExt->getParent(), ZExt, ZExt->getDebugLoc(),
TII->get(TargetOpcode::IMPLICIT_DEF), ZeroReg);
} else {
diff --git a/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp b/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
index ab6e6d0687b71..90c975e7971c9 100644
--- a/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
+++ b/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
@@ -746,8 +746,10 @@ Register X86FlagsCopyLoweringPass::promoteCondToReg(
MachineBasicBlock &TestMBB, MachineBasicBlock::iterator TestPos,
const DebugLoc &TestLoc, X86::CondCode Cond) {
Register Reg = MRI->createVirtualRegister(PromoteRC);
- auto SetI = BuildMI(TestMBB, TestPos, TestLoc, TII->get(X86::SETCCr), Reg)
- .addImm(Cond);
+ auto SetI =
+ BuildMI(TestMBB, TestPos, TestLoc,
+ TII->get(Subtarget->hasZU() ? X86::SETZUCCr : X86::SETCCr), Reg)
+ .addImm(Cond);
(void)SetI;
LLVM_DEBUG(dbgs() << " save cond: "; SetI->dump());
++NumSetCCsInserted;
@@ -791,29 +793,6 @@ void X86FlagsCopyLoweringPass::rewriteSetCC(MachineBasicBlock &MBB,
if (!CondReg)
CondReg = promoteCondToReg(MBB, Pos, Loc, Cond);
- if (X86::isSETZUCC(MI.getOpcode())) {
- // SETZUCC is generated for register only for now.
- assert(!MI.mayStore() && "Cannot handle memory variants");
- assert(MI.getOperand(0).isReg() &&
- "Cannot have a non-register defined operand to SETZUcc!");
- Register OldReg = MI.getOperand(0).getReg();
- // Drop Kill flags on the old register before replacing. CondReg may have
- // a longer live range.
- MRI->clearKillFlags(OldReg);
- for (auto &Use : MRI->use_instructions(OldReg)) {
- assert(Use.getOpcode() == X86::INSERT_SUBREG &&
- "SETZUCC should be only used by INSERT_SUBREG");
- Use.getOperand(2).setReg(CondReg);
- // Recover MOV32r0 before INSERT_SUBREG, which removed by SETZUCC.
- Register ZeroReg = MRI->createVirtualRegister(&X86::GR32RegClass);
- BuildMI(*Use.getParent(), &Use, Use.getDebugLoc(), TII->get(X86::MOV32r0),
- ZeroReg);
- Use.getOperand(1).setReg(ZeroReg);
- }
- MI.eraseFromParent();
- return;
- }
-
// Rewriting a register def is trivial: we just replace the register and
// remove the setcc.
if (!MI.mayStore()) {
diff --git a/llvm/lib/Target/X86/X86InstrCMovSetCC.td b/llvm/lib/Target/X86/X86InstrCMovSetCC.td
index 7d5d7cf4a83ab..06bf70f18e30d 100644
--- a/llvm/lib/Target/X86/X86InstrCMovSetCC.td
+++ b/llvm/lib/Target/X86/X86InstrCMovSetCC.td
@@ -137,11 +137,14 @@ let Predicates = [HasCMOV, HasCF] in {
}
// SetCC instructions.
-let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1 in {
+let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1, Predicates = [NoNDD] in {
def SETCCr : I<0x90, MRMXrCC, (outs GR8:$dst), (ins ccode:$cond),
"set${cond}\t$dst",
[(set GR8:$dst, (X86setcc timm:$cond, EFLAGS))]>,
TB, Sched<[WriteSETCC]>;
+}
+
+let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1 in {
def SETCCm : I<0x90, MRMXmCC, (outs), (ins i8mem:$dst, ccode:$cond),
"set${cond}\t$dst",
[(store (X86setcc timm:$cond, EFLAGS), addr:$dst)]>,
@@ -152,7 +155,8 @@ let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1 in {
let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1,
hasSideEffects = 0, Predicates = [In64BitMode], Predicates = [HasNDD] in {
def SETZUCCr : I<0x40, MRMXrCC, (outs GR8:$dst), (ins ccode:$cond),
- "setzu${cond}\t$dst", []>,
+ "setzu${cond}\t$dst",
+ [(set GR8:$dst, (X86setcc timm:$cond, EFLAGS))]>,
XD, ZU, NoCD8, Sched<[WriteSETCC]>;
def SETCCr_EVEX : I<0x40, MRMXrCC, (outs GR8:$dst), (ins ccode:$cond),
"set${cond}\t$dst", []>,
diff --git a/llvm/test/CodeGen/X86/apx/add.ll b/llvm/test/CodeGen/X86/apx/add.ll
index 86343811901a9..c8e1e055f8ca4 100644
--- a/llvm/test/CodeGen/X86/apx/add.ll
+++ b/llvm/test/CodeGen/X86/apx/add.ll
@@ -758,7 +758,7 @@ define i1 @add64ri_reloc(i16 %k) {
; CHECK-NEXT: addq %rax, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x01,0xc0]
; CHECK-NEXT: addq $val, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x05,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: val, kind: reloc_signed_4byte
-; CHECK-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
+; CHECK-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: add64ri_reloc:
@@ -768,7 +768,7 @@ define i1 @add64ri_reloc(i16 %k) {
; NF-NEXT: addq %rax, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x01,0xc0]
; NF-NEXT: addq $val, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x05,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: val, kind: reloc_signed_4byte
-; NF-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
+; NF-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
; NF-NEXT: retq # encoding: [0xc3]
%g = getelementptr inbounds i16, ptr @val, i16 %k
%cmp = icmp ne ptr %g, null
diff --git a/llvm/test/CodeGen/X86/apx/and.ll b/llvm/test/CodeGen/X86/apx/and.ll
index 3379ac9dec893..6de07a5b72587 100644
--- a/llvm/test/CodeGen/X86/apx/and.ll
+++ b/llvm/test/CodeGen/X86/apx/and.ll
@@ -435,7 +435,7 @@ define i1 @andflag8rr(i8 %a, i8 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: notb %sil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xf6,0xd6]
; CHECK-NEXT: andb %al, %dil, %cl # encoding: [0x62,0xf4,0x74,0x18,0x20,0xc7]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -444,7 +444,7 @@ define i1 @andflag8rr(i8 %a, i8 %b) {
; NF: # %bb.0:
; NF-NEXT: notb %sil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xf6,0xd6]
; NF-NEXT: andb %al, %dil, %cl # encoding: [0x62,0xf4,0x74,0x18,0x20,0xc7]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -460,7 +460,7 @@ define i1 @andflag16rr(i16 %a, i16 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: notw %si, %ax # encoding: [0x62,0xf4,0x7d,0x18,0xf7,0xd6]
; CHECK-NEXT: andw %ax, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x21,0xc7]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -469,7 +469,7 @@ define i1 @andflag16rr(i16 %a, i16 %b) {
; NF: # %bb.0:
; NF-NEXT: notw %si, %ax # encoding: [0x62,0xf4,0x7d,0x18,0xf7,0xd6]
; NF-NEXT: andw %ax, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x21,0xc7]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -484,7 +484,7 @@ define i1 @andflag32rr(i32 %a, i32 %b) {
; CHECK-LABEL: andflag32rr:
; CHECK: # %bb.0:
; CHECK-NEXT: andl %edi, %esi # EVEX TO LEGACY Compression encoding: [0x21,0xfe]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movl %esi, d64(%rip) # encoding: [0x89,0x35,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -492,7 +492,7 @@ define i1 @andflag32rr(i32 %a, i32 %b) {
; NF-LABEL: andflag32rr:
; NF: # %bb.0:
; NF-NEXT: andl %edi, %esi # EVEX TO LEGACY Compression encoding: [0x21,0xfe]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movl %esi, d64(%rip) # encoding: [0x89,0x35,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -506,7 +506,7 @@ define i1 @andflag64rr(i64 %a, i64 %b) {
; CHECK-LABEL: andflag64rr:
; CHECK: # %bb.0:
; CHECK-NEXT: andq %rdi, %rsi # EVEX TO LEGACY Compression encoding: [0x48,0x21,0xfe]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movq %rsi, d64(%rip) # encoding: [0x48,0x89,0x35,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -514,7 +514,7 @@ define i1 @andflag64rr(i64 %a, i64 %b) {
; NF-LABEL: andflag64rr:
; NF: # %bb.0:
; NF-NEXT: andq %rdi, %rsi # EVEX TO LEGACY Compression encoding: [0x48,0x21,0xfe]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movq %rsi, d64(%rip) # encoding: [0x48,0x89,0x35,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -529,7 +529,7 @@ define i1 @andflag8rm(ptr %ptr, i8 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: notb %sil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xf6,0xd6]
; CHECK-NEXT: andb (%rdi), %al, %cl # encoding: [0x62,0xf4,0x74,0x18,0x22,0x07]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -538,7 +538,7 @@ define i1 @andflag8rm(ptr %ptr, i8 %b) {
; NF: # %bb.0:
; NF-NEXT: notb %sil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xf6,0xd6]
; NF-NEXT: andb (%rdi), %al, %cl # encoding: [0x62,0xf4,0x74,0x18,0x22,0x07]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -555,7 +555,7 @@ define i1 @andflag16rm(ptr %ptr, i16 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: notw %si, %ax # encoding: [0x62,0xf4,0x7d,0x18,0xf7,0xd6]
; CHECK-NEXT: andw (%rdi), %ax, %cx # encoding: [0x62,0xf4,0x75,0x18,0x23,0x07]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -564,7 +564,7 @@ define i1 @andflag16rm(ptr %ptr, i16 %b) {
; NF: # %bb.0:
; NF-NEXT: notw %si, %ax # encoding: [0x62,0xf4,0x7d,0x18,0xf7,0xd6]
; NF-NEXT: andw (%rdi), %ax, %cx # encoding: [0x62,0xf4,0x75,0x18,0x23,0x07]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -580,7 +580,7 @@ define i1 @andflag32rm(ptr %ptr, i32 %b) {
; CHECK-LABEL: andflag32rm:
; CHECK: # %bb.0:
; CHECK-NEXT: andl (%rdi), %esi # EVEX TO LEGACY Compression encoding: [0x23,0x37]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movl %esi, d64(%rip) # encoding: [0x89,0x35,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -588,7 +588,7 @@ define i1 @andflag32rm(ptr %ptr, i32 %b) {
; NF-LABEL: andflag32rm:
; NF: # %bb.0:
; NF-NEXT: andl (%rdi), %esi # EVEX TO LEGACY Compression encoding: [0x23,0x37]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movl %esi, d64(%rip) # encoding: [0x89,0x35,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -603,7 +603,7 @@ define i1 @andflag64rm(ptr %ptr, i64 %b) {
; CHECK-LABEL: andflag64rm:
; CHECK: # %bb.0:
; CHECK-NEXT: andq (%rdi), %rsi # EVEX TO LEGACY Compression encoding: [0x48,0x23,0x37]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movq %rsi, d64(%rip) # encoding: [0x48,0x89,0x35,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -611,7 +611,7 @@ define i1 @andflag64rm(ptr %ptr, i64 %b) {
; NF-LABEL: andflag64rm:
; NF: # %bb.0:
; NF-NEXT: andq (%rdi), %rsi # EVEX TO LEGACY Compression encoding: [0x48,0x23,0x37]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movq %rsi, d64(%rip) # encoding: [0x48,0x89,0x35,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -626,7 +626,7 @@ define i1 @andflag8ri(i8 %a) {
; CHECK-LABEL: andflag8ri:
; CHECK: # %bb.0:
; CHECK-NEXT: andb $-124, %dil, %cl # encoding: [0x62,0xf4,0x74,0x18,0x80,0xe7,0x84]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -634,7 +634,7 @@ define i1 @andflag8ri(i8 %a) {
; NF-LABEL: andflag8ri:
; NF: # %bb.0:
; NF-NEXT: andb $-124, %dil, %cl # encoding: [0x62,0xf4,0x74,0x18,0x80,0xe7,0x84]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -650,7 +650,7 @@ define i1 @andflag16ri(i16 %a) {
; CHECK: # %bb.0:
; CHECK-NEXT: andw $-1235, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x81,0xe7,0x2d,0xfb]
; CHECK-NEXT: # imm = 0xFB2D
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -659,7 +659,7 @@ define i1 @andflag16ri(i16 %a) {
; NF: # %bb.0:
; NF-NEXT: andw $-1235, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x81,0xe7,0x2d,0xfb]
; NF-NEXT: # imm = 0xFB2D
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -675,7 +675,7 @@ define i1 @andflag32ri(i32 %a) {
; CHECK: # %bb.0:
; CHECK-NEXT: andl $123456, %edi # EVEX TO LEGACY Compression encoding: [0x81,0xe7,0x40,0xe2,0x01,0x00]
; CHECK-NEXT: # imm = 0x1E240
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movl %edi, d64(%rip) # encoding: [0x89,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -684,7 +684,7 @@ define i1 @andflag32ri(i32 %a) {
; NF: # %bb.0:
; NF-NEXT: andl $123456, %edi # EVEX TO LEGACY Compression encoding: [0x81,0xe7,0x40,0xe2,0x01,0x00]
; NF-NEXT: # imm = 0x1E240
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movl %edi, d64(%rip) # encoding: [0x89,0x3d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -699,7 +699,7 @@ define i1 @andflag64ri(i64 %a) {
; CHECK: # %bb.0:
; CHECK-NEXT: andq $123456, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x81,0xe7,0x40,0xe2,0x01,0x00]
; CHECK-NEXT: # imm = 0x1E240
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -708,7 +708,7 @@ define i1 @andflag64ri(i64 %a) {
; NF: # %bb.0:
; NF-NEXT: andq $123456, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x81,0xe7,0x40,0xe2,0x01,0x00]
; NF-NEXT: # imm = 0x1E240
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -722,7 +722,7 @@ define i1 @andflag16ri8(i16 %a) {
; CHECK-LABEL: andflag16ri8:
; CHECK: # %bb.0:
; CHECK-NEXT: andw $-124, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x83,0xe7,0x84]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -730,7 +730,7 @@ define i1 @andflag16ri8(i16 %a) {
; NF-LABEL: andflag16ri8:
; NF: # %bb.0:
; NF-NEXT: andw $-124, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x83,0xe7,0x84]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -745,7 +745,7 @@ define i1 @andflag32ri8(i32 %a) {
; CHECK-LABEL: andflag32ri8:
; CHECK: # %bb.0:
; CHECK-NEXT: andl $123, %edi # EVEX TO LEGACY Compression encoding: [0x83,0xe7,0x7b]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movl %edi, d64(%rip) # encoding: [0x89,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -753,7 +753,7 @@ define i1 @andflag32ri8(i32 %a) {
; NF-LABEL: andflag32ri8:
; NF: # %bb.0:
; NF-NEXT: andl $123, %edi # EVEX TO LEGACY Compression encoding: [0x83,0xe7,0x7b]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movl %edi, d64(%rip) # encoding: [0x89,0x3d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -767,7 +767,7 @@ define i1 @andflag64ri8(i64 %a) {
; CHECK-LABEL: andflag64ri8:
; CHECK: # %bb.0:
; CHECK-NEXT: andq $123, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x83,0xe7,0x7b]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -775,7 +775,7 @@ define i1 @andflag64ri8(i64 %a) {
; NF-LABEL: andflag64ri8:
; NF: # %bb.0:
; NF-NEXT: andq $123, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x83,0xe7,0x7b]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
diff --git a/llvm/test/CodeGen/X86/apx/ccmp.ll b/llvm/test/CodeGen/X86/apx/ccmp.ll
index 7bd8aeea8863b..210079537a38b 100644
--- a/llvm/test/CodeGen/X86/apx/ccmp.ll
+++ b/llvm/test/CodeGen/X86/apx/ccmp.ll
@@ -428,9 +428,9 @@ define i8 @ccmp8ri_zf_double_p(i8 %a, double %b, i8* nocapture %c) {
; NDD-LABEL: ccmp8ri_zf_double_p:
; NDD: # %bb.0: # %entry
; NDD-NEXT: cmpb $123, %dil # encoding: [0x40,0x80,0xff,0x7b]
-; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
+; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
; NDD-NEXT: ucomisd %xmm0, %xmm0 # encoding: [0x66,0x0f,0x2e,0xc0]
-; NDD-NEXT: setp %cl # encoding: [0x0f,0x9a,0xc1]
+; NDD-NEXT: setzup %cl # encoding: [0x62,0xf4,0x7f,0x18,0x4a,0xc1]
; NDD-NEXT: andb %cl, %al # EVEX TO LEGACY Compression encoding: [0x20,0xc8]
; NDD-NEXT: cmpb $1, %al # encoding: [0x3c,0x01]
; NDD-NEXT: jne .LBB10_2 # encoding: [0x75,A]
@@ -474,9 +474,9 @@ define i8 @ccmp8ri_zf_double_np(i8 %a, double %b, i8* nocapture %c) {
; NDD-LABEL: ccmp8ri_zf_double_np:
; NDD: # %bb.0: # %entry
; NDD-NEXT: cmpb $123, %dil # encoding: [0x40,0x80,0xff,0x7b]
-; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
+; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
; NDD-NEXT: ucomisd %xmm0, %xmm0 # encoding: [0x66,0x0f,0x2e,0xc0]
-; NDD-NEXT: setnp %cl # encoding: [0x0f,0x9b,0xc1]
+; NDD-NEXT: setzunp %cl # encoding: [0x62,0xf4,0x7f,0x18,0x4b,0xc1]
; NDD-NEXT: andb %cl, %al # EVEX TO LEGACY Compression encoding: [0x20,0xc8]
; NDD-NEXT: cmpb $1, %al # encoding: [0x3c,0x01]
; NDD-NEXT: jne .LBB11_2 # encoding: [0x75,A]
@@ -1215,7 +1215,7 @@ define i32 @ccmp_nobranch(i32 noundef %a, i32 noundef %b) {
; NDD: # %bb.0: # %entry
; NDD-NEXT: testl %edi, %edi # encoding: [0x85,0xff]
; NDD-NEXT: ccmplel {dfv=} $2, %esi # encoding: [0x62,0xf4,0x04,0x0e,0x83,0xfe,0x02]
-; NDD-NEXT: setge %al # encoding: [0x0f,0x9d,0xc0]
+; NDD-NEXT: setzuge %al # encoding: [0x62,0xf4,0x7f,0x18,0x4d,0xc0]
; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
entry:
@@ -1241,7 +1241,7 @@ define i32 @ccmp_continous_nobranch(i32 noundef %a, i32 noundef %b, i32 noundef
; NDD-NEXT: cmpl $2, %edi # encoding: [0x83,0xff,0x02]
; NDD-NEXT: ccmpll {dfv=sf} $2, %esi # encoding: [0x62,0xf4,0x24,0x0c,0x83,0xfe,0x02]
; NDD-NEXT: ccmpll {dfv=sf} $4, %edx # encoding: [0x62,0xf4,0x24,0x0c,0x83,0xfa,0x04]
-; NDD-NEXT: setge %al # encoding: [0x0f,0x9d,0xc0]
+; NDD-NEXT: setzuge %al # encoding: [0x62,0xf4,0x7f,0x18,0x4d,0xc0]
; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
entry:
diff --git a/llvm/test/CodeGen/X86/apx/ctest.ll b/llvm/test/CodeGen/X86/apx/ctest.ll
index 5f3ec8a19d0a4..7477b687c427b 100644
--- a/llvm/test/CodeGen/X86/apx/ctest.ll
+++ b/llvm/test/CodeGen/X86/apx/ctest.ll
@@ -95,9 +95,9 @@ define i8 @ctest8rr_zf_double_p(i8 %a, double %b, i8* nocapture %c) {
; NDD-LABEL: ctest8rr_zf_double_p:
; NDD: # %bb.0: # %entry
; NDD-NEXT: testb %dil, %dil
-; NDD-NEXT: setne %al
+; NDD-NEXT: setzune %al
; NDD-NEXT: ucomisd %xmm0, %xmm0
-; NDD-NEXT: setp %cl
+; NDD-NEXT: setzup %cl
; NDD-NEXT: andb %cl, %al
; NDD-NEXT: cmpb $1, %al
; NDD-NEXT: jne .LBB2_2
@@ -139,9 +139,9 @@ define i8 @ctest8rr_zf_double_np(i8 %a, double %b, i8* nocapture %c) {
; NDD-LABEL: ctest8rr_zf_double_np:
; NDD: # %bb.0: # %entry
; NDD-NEXT: testb %dil, %dil
-; NDD-NEXT: setne %al
+; NDD-NEXT: setzune %al
; NDD-NEXT: ucomisd %xmm0, %xmm0
-; NDD-NEXT: setnp %cl
+; NDD-NEXT: setzunp %cl
; NDD-NEXT: andb %cl, %al
; NDD-NEXT: cmpb $1, %al
; NDD-NEXT: jne .LBB3_2
@@ -858,7 +858,7 @@ define i32 @ctest_nobranch(i32 noundef %a, i32 noundef %b) {
; NDD: # %bb.0: # %entry
; NDD-NEXT: testl %edi, %edi
; NDD-NEXT: ctestlel {dfv=} %esi, %esi
-; NDD-NEXT: setg %al
+; NDD-NEXT: setzug %al
; NDD-NEXT: movzbl %al, %eax
; NDD-NEXT: retq
entry:
@@ -884,7 +884,7 @@ define i32 @ctest_continous_nobranch(i32 noundef %a, i32 noundef %b, i32 noundef
; NDD-NEXT: testl %edi, %edi
; NDD-NEXT: ctestlel {dfv=sf} %esi, %esi
; NDD-NEXT: ctestsl {dfv=zf} %edx, %edx
-; NDD-NEXT: setg %al
+; NDD-NEXT: setzug %al
; NDD-NEXT: movzbl %al, %eax
; NDD-NEXT: retq
entry:
@@ -962,10 +962,10 @@ define void @cmp_srem(ptr %p, i32 %a, ptr %b) {
; NDD-NEXT: cltd
; NDD-NEXT: {nf} idivl %edi
; NDD-NEXT: ctestnel {dfv=} %edx, %edx
-; NDD-NEXT: sete %al
+; NDD-NEXT: setzue %al
; NDD-NEXT: cmpl $1, %esi
; NDD-NEXT: ccmpael {dfv=zf} $1, %edi
-; NDD-NEXT: sete %dl
+; NDD-NEXT: setzue %dl
; NDD-NEXT: orb %dl, %al
; NDD-NEXT: movb %al, (%rcx)
; NDD-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/apx/flags-copy-lowering.mir b/llvm/test/CodeGen/X86/apx/flags-copy-lowering.mir
index a78e051fe65f5..36f0e4d063991 100644
--- a/llvm/test/CodeGen/X86/apx/flags-copy-lowering.mir
+++ b/llvm/test/CodeGen/X86/apx/flags-copy-lowering.mir
@@ -1,7 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=x86_64 -run-pass x86-flags-copy-lowering -mattr=+ndd -verify-machineinstrs -o - %s | FileCheck --check-prefixes=CHECK,NDD %s
-# RUN: llc -mtriple=x86_64 -run-pass x86-flags-copy-lowering -mattr=+ndd,+nf -verify-machineinstrs -o - %s | FileCheck --check-prefixes=CHECK,NDD-NF %s
-# RUN: llc -mtriple=x86_64 -run-pass x86-flags-copy-lowering -mattr=+ndd,+nf -x86-enable-apx-for-relocation=true -verify-machineinstrs -o - %s | FileCheck --check-prefixes=CHECK,NDD-NF %s
+# RUN: llc -mtriple=x86_64 -run-pass x86-flags-copy-lowering -mattr=+ndd -verify-machineinstrs -o - %s | FileCheck --check-prefixes=NDD %s
+# RUN: llc -mtriple=x86_64 -run-pass x86-flags-copy-lowering -mattr=+ndd,+nf -verify-machineinstrs -o - %s | FileCheck --check-prefixes=NDD-NF %s
+# RUN: llc -mtriple=x86_64 -run-pass x86-flags-copy-lowering -mattr=+ndd,+nf,+zu -verify-machineinstrs -o - %s | FileCheck --check-prefixes=NDD-NF-ZU %s
+# RUN: llc -mtriple=x86_64 -run-pass x86-flags-copy-lowering -mattr=+ndd,+nf -x86-enable-apx-for-relocation=true -verify-machineinstrs -o - %s | FileCheck --check-prefixes=NDD-NF %s
# Lower various interesting copy patterns of EFLAGS without using LAHF/SAHF.
@@ -12,19 +13,47 @@ body: |
bb.0:
liveins: $rdi, $rsi
- ; CHECK-LABEL: name: test_adc
- ; CHECK: liveins: $rdi, $rsi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; CHECK-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
- ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
- ; CHECK-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; CHECK-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETCCr]], 255, implicit-def $eflags
- ; CHECK-NEXT: [[ADC64ri32_ND:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADD64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
- ; CHECK-NEXT: [[ADC64ri32_ND1:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADC64ri32_ND]], 42, implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[ADC64ri32_ND1]]
- ; CHECK-NEXT: RET 0
+ ; NDD-LABEL: name: test_adc
+ ; NDD: liveins: $rdi, $rsi
+ ; NDD-NEXT: {{ $}}
+ ; NDD-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; NDD-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; NDD-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; NDD-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
+ ; NDD-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; NDD-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETCCr]], 255, implicit-def $eflags
+ ; NDD-NEXT: [[ADC64ri32_ND:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADD64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
+ ; NDD-NEXT: [[ADC64ri32_ND1:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADC64ri32_ND]], 42, implicit-def $eflags, implicit $eflags
+ ; NDD-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[ADC64ri32_ND1]]
+ ; NDD-NEXT: RET 0
+ ;
+ ; NDD-NF-LABEL: name: test_adc
+ ; NDD-NF: liveins: $rdi, $rsi
+ ; NDD-NF-NEXT: {{ $}}
+ ; NDD-NF-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; NDD-NF-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; NDD-NF-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; NDD-NF-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
+ ; NDD-NF-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; NDD-NF-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETCCr]], 255, implicit-def $eflags
+ ; NDD-NF-NEXT: [[ADC64ri32_ND:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADD64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
+ ; NDD-NF-NEXT: [[ADC64ri32_ND1:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADC64ri32_ND]], 42, implicit-def $eflags, implicit $eflags
+ ; NDD-NF-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[ADC64ri32_ND1]]
+ ; NDD-NF-NEXT: RET 0
+ ;
+ ; NDD-NF-ZU-LABEL: name: test_adc
+ ; NDD-NF-ZU: liveins: $rdi, $rsi
+ ; NDD-NF-ZU-NEXT: {{ $}}
+ ; NDD-NF-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; NDD-NF-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; NDD-NF-ZU-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; NDD-NF-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; NDD-NF-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr]], 255, implicit-def $eflags
+ ; NDD-NF-ZU-NEXT: [[ADC64ri32_ND:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADD64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
+ ; NDD-NF-ZU-NEXT: [[ADC64ri32_ND1:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADC64ri32_ND]], 42, implicit-def $eflags, implicit $eflags
+ ; NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[ADC64ri32_ND1]]
+ ; NDD-NF-ZU-NEXT: RET 0
%0:gr64 = COPY $rdi
%1:gr64 = COPY $rsi
%2:gr64 = ADD64rr_ND %0, %1, implicit-def $eflags
@@ -46,19 +75,47 @@ body: |
bb.0:
liveins: $rdi, $rsi
- ; CHECK-LABEL: name: test_sbb
- ; CHECK: liveins: $rdi, $rsi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; CHECK-NEXT: [[SUB64rr_ND:%[0-9]+]]:gr64 = SUB64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
- ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
- ; CHECK-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; CHECK-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETCCr]], 255, implicit-def $eflags
- ; CHECK-NEXT: [[SBB64ri32_ND:%[0-9]+]]:gr64 = SBB64ri32_ND [[SUB64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
- ; CHECK-NEXT: [[SBB64ri32_ND1:%[0-9]+]]:gr64 = SBB64ri32_ND [[SBB64ri32_ND]], 42, implicit-def dead $eflags, implicit killed $eflags
- ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[SBB64ri32_ND1]]
- ; CHECK-NEXT: RET 0
+ ; NDD-LABEL: name: test_sbb
+ ; NDD: liveins: $rdi, $rsi
+ ; NDD-NEXT: {{ $}}
+ ; NDD-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; NDD-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; NDD-NEXT: [[SUB64rr_ND:%[0-9]+]]:gr64 = SUB64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; NDD-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
+ ; NDD-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; NDD-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETCCr]], 255, implicit-def $eflags
+ ; NDD-NEXT: [[SBB64ri32_ND:%[0-9]+]]:gr64 = SBB64ri32_ND [[SUB64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
+ ; NDD-NEXT: [[SBB64ri32_ND1:%[0-9]+]]:gr64 = SBB64ri32_ND [[SBB64ri32_ND]], 42, implicit-def dead $eflags, implicit killed $eflags
+ ; NDD-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[SBB64ri32_ND1]]
+ ; NDD-NEXT: RET 0
+ ;
+ ; NDD-NF-LABEL: name: test_sbb
+ ; NDD-NF: liveins: $rdi, $rsi
+ ; NDD-NF-NEXT: {{ $}}
+ ; NDD-NF-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; NDD-NF-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; NDD-NF-NEXT: [[SUB64rr_ND:%[0-9]+]]:gr64 = SUB64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; NDD-NF-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
+ ; NDD-NF-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; NDD-NF-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETCCr]], 255, implicit-def $eflags
+ ; NDD-NF-NEXT: [[SBB64ri32_ND:%[0-9]+]]:gr64 = SBB64ri32_ND [[SUB64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
+ ; NDD-NF-NEXT: [[SBB64ri32_ND1:%[0-9]+]]:gr64 = SBB64ri32_ND [[SBB64ri32_ND]], 42, implicit-def dead $eflags, implicit killed $eflags
+ ; NDD-NF-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[SBB64ri32_ND1]]
+ ; NDD-NF-NEXT: RET 0
+ ;
+ ; NDD-NF-ZU-LABEL: name: test_sbb
+ ; NDD-NF-ZU: liveins: $rdi, $rsi
+ ; NDD-NF-ZU-NEXT: {{ $}}
+ ; NDD-NF-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; NDD-NF-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; NDD-NF-ZU-NEXT: [[SUB64rr_ND:%[0-9]+]]:gr64 = SUB64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; NDD-NF-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; NDD-NF-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr]], 255, implicit-def $eflags
+ ; NDD-NF-ZU-NEXT: [[SBB64ri32_ND:%[0-9]+]]:gr64 = SBB64ri32_ND [[SUB64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
+ ; NDD-NF-ZU-NEXT: [[SBB64ri32_ND1:%[0-9]+]]:gr64 = SBB64ri32_ND [[SBB64ri32_ND]], 42, implicit-def dead $eflags, implicit killed $eflags
+ ; NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[SBB64ri32_ND1]]
+ ; NDD-NF-ZU-NEXT: RET 0
%0:gr64 = COPY $rdi
%1:gr64 = COPY $rsi
%2:gr64 = SUB64rr_ND %0, %1, implicit-def $eflags
@@ -80,19 +137,47 @@ body: |
bb.0:
liveins: $rdi, $rsi
- ; CHECK-LABEL: name: test_rcl
- ; CHECK: liveins: $rdi, $rsi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; CHECK-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
- ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
- ; CHECK-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; CHECK-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETCCr]], 255, implicit-def $eflags
- ; CHECK-NEXT: [[RCL64r1_ND:%[0-9]+]]:gr64 = RCL64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
- ; CHECK-NEXT: [[RCL64r1_ND1:%[0-9]+]]:gr64 = RCL64r1_ND [[RCL64r1_ND]], implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCL64r1_ND1]]
- ; CHECK-NEXT: RET 0
+ ; NDD-LABEL: name: test_rcl
+ ; NDD: liveins: $rdi, $rsi
+ ; NDD-NEXT: {{ $}}
+ ; NDD-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; NDD-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; NDD-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; NDD-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
+ ; NDD-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; NDD-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETCCr]], 255, implicit-def $eflags
+ ; NDD-NEXT: [[RCL64r1_ND:%[0-9]+]]:gr64 = RCL64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
+ ; NDD-NEXT: [[RCL64r1_ND1:%[0-9]+]]:gr64 = RCL64r1_ND [[RCL64r1_ND]], implicit-def $eflags, implicit $eflags
+ ; NDD-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCL64r1_ND1]]
+ ; NDD-NEXT: RET 0
+ ;
+ ; NDD-NF-LABEL: name: test_rcl
+ ; NDD-NF: liveins: $rdi, $rsi
+ ; NDD-NF-NEXT: {{ $}}
+ ; NDD-NF-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; NDD-NF-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; NDD-NF-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; NDD-NF-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
+ ; NDD-NF-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; NDD-NF-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETCCr]], 255, implicit-def $eflags
+ ; NDD-NF-NEXT: [[RCL64r1_ND:%[0-9]+]]:gr64 = RCL64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
+ ; NDD-NF-NEXT: [[RCL64r1_ND1:%[0-9]+]]:gr64 = RCL64r1_ND [[RCL64r1_ND]], implicit-def $eflags, implicit $eflags
+ ; NDD-NF-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCL64r1_ND1]]
+ ; NDD-NF-NEXT: RET 0
+ ;
+ ; NDD-NF-ZU-LABEL: name: test_rcl
+ ; NDD-NF-ZU: liveins: $rdi, $rsi
+ ; NDD-NF-ZU-NEXT: {{ $}}
+ ; NDD-NF-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; NDD-NF-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; NDD-NF-ZU-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; NDD-NF-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; NDD-NF-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr]], 255, implicit-def $eflags
+ ; NDD-NF-ZU-NEXT: [[RCL64r1_ND:%[0-9]+]]:gr64 = RCL64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
+ ; NDD-NF-ZU-NEXT: [[RCL64r1_ND1:%[0-9]+]]:gr64 = RCL64r1_ND [[RCL64r1_ND]], implicit-def $eflags, implicit $eflags
+ ; NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCL64r1_ND1]]
+ ; NDD-NF-ZU-NEXT: RET 0
%0:gr64 = COPY $rdi
%1:gr64 = COPY $rsi
%2:gr64 = ADD64rr_ND %0, %1, implicit-def $eflags
@@ -114,19 +199,47 @@ body: |
bb.0:
liveins: $rdi, $rsi
- ; CHECK-LABEL: name: test_rcr
- ; CHECK: liveins: $rdi, $rsi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; CHECK-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
- ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
- ; CHECK-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; CHECK-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETCCr]], 255, implicit-def $eflags
- ; CHECK-NEXT: [[RCR64r1_ND:%[0-9]+]]:gr64 = RCR64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
- ; CHECK-NEXT: [[RCR64r1_ND1:%[0-9]+]]:gr64 = RCR64r1_ND [[RCR64r1_ND]], implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCR64r1_ND1]]
- ; CHECK-NEXT: RET 0
+ ; NDD-LABEL: name: test_rcr
+ ; NDD: liveins: $rdi, $rsi
+ ; NDD-NEXT: {{ $}}
+ ; NDD-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; NDD-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; NDD-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; NDD-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
+ ; NDD-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; NDD-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETCCr]], 255, implicit-def $eflags
+ ; NDD-NEXT: [[RCR64r1_ND:%[0-9]+]]:gr64 = RCR64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
+ ; NDD-NEXT: [[RCR64r1_ND1:%[0-9]+]]:gr64 = RCR64r1_ND [[RCR64r1_ND]], implicit-def $eflags, implicit $eflags
+ ; NDD-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCR64r1_ND1]]
+ ; NDD-NEXT: RET 0
+ ;
+ ; NDD-NF-LABEL: name: test_rcr
+ ; NDD-NF: liveins: $rdi, $rsi
+ ; NDD-NF-NEXT: {{ $}}
+ ; NDD-NF-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; NDD-NF-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; NDD-NF-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; NDD-NF-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
+ ; NDD-NF-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; NDD-NF-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETCCr]], 255, implicit-def $eflags
+ ; NDD-NF-NEXT: [[RCR64r1_ND:%[0-9]+]]:gr64 = RCR64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
+ ; NDD-NF-NEXT: [[RCR64r1_ND1:%[0-9]+]]:gr64 = RCR64r1_ND [[RCR64r1_ND]], implicit-def $eflags, implicit $eflags
+ ; NDD-NF-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCR64r1_ND1]]
+ ; NDD-NF-NEXT: RET 0
+ ;
+ ; NDD-NF-ZU-LABEL: name: test_rcr
+ ; NDD-NF-ZU: liveins: $rdi, $rsi
+ ; NDD-NF-ZU-NEXT: {{ $}}
+ ; NDD-NF-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; NDD-NF-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; NDD-NF-ZU-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; NDD-NF-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; NDD-NF-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr]], 255, implicit-def $eflags
+ ; NDD-NF-ZU-NEXT: [[RCR64r1_ND:%[0-9]+]]:gr64 = RCR64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
+ ; NDD-NF-ZU-NEXT: [[RCR64r1_ND1:%[0-9]+]]:gr64 = RCR64r1_ND [[RCR64r1_ND]], implicit-def $eflags, implicit $eflags
+ ; NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCR64r1_ND1]]
+ ; NDD-NF-ZU-NEXT: RET 0
%0:gr64 = COPY $rdi
%1:gr64 = COPY $rsi
%2:gr64 = ADD64rr_ND %0, %1, implicit-def $eflags
@@ -148,29 +261,77 @@ body: |
bb.0:
liveins: $rdi, $rsi
- ; CHECK-LABEL: name: test_cmov
- ; CHECK: liveins: $rdi, $rsi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; CHECK-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
- ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
- ; CHECK-NEXT: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
- ; CHECK-NEXT: [[SETCCr2:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
- ; CHECK-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; CHECK-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
- ; CHECK-NEXT: [[CMOV64rr_ND:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
- ; CHECK-NEXT: TEST8rr [[SETCCr1]], [[SETCCr1]], implicit-def $eflags
- ; CHECK-NEXT: [[CMOV64rr_ND1:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
- ; CHECK-NEXT: TEST8rr [[SETCCr2]], [[SETCCr2]], implicit-def $eflags
- ; CHECK-NEXT: [[CMOV64rr_ND2:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
- ; CHECK-NEXT: TEST8rr [[SETCCr2]], [[SETCCr2]], implicit-def $eflags
- ; CHECK-NEXT: [[CMOV64rr_ND3:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
- ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND]]
- ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND1]]
- ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND2]]
- ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND3]]
- ; CHECK-NEXT: RET 0
+ ; NDD-LABEL: name: test_cmov
+ ; NDD: liveins: $rdi, $rsi
+ ; NDD-NEXT: {{ $}}
+ ; NDD-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; NDD-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; NDD-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
+ ; NDD-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
+ ; NDD-NEXT: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
+ ; NDD-NEXT: [[SETCCr2:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
+ ; NDD-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; NDD-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
+ ; NDD-NEXT: [[CMOV64rr_ND:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; NDD-NEXT: TEST8rr [[SETCCr1]], [[SETCCr1]], implicit-def $eflags
+ ; NDD-NEXT: [[CMOV64rr_ND1:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; NDD-NEXT: TEST8rr [[SETCCr2]], [[SETCCr2]], implicit-def $eflags
+ ; NDD-NEXT: [[CMOV64rr_ND2:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; NDD-NEXT: TEST8rr [[SETCCr2]], [[SETCCr2]], implicit-def $eflags
+ ; NDD-NEXT: [[CMOV64rr_ND3:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
+ ; NDD-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND]]
+ ; NDD-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND1]]
+ ; NDD-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND2]]
+ ; NDD-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND3]]
+ ; NDD-NEXT: RET 0
+ ;
+ ; NDD-NF-LABEL: name: test_cmov
+ ; NDD-NF: liveins: $rdi, $rsi
+ ; NDD-NF-NEXT: {{ $}}
+ ; NDD-NF-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; NDD-NF-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; NDD-NF-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
+ ; NDD-NF-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
+ ; NDD-NF-NEXT: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
+ ; NDD-NF-NEXT: [[SETCCr2:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
+ ; NDD-NF-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; NDD-NF-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
+ ; NDD-NF-NEXT: [[CMOV64rr_ND:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; NDD-NF-NEXT: TEST8rr [[SETCCr1]], [[SETCCr1]], implicit-def $eflags
+ ; NDD-NF-NEXT: [[CMOV64rr_ND1:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; NDD-NF-NEXT: TEST8rr [[SETCCr2]], [[SETCCr2]], implicit-def $eflags
+ ; NDD-NF-NEXT: [[CMOV64rr_ND2:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; NDD-NF-NEXT: TEST8rr [[SETCCr2]], [[SETCCr2]], implicit-def $eflags
+ ; NDD-NF-NEXT: [[CMOV64rr_ND3:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
+ ; NDD-NF-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND]]
+ ; NDD-NF-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND1]]
+ ; NDD-NF-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND2]]
+ ; NDD-NF-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND3]]
+ ; NDD-NF-NEXT: RET 0
+ ;
+ ; NDD-NF-ZU-LABEL: name: test_cmov
+ ; NDD-NF-ZU: liveins: $rdi, $rsi
+ ; NDD-NF-ZU-NEXT: {{ $}}
+ ; NDD-NF-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; NDD-NF-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; NDD-NF-ZU-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
+ ; NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; NDD-NF-ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; NDD-NF-ZU-NEXT: [[SETZUCCr2:%[0-9]+]]:gr8 = SETZUCCr 4, implicit $eflags
+ ; NDD-NF-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; NDD-NF-ZU-NEXT: [[CMOV64rr_ND:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr1]], [[SETZUCCr1]], implicit-def $eflags
+ ; NDD-NF-ZU-NEXT: [[CMOV64rr_ND1:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
+ ; NDD-NF-ZU-NEXT: [[CMOV64rr_ND2:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
+ ; NDD-NF-ZU-NEXT: [[CMOV64rr_ND3:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
+ ; NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND]]
+ ; NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND1]]
+ ; NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND2]]
+ ; NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND3]]
+ ; NDD-NF-ZU-NEXT: RET 0
%0:gr64 = COPY $rdi
%1:gr64 = COPY $rsi
CMP64rr %0, %1, implicit-def $eflags
@@ -196,29 +357,77 @@ body: |
bb.0:
liveins: $rdi, $rsi
- ; CHECK-LABEL: name: test_cfcmov
- ; CHECK: liveins: $rdi, $rsi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; CHECK-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
- ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
- ; CHECK-NEXT: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
- ; CHECK-NEXT: [[SETCCr2:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
- ; CHECK-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; CHECK-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
- ; CHECK-NEXT: [[CFCMOV64rr:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
- ; CHECK-NEXT: TEST8rr [[SETCCr1]], [[SETCCr1]], implicit-def $eflags
- ; CHECK-NEXT: [[CFCMOV64rr1:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
- ; CHECK-NEXT: TEST8rr [[SETCCr2]], [[SETCCr2]], implicit-def $eflags
- ; CHECK-NEXT: [[CFCMOV64rr_ND:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
- ; CHECK-NEXT: TEST8rr [[SETCCr2]], [[SETCCr2]], implicit-def $eflags
- ; CHECK-NEXT: [[CFCMOV64rr_ND1:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
- ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr]]
- ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr1]]
- ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND]]
- ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND1]]
- ; CHECK-NEXT: RET 0
+ ; NDD-LABEL: name: test_cfcmov
+ ; NDD: liveins: $rdi, $rsi
+ ; NDD-NEXT: {{ $}}
+ ; NDD-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; NDD-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; NDD-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
+ ; NDD-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
+ ; NDD-NEXT: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
+ ; NDD-NEXT: [[SETCCr2:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
+ ; NDD-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; NDD-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
+ ; NDD-NEXT: [[CFCMOV64rr:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
+ ; NDD-NEXT: TEST8rr [[SETCCr1]], [[SETCCr1]], implicit-def $eflags
+ ; NDD-NEXT: [[CFCMOV64rr1:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
+ ; NDD-NEXT: TEST8rr [[SETCCr2]], [[SETCCr2]], implicit-def $eflags
+ ; NDD-NEXT: [[CFCMOV64rr_ND:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; NDD-NEXT: TEST8rr [[SETCCr2]], [[SETCCr2]], implicit-def $eflags
+ ; NDD-NEXT: [[CFCMOV64rr_ND1:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
+ ; NDD-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr]]
+ ; NDD-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr1]]
+ ; NDD-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND]]
+ ; NDD-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND1]]
+ ; NDD-NEXT: RET 0
+ ;
+ ; NDD-NF-LABEL: name: test_cfcmov
+ ; NDD-NF: liveins: $rdi, $rsi
+ ; NDD-NF-NEXT: {{ $}}
+ ; NDD-NF-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; NDD-NF-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; NDD-NF-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
+ ; NDD-NF-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
+ ; NDD-NF-NEXT: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
+ ; NDD-NF-NEXT: [[SETCCr2:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
+ ; NDD-NF-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; NDD-NF-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
+ ; NDD-NF-NEXT: [[CFCMOV64rr:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
+ ; NDD-NF-NEXT: TEST8rr [[SETCCr1]], [[SETCCr1]], implicit-def $eflags
+ ; NDD-NF-NEXT: [[CFCMOV64rr1:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
+ ; NDD-NF-NEXT: TEST8rr [[SETCCr2]], [[SETCCr2]], implicit-def $eflags
+ ; NDD-NF-NEXT: [[CFCMOV64rr_ND:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; NDD-NF-NEXT: TEST8rr [[SETCCr2]], [[SETCCr2]], implicit-def $eflags
+ ; NDD-NF-NEXT: [[CFCMOV64rr_ND1:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
+ ; NDD-NF-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr]]
+ ; NDD-NF-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr1]]
+ ; NDD-NF-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND]]
+ ; NDD-NF-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND1]]
+ ; NDD-NF-NEXT: RET 0
+ ;
+ ; NDD-NF-ZU-LABEL: name: test_cfcmov
+ ; NDD-NF-ZU: liveins: $rdi, $rsi
+ ; NDD-NF-ZU-NEXT: {{ $}}
+ ; NDD-NF-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; NDD-NF-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; NDD-NF-ZU-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
+ ; NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; NDD-NF-ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; NDD-NF-ZU-NEXT: [[SETZUCCr2:%[0-9]+]]:gr8 = SETZUCCr 4, implicit $eflags
+ ; NDD-NF-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; NDD-NF-ZU-NEXT: [[CFCMOV64rr:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
+ ; NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr1]], [[SETZUCCr1]], implicit-def $eflags
+ ; NDD-NF-ZU-NEXT: [[CFCMOV64rr1:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
+ ; NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
+ ; NDD-NF-ZU-NEXT: [[CFCMOV64rr_ND:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
+ ; NDD-NF-ZU-NEXT: [[CFCMOV64rr_ND1:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
+ ; NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr]]
+ ; NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr1]]
+ ; NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND]]
+ ; NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND1]]
+ ; NDD-NF-ZU-NEXT: RET 0
%0:gr64 = COPY $rdi
%1:gr64 = COPY $rsi
CMP64rr %0, %1, implicit-def $eflags
@@ -261,6 +470,14 @@ body: |
; NDD-NF-NEXT: [[ADD32rr_NF:%[0-9]+]]:gr32 = ADD32rr_NF $edi, $edi
; NDD-NF-NEXT: CCMP32rr [[ADD32rr_NF]], [[ADD32rr_NF]], 0, 1, implicit-def $eflags, implicit $eflags
; NDD-NF-NEXT: RET 0, $al
+ ;
+ ; NDD-NF-ZU-LABEL: name: test_ccmp
+ ; NDD-NF-ZU: liveins: $edi
+ ; NDD-NF-ZU-NEXT: {{ $}}
+ ; NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; NDD-NF-ZU-NEXT: [[ADD32rr_NF:%[0-9]+]]:gr32 = ADD32rr_NF $edi, $edi
+ ; NDD-NF-ZU-NEXT: CCMP32rr [[ADD32rr_NF]], [[ADD32rr_NF]], 0, 1, implicit-def $eflags, implicit $eflags
+ ; NDD-NF-ZU-NEXT: RET 0, $al
MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
%1:gr64 = COPY $eflags
%2:gr32 = ADD32rr $edi, $edi, implicit-def dead $eflags
@@ -292,6 +509,14 @@ body: |
; NDD-NF-NEXT: [[ADD32rr_NF:%[0-9]+]]:gr32 = ADD32rr_NF $edi, $edi
; NDD-NF-NEXT: CTEST32rr [[ADD32rr_NF]], [[ADD32rr_NF]], 0, 1, implicit-def $eflags, implicit $eflags
; NDD-NF-NEXT: RET 0, $al
+ ;
+ ; NDD-NF-ZU-LABEL: name: test_ctest
+ ; NDD-NF-ZU: liveins: $edi
+ ; NDD-NF-ZU-NEXT: {{ $}}
+ ; NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; NDD-NF-ZU-NEXT: [[ADD32rr_NF:%[0-9]+]]:gr32 = ADD32rr_NF $edi, $edi
+ ; NDD-NF-ZU-NEXT: CTEST32rr [[ADD32rr_NF]], [[ADD32rr_NF]], 0, 1, implicit-def $eflags, implicit $eflags
+ ; NDD-NF-ZU-NEXT: RET 0, $al
MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
%1:gr64 = COPY $eflags
%2:gr32 = ADD32rr $edi, $edi, implicit-def dead $eflags
@@ -323,6 +548,14 @@ body: |
; NDD-NF-NEXT: [[ADD32rr_NF_ND:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $edi
; NDD-NF-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND]], 7, implicit $eflags
; NDD-NF-NEXT: RET 0, $al
+ ;
+ ; NDD-NF-ZU-LABEL: name: test_evitable_clobber
+ ; NDD-NF-ZU: liveins: $edi
+ ; NDD-NF-ZU-NEXT: {{ $}}
+ ; NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; NDD-NF-ZU-NEXT: [[ADD32rr_NF_ND:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $edi
+ ; NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND]], 7, implicit $eflags
+ ; NDD-NF-ZU-NEXT: RET 0, $al
MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
%1:gr64 = COPY $eflags
%2:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
@@ -337,15 +570,35 @@ body: |
bb.0:
liveins: $edi
- ; CHECK-LABEL: name: test_inevitable_clobber
- ; CHECK: liveins: $edi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
- ; CHECK-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
- ; CHECK-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
- ; CHECK-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
- ; CHECK-NEXT: RET 0, $al
+ ; NDD-LABEL: name: test_inevitable_clobber
+ ; NDD: liveins: $edi
+ ; NDD-NEXT: {{ $}}
+ ; NDD-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; NDD-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
+ ; NDD-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
+ ; NDD-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
+ ; NDD-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
+ ; NDD-NEXT: RET 0, $al
+ ;
+ ; NDD-NF-LABEL: name: test_inevitable_clobber
+ ; NDD-NF: liveins: $edi
+ ; NDD-NF-NEXT: {{ $}}
+ ; NDD-NF-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; NDD-NF-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
+ ; NDD-NF-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
+ ; NDD-NF-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
+ ; NDD-NF-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
+ ; NDD-NF-NEXT: RET 0, $al
+ ;
+ ; NDD-NF-ZU-LABEL: name: test_inevitable_clobber
+ ; NDD-NF-ZU: liveins: $edi
+ ; NDD-NF-ZU-NEXT: {{ $}}
+ ; NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; NDD-NF-ZU-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
+ ; NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
+ ; NDD-NF-ZU-NEXT: RET 0, $al
MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
%1:gr64 = COPY $eflags
%2:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
@@ -382,6 +635,16 @@ body: |
; NDD-NF-NEXT: [[ADD32rr_NF_ND1:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $eax
; NDD-NF-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND1]], 9, implicit $eflags
; NDD-NF-NEXT: RET 0, $al
+ ;
+ ; NDD-NF-ZU-LABEL: name: test_evitable_clobber_multiple_uses
+ ; NDD-NF-ZU: liveins: $edi
+ ; NDD-NF-ZU-NEXT: {{ $}}
+ ; NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; NDD-NF-ZU-NEXT: [[ADD32rr_NF_ND:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $edi
+ ; NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND]], 7, implicit $eflags
+ ; NDD-NF-ZU-NEXT: [[ADD32rr_NF_ND1:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $eax
+ ; NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND1]], 9, implicit $eflags
+ ; NDD-NF-ZU-NEXT: RET 0, $al
MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
%1:gr64 = COPY $eflags
%2:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
@@ -426,6 +689,19 @@ body: |
; NDD-NF-NEXT: [[ADD32rr_NF_ND:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $edi
; NDD-NF-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND]], 1, implicit $eflags
; NDD-NF-NEXT: RET 0, $al
+ ;
+ ; NDD-NF-ZU-LABEL: name: test_mixed_clobber
+ ; NDD-NF-ZU: liveins: $edi
+ ; NDD-NF-ZU-NEXT: {{ $}}
+ ; NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; NDD-NF-ZU-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
+ ; NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
+ ; NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; NDD-NF-ZU-NEXT: [[ADD32rr_NF_ND:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $edi
+ ; NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND]], 1, implicit $eflags
+ ; NDD-NF-ZU-NEXT: RET 0, $al
MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
%1:gr64 = COPY $eflags
%2:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
@@ -476,6 +752,23 @@ body: |
; NDD-NF-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND]], 7, implicit $eflags
; NDD-NF-NEXT: $eax = ADC32rr_ND $eax, $edi, implicit-def dead $eflags, implicit $eflags
; NDD-NF-NEXT: RET 0, $al
+ ;
+ ; NDD-NF-ZU-LABEL: name: test_evitable_clobber_crossbb
+ ; NDD-NF-ZU: bb.0:
+ ; NDD-NF-ZU-NEXT: successors: %bb.1(0x80000000)
+ ; NDD-NF-ZU-NEXT: liveins: $edi
+ ; NDD-NF-ZU-NEXT: {{ $}}
+ ; NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; NDD-NF-ZU-NEXT: [[ADD32rr_NF_ND:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $edi
+ ; NDD-NF-ZU-NEXT: JCC_1 %bb.1, 4, implicit $eflags
+ ; NDD-NF-ZU-NEXT: RET 0, $al
+ ; NDD-NF-ZU-NEXT: {{ $}}
+ ; NDD-NF-ZU-NEXT: bb.1:
+ ; NDD-NF-ZU-NEXT: liveins: $eflags
+ ; NDD-NF-ZU-NEXT: {{ $}}
+ ; NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND]], 7, implicit $eflags
+ ; NDD-NF-ZU-NEXT: $eax = ADC32rr_ND $eax, $edi, implicit-def dead $eflags, implicit $eflags
+ ; NDD-NF-ZU-NEXT: RET 0, $al
bb.0:
liveins: $edi
@@ -494,21 +787,53 @@ body: |
---
name: test_inevitable_clobber_crossbb
body: |
- ; CHECK-LABEL: name: test_inevitable_clobber_crossbb
- ; CHECK: bb.0:
- ; CHECK-NEXT: successors: %bb.1(0x80000000)
- ; CHECK-NEXT: liveins: $edi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
- ; CHECK-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
- ; CHECK-NEXT: JCC_1 %bb.1, 4, implicit $eflags
- ; CHECK-NEXT: RET 0, $al
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.1:
- ; CHECK-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
- ; CHECK-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
- ; CHECK-NEXT: RET 0, $al
+ ; NDD-LABEL: name: test_inevitable_clobber_crossbb
+ ; NDD: bb.0:
+ ; NDD-NEXT: successors: %bb.1(0x80000000)
+ ; NDD-NEXT: liveins: $edi
+ ; NDD-NEXT: {{ $}}
+ ; NDD-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; NDD-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
+ ; NDD-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
+ ; NDD-NEXT: JCC_1 %bb.1, 4, implicit $eflags
+ ; NDD-NEXT: RET 0, $al
+ ; NDD-NEXT: {{ $}}
+ ; NDD-NEXT: bb.1:
+ ; NDD-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
+ ; NDD-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
+ ; NDD-NEXT: RET 0, $al
+ ;
+ ; NDD-NF-LABEL: name: test_inevitable_clobber_crossbb
+ ; NDD-NF: bb.0:
+ ; NDD-NF-NEXT: successors: %bb.1(0x80000000)
+ ; NDD-NF-NEXT: liveins: $edi
+ ; NDD-NF-NEXT: {{ $}}
+ ; NDD-NF-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; NDD-NF-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
+ ; NDD-NF-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
+ ; NDD-NF-NEXT: JCC_1 %bb.1, 4, implicit $eflags
+ ; NDD-NF-NEXT: RET 0, $al
+ ; NDD-NF-NEXT: {{ $}}
+ ; NDD-NF-NEXT: bb.1:
+ ; NDD-NF-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
+ ; NDD-NF-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
+ ; NDD-NF-NEXT: RET 0, $al
+ ;
+ ; NDD-NF-ZU-LABEL: name: test_inevitable_clobber_crossbb
+ ; NDD-NF-ZU: bb.0:
+ ; NDD-NF-ZU-NEXT: successors: %bb.1(0x80000000)
+ ; NDD-NF-ZU-NEXT: liveins: $edi
+ ; NDD-NF-ZU-NEXT: {{ $}}
+ ; NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; NDD-NF-ZU-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
+ ; NDD-NF-ZU-NEXT: JCC_1 %bb.1, 4, implicit $eflags
+ ; NDD-NF-ZU-NEXT: RET 0, $al
+ ; NDD-NF-ZU-NEXT: {{ $}}
+ ; NDD-NF-ZU-NEXT: bb.1:
+ ; NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
+ ; NDD-NF-ZU-NEXT: RET 0, $al
bb.0:
liveins: $edi
@@ -581,6 +906,35 @@ body: |
; NDD-NF-NEXT: {{ $}}
; NDD-NF-NEXT: $eax = CMOV32rr_ND $edi, [[SUB32rr_NF_ND]], 7, implicit $eflags
; NDD-NF-NEXT: RET 0, $al
+ ;
+ ; NDD-NF-ZU-LABEL: name: test_evitable_clobber_crossbb_complex
+ ; NDD-NF-ZU: bb.0:
+ ; NDD-NF-ZU-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; NDD-NF-ZU-NEXT: liveins: $edi
+ ; NDD-NF-ZU-NEXT: {{ $}}
+ ; NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; NDD-NF-ZU-NEXT: [[SUB32rr_NF_ND:%[0-9]+]]:gr32 = SUB32rr_NF_ND $edi, $edi
+ ; NDD-NF-ZU-NEXT: JCC_1 %bb.2, 4, implicit $eflags
+ ; NDD-NF-ZU-NEXT: {{ $}}
+ ; NDD-NF-ZU-NEXT: bb.1:
+ ; NDD-NF-ZU-NEXT: successors: %bb.3(0x80000000)
+ ; NDD-NF-ZU-NEXT: liveins: $eflags
+ ; NDD-NF-ZU-NEXT: {{ $}}
+ ; NDD-NF-ZU-NEXT: $eax = IMUL32rr_NF_ND $eax, $edi
+ ; NDD-NF-ZU-NEXT: JMP_1 %bb.3
+ ; NDD-NF-ZU-NEXT: {{ $}}
+ ; NDD-NF-ZU-NEXT: bb.2:
+ ; NDD-NF-ZU-NEXT: successors: %bb.3(0x80000000)
+ ; NDD-NF-ZU-NEXT: liveins: $eflags
+ ; NDD-NF-ZU-NEXT: {{ $}}
+ ; NDD-NF-ZU-NEXT: $eax = IMUL32rr_NF $eax, $esi
+ ; NDD-NF-ZU-NEXT: JMP_1 %bb.3
+ ; NDD-NF-ZU-NEXT: {{ $}}
+ ; NDD-NF-ZU-NEXT: bb.3:
+ ; NDD-NF-ZU-NEXT: liveins: $eflags
+ ; NDD-NF-ZU-NEXT: {{ $}}
+ ; NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[SUB32rr_NF_ND]], 7, implicit $eflags
+ ; NDD-NF-ZU-NEXT: RET 0, $al
bb.0:
liveins: $edi
@@ -605,32 +959,86 @@ body: |
---
name: test_inevitable_clobber_crossbb_complex
body: |
- ; CHECK-LABEL: name: test_inevitable_clobber_crossbb_complex
- ; CHECK: bb.0:
- ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; CHECK-NEXT: liveins: $edi
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
- ; CHECK-NEXT: [[SUB32rr_ND:%[0-9]+]]:gr32 = SUB32rr_ND $edi, $edi, implicit-def dead $eflags
- ; CHECK-NEXT: JCC_1 %bb.2, 4, implicit $eflags
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.1:
- ; CHECK-NEXT: successors: %bb.3(0x80000000)
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $eax = IMUL32rr_ND $eax, $edi, implicit-def dead $eflags
- ; CHECK-NEXT: JMP_1 %bb.3
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.2:
- ; CHECK-NEXT: successors: %bb.3(0x80000000)
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $eax = SBB32rr $eax, $esi, implicit-def dead $eflags, implicit $eflags
- ; CHECK-NEXT: JMP_1 %bb.3
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.3:
- ; CHECK-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
- ; CHECK-NEXT: $eax = CMOV32rr_ND $edi, [[SUB32rr_ND]], 5, implicit killed $eflags
- ; CHECK-NEXT: RET 0, $al
+ ; NDD-LABEL: name: test_inevitable_clobber_crossbb_complex
+ ; NDD: bb.0:
+ ; NDD-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; NDD-NEXT: liveins: $edi
+ ; NDD-NEXT: {{ $}}
+ ; NDD-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; NDD-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
+ ; NDD-NEXT: [[SUB32rr_ND:%[0-9]+]]:gr32 = SUB32rr_ND $edi, $edi, implicit-def dead $eflags
+ ; NDD-NEXT: JCC_1 %bb.2, 4, implicit $eflags
+ ; NDD-NEXT: {{ $}}
+ ; NDD-NEXT: bb.1:
+ ; NDD-NEXT: successors: %bb.3(0x80000000)
+ ; NDD-NEXT: {{ $}}
+ ; NDD-NEXT: $eax = IMUL32rr_ND $eax, $edi, implicit-def dead $eflags
+ ; NDD-NEXT: JMP_1 %bb.3
+ ; NDD-NEXT: {{ $}}
+ ; NDD-NEXT: bb.2:
+ ; NDD-NEXT: successors: %bb.3(0x80000000)
+ ; NDD-NEXT: {{ $}}
+ ; NDD-NEXT: $eax = SBB32rr $eax, $esi, implicit-def dead $eflags, implicit $eflags
+ ; NDD-NEXT: JMP_1 %bb.3
+ ; NDD-NEXT: {{ $}}
+ ; NDD-NEXT: bb.3:
+ ; NDD-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
+ ; NDD-NEXT: $eax = CMOV32rr_ND $edi, [[SUB32rr_ND]], 5, implicit killed $eflags
+ ; NDD-NEXT: RET 0, $al
+ ;
+ ; NDD-NF-LABEL: name: test_inevitable_clobber_crossbb_complex
+ ; NDD-NF: bb.0:
+ ; NDD-NF-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; NDD-NF-NEXT: liveins: $edi
+ ; NDD-NF-NEXT: {{ $}}
+ ; NDD-NF-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; NDD-NF-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
+ ; NDD-NF-NEXT: [[SUB32rr_ND:%[0-9]+]]:gr32 = SUB32rr_ND $edi, $edi, implicit-def dead $eflags
+ ; NDD-NF-NEXT: JCC_1 %bb.2, 4, implicit $eflags
+ ; NDD-NF-NEXT: {{ $}}
+ ; NDD-NF-NEXT: bb.1:
+ ; NDD-NF-NEXT: successors: %bb.3(0x80000000)
+ ; NDD-NF-NEXT: {{ $}}
+ ; NDD-NF-NEXT: $eax = IMUL32rr_ND $eax, $edi, implicit-def dead $eflags
+ ; NDD-NF-NEXT: JMP_1 %bb.3
+ ; NDD-NF-NEXT: {{ $}}
+ ; NDD-NF-NEXT: bb.2:
+ ; NDD-NF-NEXT: successors: %bb.3(0x80000000)
+ ; NDD-NF-NEXT: {{ $}}
+ ; NDD-NF-NEXT: $eax = SBB32rr $eax, $esi, implicit-def dead $eflags, implicit $eflags
+ ; NDD-NF-NEXT: JMP_1 %bb.3
+ ; NDD-NF-NEXT: {{ $}}
+ ; NDD-NF-NEXT: bb.3:
+ ; NDD-NF-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
+ ; NDD-NF-NEXT: $eax = CMOV32rr_ND $edi, [[SUB32rr_ND]], 5, implicit killed $eflags
+ ; NDD-NF-NEXT: RET 0, $al
+ ;
+ ; NDD-NF-ZU-LABEL: name: test_inevitable_clobber_crossbb_complex
+ ; NDD-NF-ZU: bb.0:
+ ; NDD-NF-ZU-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; NDD-NF-ZU-NEXT: liveins: $edi
+ ; NDD-NF-ZU-NEXT: {{ $}}
+ ; NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; NDD-NF-ZU-NEXT: [[SUB32rr_ND:%[0-9]+]]:gr32 = SUB32rr_ND $edi, $edi, implicit-def dead $eflags
+ ; NDD-NF-ZU-NEXT: JCC_1 %bb.2, 4, implicit $eflags
+ ; NDD-NF-ZU-NEXT: {{ $}}
+ ; NDD-NF-ZU-NEXT: bb.1:
+ ; NDD-NF-ZU-NEXT: successors: %bb.3(0x80000000)
+ ; NDD-NF-ZU-NEXT: {{ $}}
+ ; NDD-NF-ZU-NEXT: $eax = IMUL32rr_ND $eax, $edi, implicit-def dead $eflags
+ ; NDD-NF-ZU-NEXT: JMP_1 %bb.3
+ ; NDD-NF-ZU-NEXT: {{ $}}
+ ; NDD-NF-ZU-NEXT: bb.2:
+ ; NDD-NF-ZU-NEXT: successors: %bb.3(0x80000000)
+ ; NDD-NF-ZU-NEXT: {{ $}}
+ ; NDD-NF-ZU-NEXT: $eax = SBB32rr $eax, $esi, implicit-def dead $eflags, implicit $eflags
+ ; NDD-NF-ZU-NEXT: JMP_1 %bb.3
+ ; NDD-NF-ZU-NEXT: {{ $}}
+ ; NDD-NF-ZU-NEXT: bb.3:
+ ; NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[SUB32rr_ND]], 5, implicit killed $eflags
+ ; NDD-NF-ZU-NEXT: RET 0, $al
bb.0:
liveins: $edi
diff --git a/llvm/test/CodeGen/X86/apx/memfold-nd2rmw.mir b/llvm/test/CodeGen/X86/apx/memfold-nd2rmw.mir
index 54e140686876f..4f00076b92a4d 100644
--- a/llvm/test/CodeGen/X86/apx/memfold-nd2rmw.mir
+++ b/llvm/test/CodeGen/X86/apx/memfold-nd2rmw.mir
@@ -4,7 +4,7 @@
# below show be morphed into an ADD32mi by the register allocator, making it
# load-operate-store to %stack.2.
#
-# CHECK: ADD32mi %stack.2
+# CHECK: MOV32mi %stack.2
--- |
define fastcc void @add32ri_nd_2_add32mi(i1 %arg, i1 %arg1, i1 %arg2, ptr %arg3, ptr %arg4, i1 %arg5, i8 %arg6) #0 {
diff --git a/llvm/test/CodeGen/X86/apx/mul-i1024.ll b/llvm/test/CodeGen/X86/apx/mul-i1024.ll
index a29a92176f432..a5feaeb28cfe7 100644
--- a/llvm/test/CodeGen/X86/apx/mul-i1024.ll
+++ b/llvm/test/CodeGen/X86/apx/mul-i1024.ll
@@ -1069,7 +1069,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r23
; EGPR-NDD-NEXT: addq %r27, %rax, %rsi
; EGPR-NDD-NEXT: adcq %rdx, %rcx
-; EGPR-NDD-NEXT: setb %al
+; EGPR-NDD-NEXT: setzub %al
; EGPR-NDD-NEXT: movzbl %al, %r8d
; EGPR-NDD-NEXT: movq %r18, %rax
; EGPR-NDD-NEXT: mulq %r23
@@ -1087,7 +1087,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r23
; EGPR-NDD-NEXT: addq %rax, %rcx
; EGPR-NDD-NEXT: adcq %rdx, %r30
-; EGPR-NDD-NEXT: setb %al
+; EGPR-NDD-NEXT: setzub %al
; EGPR-NDD-NEXT: movzbl %al, %r20d
; EGPR-NDD-NEXT: movq %rdi, %rax
; EGPR-NDD-NEXT: mulq %r23
@@ -1111,7 +1111,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r14
; EGPR-NDD-NEXT: addq %rax, %r19
; EGPR-NDD-NEXT: adcq %rdx, %rsi
-; EGPR-NDD-NEXT: setb %al
+; EGPR-NDD-NEXT: setzub %al
; EGPR-NDD-NEXT: movzbl %al, %r28d
; EGPR-NDD-NEXT: movq %rdi, %rax
; EGPR-NDD-NEXT: mulq %r14
@@ -1123,7 +1123,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: adcq $0, %rdx
; EGPR-NDD-NEXT: addq %rax, %r31
; EGPR-NDD-NEXT: adcq %rdx, %r8
-; EGPR-NDD-NEXT: setb %al
+; EGPR-NDD-NEXT: setzub %al
; EGPR-NDD-NEXT: movzbl %al, %r29d
; EGPR-NDD-NEXT: movq %r25, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; EGPR-NDD-NEXT: movq %r25, %rax
@@ -1139,7 +1139,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r14
; EGPR-NDD-NEXT: addq %rax, %r19
; EGPR-NDD-NEXT: adcq %rdx, %r21
-; EGPR-NDD-NEXT: setb %al
+; EGPR-NDD-NEXT: setzub %al
; EGPR-NDD-NEXT: movzbl %al, %r28d
; EGPR-NDD-NEXT: movq %r18, %rax
; EGPR-NDD-NEXT: mulq %r14
@@ -1161,7 +1161,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r23
; EGPR-NDD-NEXT: addq %rax, %r19
; EGPR-NDD-NEXT: adcq %rdx, %r8
-; EGPR-NDD-NEXT: setb %al
+; EGPR-NDD-NEXT: setzub %al
; EGPR-NDD-NEXT: movzbl %al, %r31d
; EGPR-NDD-NEXT: movq %r9, %rax
; EGPR-NDD-NEXT: mulq %r23
@@ -1180,7 +1180,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: addq %r31, %rax
; EGPR-NDD-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; EGPR-NDD-NEXT: adcq %rdx, %r12
-; EGPR-NDD-NEXT: setb %r31b
+; EGPR-NDD-NEXT: setzub %r31b
; EGPR-NDD-NEXT: movq %r11, %rax
; EGPR-NDD-NEXT: mulq %r23
; EGPR-NDD-NEXT: addq %r12, %rax
@@ -1202,7 +1202,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r14
; EGPR-NDD-NEXT: addq %rax, %r30
; EGPR-NDD-NEXT: adcq %rdx, %r13
-; EGPR-NDD-NEXT: setb %bpl
+; EGPR-NDD-NEXT: setzub %bpl
; EGPR-NDD-NEXT: movq %r11, %rax
; EGPR-NDD-NEXT: mulq %r14
; EGPR-NDD-NEXT: addq %r13, %rax
@@ -1216,7 +1216,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: adcq $0, %rdx
; EGPR-NDD-NEXT: addq %rax, %r8
; EGPR-NDD-NEXT: adcq %rdx, %rbx
-; EGPR-NDD-NEXT: setb %r19b
+; EGPR-NDD-NEXT: setzub %r19b
; EGPR-NDD-NEXT: movq %r10, %r16
; EGPR-NDD-NEXT: movq %r10, %rax
; EGPR-NDD-NEXT: mulq %r26
@@ -1230,7 +1230,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r14
; EGPR-NDD-NEXT: addq %rax, %r30
; EGPR-NDD-NEXT: adcq %rdx, %r12
-; EGPR-NDD-NEXT: setb %bpl
+; EGPR-NDD-NEXT: setzub %bpl
; EGPR-NDD-NEXT: movq %r9, %rax
; EGPR-NDD-NEXT: mulq %r14
; EGPR-NDD-NEXT: addq %r12, %rax
@@ -1266,7 +1266,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r18
; EGPR-NDD-NEXT: addq %r27, %rax, %r21
; EGPR-NDD-NEXT: adcq %rdx, %rcx
-; EGPR-NDD-NEXT: setb %r8b
+; EGPR-NDD-NEXT: setzub %r8b
; EGPR-NDD-NEXT: movq %r9, %rax
; EGPR-NDD-NEXT: mulq %r18
; EGPR-NDD-NEXT: addq %rcx, %rax, %rdi
@@ -1285,7 +1285,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r18
; EGPR-NDD-NEXT: addq %r8, %rax, %r25
; EGPR-NDD-NEXT: adcq %rdx, %r20
-; EGPR-NDD-NEXT: setb %cl
+; EGPR-NDD-NEXT: setzub %cl
; EGPR-NDD-NEXT: movq %r11, %rax
; EGPR-NDD-NEXT: mulq %r18
; EGPR-NDD-NEXT: addq %r20, %rax
@@ -1312,7 +1312,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r17
; EGPR-NDD-NEXT: addq %rax, %r20
; EGPR-NDD-NEXT: adcq %rdx, %rcx
-; EGPR-NDD-NEXT: setb %sil
+; EGPR-NDD-NEXT: setzub %sil
; EGPR-NDD-NEXT: movq %r10, %rax
; EGPR-NDD-NEXT: mulq %r17
; EGPR-NDD-NEXT: addq %rcx, %rax
@@ -1324,7 +1324,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: adcq $0, %rcx
; EGPR-NDD-NEXT: addq %rax, %rdi
; EGPR-NDD-NEXT: adcq %rcx, %r9, %r8
-; EGPR-NDD-NEXT: setb %sil
+; EGPR-NDD-NEXT: setzub %sil
; EGPR-NDD-NEXT: movq %r16, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; EGPR-NDD-NEXT: movq %r16, %rax
; EGPR-NDD-NEXT: mulq %r11
@@ -1339,7 +1339,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r17
; EGPR-NDD-NEXT: addq %rax, %r20
; EGPR-NDD-NEXT: adcq %rdx, %r9
-; EGPR-NDD-NEXT: setb %cl
+; EGPR-NDD-NEXT: setzub %cl
; EGPR-NDD-NEXT: movq %r19, %rax
; EGPR-NDD-NEXT: mulq %r17
; EGPR-NDD-NEXT: addq %r9, %rax
@@ -1366,7 +1366,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: adcq %r8, %r28
; EGPR-NDD-NEXT: adcq %rax, %r29
; EGPR-NDD-NEXT: adcq %rcx, {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Folded Reload
-; EGPR-NDD-NEXT: setb %r8b
+; EGPR-NDD-NEXT: setzub %r8b
; EGPR-NDD-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r13 # 8-byte Reload
; EGPR-NDD-NEXT: movq %r13, %rax
; EGPR-NDD-NEXT: mulq %r30
@@ -1381,7 +1381,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r18
; EGPR-NDD-NEXT: addq %r27, %rax, %rdi
; EGPR-NDD-NEXT: adcq %rdx, %rsi
-; EGPR-NDD-NEXT: setb %r9b
+; EGPR-NDD-NEXT: setzub %r9b
; EGPR-NDD-NEXT: movq %r10, %rax
; EGPR-NDD-NEXT: movq %r10, %r16
; EGPR-NDD-NEXT: mulq %r18
@@ -1402,7 +1402,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r18
; EGPR-NDD-NEXT: addq %r21, %rax, %rbx
; EGPR-NDD-NEXT: adcq %rdx, %r10
-; EGPR-NDD-NEXT: setb %r31b
+; EGPR-NDD-NEXT: setzub %r31b
; EGPR-NDD-NEXT: movq %r12, %rax
; EGPR-NDD-NEXT: mulq %r18
; EGPR-NDD-NEXT: addq %r10, %rax
@@ -1424,7 +1424,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r17
; EGPR-NDD-NEXT: addq %rax, %r20
; EGPR-NDD-NEXT: adcq %rdx, %r31
-; EGPR-NDD-NEXT: setb %bpl
+; EGPR-NDD-NEXT: setzub %bpl
; EGPR-NDD-NEXT: movq %r12, %rax
; EGPR-NDD-NEXT: mulq %r17
; EGPR-NDD-NEXT: addq %r31, %rax
@@ -1436,7 +1436,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: adcq $0, %rdx
; EGPR-NDD-NEXT: addq %rax, %rsi
; EGPR-NDD-NEXT: adcq %rdx, %r9
-; EGPR-NDD-NEXT: setb %r31b
+; EGPR-NDD-NEXT: setzub %r31b
; EGPR-NDD-NEXT: movq %r13, %rax
; EGPR-NDD-NEXT: mulq %r11
; EGPR-NDD-NEXT: movq %rdx, %r20
@@ -1449,7 +1449,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r17
; EGPR-NDD-NEXT: addq %rax, %r20
; EGPR-NDD-NEXT: adcq %rdx, %r12
-; EGPR-NDD-NEXT: setb %bpl
+; EGPR-NDD-NEXT: setzub %bpl
; EGPR-NDD-NEXT: movq %r16, %rax
; EGPR-NDD-NEXT: mulq %r17
; EGPR-NDD-NEXT: addq %r12, %rax
@@ -1491,7 +1491,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r21
; EGPR-NDD-NEXT: addq %rax, %r27
; EGPR-NDD-NEXT: adcq %rdx, %rcx
-; EGPR-NDD-NEXT: setb %sil
+; EGPR-NDD-NEXT: setzub %sil
; EGPR-NDD-NEXT: movq %r14, %rax
; EGPR-NDD-NEXT: mulq %r21
; EGPR-NDD-NEXT: addq %rax, %rcx
@@ -1510,7 +1510,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: addq %r29, %rax
; EGPR-NDD-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; EGPR-NDD-NEXT: adcq %rdx, %rdi
-; EGPR-NDD-NEXT: setb %r8b
+; EGPR-NDD-NEXT: setzub %r8b
; EGPR-NDD-NEXT: movq %r23, %rax
; EGPR-NDD-NEXT: mulq %r21
; EGPR-NDD-NEXT: addq %rdi, %rax
@@ -1534,7 +1534,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %rbx
; EGPR-NDD-NEXT: addq %rax, %r28
; EGPR-NDD-NEXT: adcq %rdx, %r9
-; EGPR-NDD-NEXT: setb %r10b
+; EGPR-NDD-NEXT: setzub %r10b
; EGPR-NDD-NEXT: movq %r23, %rax
; EGPR-NDD-NEXT: mulq %rbx
; EGPR-NDD-NEXT: addq %r9, %rax
@@ -1547,7 +1547,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: adcq $0, %rdx
; EGPR-NDD-NEXT: addq %rax, %rcx
; EGPR-NDD-NEXT: adcq %rdx, %rsi
-; EGPR-NDD-NEXT: setb %dil
+; EGPR-NDD-NEXT: setzub %dil
; EGPR-NDD-NEXT: movq %r26, %rax
; EGPR-NDD-NEXT: mulq %r8
; EGPR-NDD-NEXT: movq %rdx, %r28
@@ -1560,7 +1560,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %rbx
; EGPR-NDD-NEXT: addq %rax, %r28
; EGPR-NDD-NEXT: adcq %rdx, %r9
-; EGPR-NDD-NEXT: setb %r10b
+; EGPR-NDD-NEXT: setzub %r10b
; EGPR-NDD-NEXT: movq %r14, %rax
; EGPR-NDD-NEXT: mulq %rbx
; EGPR-NDD-NEXT: addq %r9, %rax
@@ -1598,7 +1598,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r18
; EGPR-NDD-NEXT: addq %rax, %rcx
; EGPR-NDD-NEXT: adcq %rdx, %rdi
-; EGPR-NDD-NEXT: setb %r9b
+; EGPR-NDD-NEXT: setzub %r9b
; EGPR-NDD-NEXT: movq %r21, %rax
; EGPR-NDD-NEXT: mulq %r18
; EGPR-NDD-NEXT: addq %rdi, %rax
@@ -1636,7 +1636,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r23
; EGPR-NDD-NEXT: addq %rax, %r25
; EGPR-NDD-NEXT: adcq %rdx, %r10
-; EGPR-NDD-NEXT: setb %r11b
+; EGPR-NDD-NEXT: setzub %r11b
; EGPR-NDD-NEXT: movq %rdi, %rax
; EGPR-NDD-NEXT: mulq %r23
; EGPR-NDD-NEXT: addq %r10, %rax
@@ -1668,7 +1668,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r23
; EGPR-NDD-NEXT: addq %rax, %rdi
; EGPR-NDD-NEXT: adcq %rdx, %rcx
-; EGPR-NDD-NEXT: setb %sil
+; EGPR-NDD-NEXT: setzub %sil
; EGPR-NDD-NEXT: movq %r22, %rax
; EGPR-NDD-NEXT: mulq %r23
; EGPR-NDD-NEXT: addq %rax, %rcx
@@ -1688,7 +1688,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r23
; EGPR-NDD-NEXT: addq %r31, %rax, %r29
; EGPR-NDD-NEXT: adcq %rdx, %r8
-; EGPR-NDD-NEXT: setb %r9b
+; EGPR-NDD-NEXT: setzub %r9b
; EGPR-NDD-NEXT: movq %r25, %rax
; EGPR-NDD-NEXT: mulq %r23
; EGPR-NDD-NEXT: addq %r8, %rax
@@ -1712,7 +1712,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r11
; EGPR-NDD-NEXT: addq %r30, %rax, %r27
; EGPR-NDD-NEXT: adcq %rdx, %r8
-; EGPR-NDD-NEXT: setb %r9b
+; EGPR-NDD-NEXT: setzub %r9b
; EGPR-NDD-NEXT: movq %r25, %rax
; EGPR-NDD-NEXT: mulq %r11
; EGPR-NDD-NEXT: addq %r8, %rax
@@ -1724,7 +1724,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: adcq $0, %rdx
; EGPR-NDD-NEXT: addq %rax, %rcx
; EGPR-NDD-NEXT: adcq %rdx, %rsi
-; EGPR-NDD-NEXT: setb %dil
+; EGPR-NDD-NEXT: setzub %dil
; EGPR-NDD-NEXT: movq %r24, %rax
; EGPR-NDD-NEXT: mulq %r10
; EGPR-NDD-NEXT: movq %rdx, %r30
@@ -1737,7 +1737,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r11
; EGPR-NDD-NEXT: addq %r30, %rax, %r19
; EGPR-NDD-NEXT: adcq %rdx, %r8
-; EGPR-NDD-NEXT: setb %r9b
+; EGPR-NDD-NEXT: setzub %r9b
; EGPR-NDD-NEXT: movq %r22, %rax
; EGPR-NDD-NEXT: mulq %r11
; EGPR-NDD-NEXT: addq %r8, %rax
@@ -1778,7 +1778,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r8
; EGPR-NDD-NEXT: addq %rax, %r11
; EGPR-NDD-NEXT: adcq %rdx, %r16
-; EGPR-NDD-NEXT: setb %r17b
+; EGPR-NDD-NEXT: setzub %r17b
; EGPR-NDD-NEXT: movq %r23, %rax
; EGPR-NDD-NEXT: mulq %r8
; EGPR-NDD-NEXT: addq %r16, %rax
@@ -1817,7 +1817,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r25
; EGPR-NDD-NEXT: addq %rax, %r8
; EGPR-NDD-NEXT: adcq %rdx, %r22
-; EGPR-NDD-NEXT: setb %r23b
+; EGPR-NDD-NEXT: setzub %r23b
; EGPR-NDD-NEXT: movq %r24, %rax
; EGPR-NDD-NEXT: mulq %r25
; EGPR-NDD-NEXT: addq %r22, %rax
diff --git a/llvm/test/CodeGen/X86/apx/neg.ll b/llvm/test/CodeGen/X86/apx/neg.ll
index 8f8a391487b5a..c1cebf08e0651 100644
--- a/llvm/test/CodeGen/X86/apx/neg.ll
+++ b/llvm/test/CodeGen/X86/apx/neg.ll
@@ -1,18 +1,18 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd,nf -verify-machineinstrs | FileCheck --check-prefix=NF %s
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd -verify-machineinstrs --show-mc-encoding | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd,nf -verify-machineinstrs --show-mc-encoding | FileCheck --check-prefix=NF %s
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd,nf -x86-enable-apx-for-relocation=true -verify-machineinstrs --show-mc-encoding | FileCheck --check-prefix=NF %s
define i8 @neg8r(i8 noundef %a) {
; CHECK-LABEL: neg8r:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: negb %dil, %al
-; CHECK-NEXT: retq
+; CHECK-NEXT: negb %dil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xf6,0xdf]
+; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: neg8r:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} negb %dil, %al
-; NF-NEXT: retq
+; NF-NEXT: {nf} negb %dil, %al # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0xf6,0xdf]
+; NF-NEXT: retq # encoding: [0xc3]
entry:
%neg = sub i8 0, %a
ret i8 %neg
@@ -21,13 +21,13 @@ entry:
define i16 @neg16r(i16 noundef %a) {
; CHECK-LABEL: neg16r:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: negw %di, %ax
-; CHECK-NEXT: retq
+; CHECK-NEXT: negw %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0xf7,0xdf]
+; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: neg16r:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} negw %di, %ax
-; NF-NEXT: retq
+; NF-NEXT: {nf} negw %di, %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0xf7,0xdf]
+; NF-NEXT: retq # encoding: [0xc3]
entry:
%neg = sub i16 0, %a
ret i16 %neg
@@ -36,13 +36,13 @@ entry:
define i32 @neg32r(i32 noundef %a) {
; CHECK-LABEL: neg32r:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: negl %edi, %eax
-; CHECK-NEXT: retq
+; CHECK-NEXT: negl %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0xf7,0xdf]
+; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: neg32r:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} negl %edi, %eax
-; NF-NEXT: retq
+; NF-NEXT: {nf} negl %edi, %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0xf7,0xdf]
+; NF-NEXT: retq # encoding: [0xc3]
entry:
%neg = sub i32 0, %a
ret i32 %neg
@@ -51,13 +51,13 @@ entry:
define i64 @neg64r(i64 noundef %a) {
; CHECK-LABEL: neg64r:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: negq %rdi, %rax
-; CHECK-NEXT: retq
+; CHECK-NEXT: negq %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xf7,0xdf]
+; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: neg64r:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} negq %rdi, %rax
-; NF-NEXT: retq
+; NF-NEXT: {nf} negq %rdi, %rax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0xfc,0x1c,0xf7,0xdf]
+; NF-NEXT: retq # encoding: [0xc3]
entry:
%neg = sub i64 0, %a
ret i64 %neg
@@ -66,13 +66,13 @@ entry:
define i8 @neg8m(ptr %ptr) {
; CHECK-LABEL: neg8m:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: negb (%rdi), %al
-; CHECK-NEXT: retq
+; CHECK-NEXT: negb (%rdi), %al # encoding: [0x62,0xf4,0x7c,0x18,0xf6,0x1f]
+; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: neg8m:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} negb (%rdi), %al
-; NF-NEXT: retq
+; NF-NEXT: {nf} negb (%rdi), %al # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0xf6,0x1f]
+; NF-NEXT: retq # encoding: [0xc3]
entry:
%a = load i8, ptr %ptr
%neg = sub i8 0, %a
@@ -82,13 +82,13 @@ entry:
define i16 @neg16m(ptr %ptr) {
; CHECK-LABEL: neg16m:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: negw (%rdi), %ax
-; CHECK-NEXT: retq
+; CHECK-NEXT: negw (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0xf7,0x1f]
+; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: neg16m:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} negw (%rdi), %ax
-; NF-NEXT: retq
+; NF-NEXT: {nf} negw (%rdi), %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0xf7,0x1f]
+; NF-NEXT: retq # encoding: [0xc3]
entry:
%a = load i16, ptr %ptr
%neg = sub i16 0, %a
@@ -98,13 +98,13 @@ entry:
define i32 @neg32m(ptr %ptr) {
; CHECK-LABEL: neg32m:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: negl (%rdi), %eax
-; CHECK-NEXT: retq
+; CHECK-NEXT: negl (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0xf7,0x1f]
+; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: neg32m:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} negl (%rdi), %eax
-; NF-NEXT: retq
+; NF-NEXT: {nf} negl (%rdi), %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0xf7,0x1f]
+; NF-NEXT: retq # encoding: [0xc3]
entry:
%a = load i32, ptr %ptr
%neg = sub i32 0, %a
@@ -114,13 +114,13 @@ entry:
define i64 @neg64m(ptr %ptr) {
; CHECK-LABEL: neg64m:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: negq (%rdi), %rax
-; CHECK-NEXT: retq
+; CHECK-NEXT: negq (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0xf7,0x1f]
+; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: neg64m:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} negq (%rdi), %rax
-; NF-NEXT: retq
+; NF-NEXT: {nf} negq (%rdi), %rax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0xfc,0x1c,0xf7,0x1f]
+; NF-NEXT: retq # encoding: [0xc3]
entry:
%a = load i64, ptr %ptr
%neg = sub i64 0, %a
@@ -130,13 +130,13 @@ entry:
define i8 @uneg8r(i8 noundef %a) {
; CHECK-LABEL: uneg8r:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: negb %dil, %al
-; CHECK-NEXT: retq
+; CHECK-NEXT: negb %dil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xf6,0xdf]
+; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: uneg8r:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} negb %dil, %al
-; NF-NEXT: retq
+; NF-NEXT: {nf} negb %dil, %al # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0xf6,0xdf]
+; NF-NEXT: retq # encoding: [0xc3]
entry:
%t = call {i8, i1} @llvm.usub.with.overflow.i8(i8 0, i8 %a)
%neg = extractvalue {i8, i1} %t, 0
@@ -146,13 +146,13 @@ entry:
define i16 @uneg16r(i16 noundef %a) {
; CHECK-LABEL: uneg16r:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: negw %di, %ax
-; CHECK-NEXT: retq
+; CHECK-NEXT: negw %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0xf7,0xdf]
+; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: uneg16r:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} negw %di, %ax
-; NF-NEXT: retq
+; NF-NEXT: {nf} negw %di, %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0xf7,0xdf]
+; NF-NEXT: retq # encoding: [0xc3]
entry:
%t = call {i16, i1} @llvm.usub.with.overflow.i16(i16 0, i16 %a)
%neg = extractvalue {i16, i1} %t, 0
@@ -162,13 +162,13 @@ entry:
define i32 @uneg32r(i32 noundef %a) {
; CHECK-LABEL: uneg32r:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: negl %edi, %eax
-; CHECK-NEXT: retq
+; CHECK-NEXT: negl %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0xf7,0xdf]
+; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: uneg32r:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} negl %edi, %eax
-; NF-NEXT: retq
+; NF-NEXT: {nf} negl %edi, %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0xf7,0xdf]
+; NF-NEXT: retq # encoding: [0xc3]
entry:
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 0, i32 %a)
%neg = extractvalue {i32, i1} %t, 0
@@ -178,13 +178,13 @@ entry:
define i64 @uneg64r(i64 noundef %a) {
; CHECK-LABEL: uneg64r:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: negq %rdi, %rax
-; CHECK-NEXT: retq
+; CHECK-NEXT: negq %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xf7,0xdf]
+; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: uneg64r:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} negq %rdi, %rax
-; NF-NEXT: retq
+; NF-NEXT: {nf} negq %rdi, %rax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0xfc,0x1c,0xf7,0xdf]
+; NF-NEXT: retq # encoding: [0xc3]
entry:
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 0, i64 %a)
%neg = extractvalue {i64, i1} %t, 0
@@ -194,13 +194,13 @@ entry:
define i8 @uneg8m(ptr %ptr) {
; CHECK-LABEL: uneg8m:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: negb (%rdi), %al
-; CHECK-NEXT: retq
+; CHECK-NEXT: negb (%rdi), %al # encoding: [0x62,0xf4,0x7c,0x18,0xf6,0x1f]
+; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: uneg8m:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} negb (%rdi), %al
-; NF-NEXT: retq
+; NF-NEXT: {nf} negb (%rdi), %al # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0xf6,0x1f]
+; NF-NEXT: retq # encoding: [0xc3]
entry:
%a = load i8, ptr %ptr
%t = call {i8, i1} @llvm.usub.with.overflow.i8(i8 0, i8 %a)
@@ -211,13 +211,13 @@ entry:
define i16 @uneg16m(ptr %ptr) {
; CHECK-LABEL: uneg16m:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: negw (%rdi), %ax
-; CHECK-NEXT: retq
+; CHECK-NEXT: negw (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0xf7,0x1f]
+; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: uneg16m:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} negw (%rdi), %ax
-; NF-NEXT: retq
+; NF-NEXT: {nf} negw (%rdi), %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0xf7,0x1f]
+; NF-NEXT: retq # encoding: [0xc3]
entry:
%a = load i16, ptr %ptr
%t = call {i16, i1} @llvm.usub.with.overflow.i16(i16 0, i16 %a)
@@ -228,13 +228,13 @@ entry:
define i32 @uneg32m(ptr %ptr) {
; CHECK-LABEL: uneg32m:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: negl (%rdi), %eax
-; CHECK-NEXT: retq
+; CHECK-NEXT: negl (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0xf7,0x1f]
+; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: uneg32m:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} negl (%rdi), %eax
-; NF-NEXT: retq
+; NF-NEXT: {nf} negl (%rdi), %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0xf7,0x1f]
+; NF-NEXT: retq # encoding: [0xc3]
entry:
%a = load i32, ptr %ptr
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 0, i32 %a)
@@ -245,13 +245,13 @@ entry:
define i64 @uneg64m(ptr %ptr) {
; CHECK-LABEL: uneg64m:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: negq (%rdi), %rax
-; CHECK-NEXT: retq
+; CHECK-NEXT: negq (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0xf7,0x1f]
+; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: uneg64m:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} negq (%rdi), %rax
-; NF-NEXT: retq
+; NF-NEXT: {nf} negq (%rdi), %rax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0xfc,0x1c,0xf7,0x1f]
+; NF-NEXT: retq # encoding: [0xc3]
entry:
%a = load i64, ptr %ptr
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 0, i64 %a)
@@ -267,13 +267,13 @@ declare {i64, i1} @llvm.usub.with.overflow.i64(i64, i64)
define void @neg8m_legacy(ptr %ptr) {
; CHECK-LABEL: neg8m_legacy:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: negb (%rdi)
-; CHECK-NEXT: retq
+; CHECK-NEXT: negb (%rdi) # encoding: [0xf6,0x1f]
+; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: neg8m_legacy:
; NF: # %bb.0: # %entry
-; NF-NEXT: negb (%rdi)
-; NF-NEXT: retq
+; NF-NEXT: negb (%rdi) # encoding: [0xf6,0x1f]
+; NF-NEXT: retq # encoding: [0xc3]
entry:
%a = load i8, ptr %ptr
%neg = sub i8 0, %a
@@ -284,13 +284,13 @@ entry:
define void @neg16m_legacy(ptr %ptr) {
; CHECK-LABEL: neg16m_legacy:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: negw (%rdi)
-; CHECK-NEXT: retq
+; CHECK-NEXT: negw (%rdi) # encoding: [0x66,0xf7,0x1f]
+; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: neg16m_legacy:
; NF: # %bb.0: # %entry
-; NF-NEXT: negw (%rdi)
-; NF-NEXT: retq
+; NF-NEXT: negw (%rdi) # encoding: [0x66,0xf7,0x1f]
+; NF-NEXT: retq # encoding: [0xc3]
entry:
%a = load i16, ptr %ptr
%neg = sub i16 0, %a
@@ -301,13 +301,13 @@ entry:
define void @neg32m_legacy(ptr %ptr) {
; CHECK-LABEL: neg32m_legacy:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: negl (%rdi)
-; CHECK-NEXT: retq
+; CHECK-NEXT: negl (%rdi) # encoding: [0xf7,0x1f]
+; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: neg32m_legacy:
; NF: # %bb.0: # %entry
-; NF-NEXT: negl (%rdi)
-; NF-NEXT: retq
+; NF-NEXT: negl (%rdi) # encoding: [0xf7,0x1f]
+; NF-NEXT: retq # encoding: [0xc3]
entry:
%a = load i32, ptr %ptr
%neg = sub i32 0, %a
@@ -318,13 +318,13 @@ entry:
define void @neg64m_legacy(ptr %ptr) {
; CHECK-LABEL: neg64m_legacy:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: negq (%rdi)
-; CHECK-NEXT: retq
+; CHECK-NEXT: negq (%rdi) # encoding: [0x48,0xf7,0x1f]
+; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: neg64m_legacy:
; NF: # %bb.0: # %entry
-; NF-NEXT: negq (%rdi)
-; NF-NEXT: retq
+; NF-NEXT: negq (%rdi) # encoding: [0x48,0xf7,0x1f]
+; NF-NEXT: retq # encoding: [0xc3]
entry:
%a = load i64, ptr %ptr
%neg = sub i64 0, %a
diff --git a/llvm/test/CodeGen/X86/apx/or.ll b/llvm/test/CodeGen/X86/apx/or.ll
index 12ee5fc3404db..a2242eadeff69 100644
--- a/llvm/test/CodeGen/X86/apx/or.ll
+++ b/llvm/test/CodeGen/X86/apx/or.ll
@@ -431,7 +431,7 @@ define i1 @orflag8rr(i8 %a, i8 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: notb %sil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xf6,0xd6]
; CHECK-NEXT: orb %al, %dil, %cl # encoding: [0x62,0xf4,0x74,0x18,0x08,0xc7]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -440,7 +440,7 @@ define i1 @orflag8rr(i8 %a, i8 %b) {
; NF: # %bb.0:
; NF-NEXT: notb %sil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xf6,0xd6]
; NF-NEXT: orb %al, %dil, %cl # encoding: [0x62,0xf4,0x74,0x18,0x08,0xc7]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -456,7 +456,7 @@ define i1 @orflag16rr(i16 %a, i16 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: notw %si, %ax # encoding: [0x62,0xf4,0x7d,0x18,0xf7,0xd6]
; CHECK-NEXT: orw %ax, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x09,0xc7]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -465,7 +465,7 @@ define i1 @orflag16rr(i16 %a, i16 %b) {
; NF: # %bb.0:
; NF-NEXT: notw %si, %ax # encoding: [0x62,0xf4,0x7d,0x18,0xf7,0xd6]
; NF-NEXT: orw %ax, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x09,0xc7]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -480,7 +480,7 @@ define i1 @orflag32rr(i32 %a, i32 %b) {
; CHECK-LABEL: orflag32rr:
; CHECK: # %bb.0:
; CHECK-NEXT: orl %edi, %esi # EVEX TO LEGACY Compression encoding: [0x09,0xfe]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movl %esi, d64(%rip) # encoding: [0x89,0x35,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -488,7 +488,7 @@ define i1 @orflag32rr(i32 %a, i32 %b) {
; NF-LABEL: orflag32rr:
; NF: # %bb.0:
; NF-NEXT: orl %edi, %esi # EVEX TO LEGACY Compression encoding: [0x09,0xfe]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movl %esi, d64(%rip) # encoding: [0x89,0x35,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -502,7 +502,7 @@ define i1 @orflag64rr(i64 %a, i64 %b) {
; CHECK-LABEL: orflag64rr:
; CHECK: # %bb.0:
; CHECK-NEXT: orq %rdi, %rsi # EVEX TO LEGACY Compression encoding: [0x48,0x09,0xfe]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movq %rsi, d64(%rip) # encoding: [0x48,0x89,0x35,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -510,7 +510,7 @@ define i1 @orflag64rr(i64 %a, i64 %b) {
; NF-LABEL: orflag64rr:
; NF: # %bb.0:
; NF-NEXT: orq %rdi, %rsi # EVEX TO LEGACY Compression encoding: [0x48,0x09,0xfe]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movq %rsi, d64(%rip) # encoding: [0x48,0x89,0x35,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -525,7 +525,7 @@ define i1 @orflag8rm(ptr %ptr, i8 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: notb %sil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xf6,0xd6]
; CHECK-NEXT: orb (%rdi), %al, %cl # encoding: [0x62,0xf4,0x74,0x18,0x0a,0x07]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -534,7 +534,7 @@ define i1 @orflag8rm(ptr %ptr, i8 %b) {
; NF: # %bb.0:
; NF-NEXT: notb %sil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xf6,0xd6]
; NF-NEXT: orb (%rdi), %al, %cl # encoding: [0x62,0xf4,0x74,0x18,0x0a,0x07]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -551,7 +551,7 @@ define i1 @orflag16rm(ptr %ptr, i16 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: notw %si, %ax # encoding: [0x62,0xf4,0x7d,0x18,0xf7,0xd6]
; CHECK-NEXT: orw (%rdi), %ax, %cx # encoding: [0x62,0xf4,0x75,0x18,0x0b,0x07]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -560,7 +560,7 @@ define i1 @orflag16rm(ptr %ptr, i16 %b) {
; NF: # %bb.0:
; NF-NEXT: notw %si, %ax # encoding: [0x62,0xf4,0x7d,0x18,0xf7,0xd6]
; NF-NEXT: orw (%rdi), %ax, %cx # encoding: [0x62,0xf4,0x75,0x18,0x0b,0x07]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -576,7 +576,7 @@ define i1 @orflag32rm(ptr %ptr, i32 %b) {
; CHECK-LABEL: orflag32rm:
; CHECK: # %bb.0:
; CHECK-NEXT: orl (%rdi), %esi # EVEX TO LEGACY Compression encoding: [0x0b,0x37]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movl %esi, d64(%rip) # encoding: [0x89,0x35,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -584,7 +584,7 @@ define i1 @orflag32rm(ptr %ptr, i32 %b) {
; NF-LABEL: orflag32rm:
; NF: # %bb.0:
; NF-NEXT: orl (%rdi), %esi # EVEX TO LEGACY Compression encoding: [0x0b,0x37]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movl %esi, d64(%rip) # encoding: [0x89,0x35,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -599,7 +599,7 @@ define i1 @orflag64rm(ptr %ptr, i64 %b) {
; CHECK-LABEL: orflag64rm:
; CHECK: # %bb.0:
; CHECK-NEXT: orq (%rdi), %rsi # EVEX TO LEGACY Compression encoding: [0x48,0x0b,0x37]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movq %rsi, d64(%rip) # encoding: [0x48,0x89,0x35,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -607,7 +607,7 @@ define i1 @orflag64rm(ptr %ptr, i64 %b) {
; NF-LABEL: orflag64rm:
; NF: # %bb.0:
; NF-NEXT: orq (%rdi), %rsi # EVEX TO LEGACY Compression encoding: [0x48,0x0b,0x37]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movq %rsi, d64(%rip) # encoding: [0x48,0x89,0x35,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -622,7 +622,7 @@ define i1 @orflag8ri(i8 %a) {
; CHECK-LABEL: orflag8ri:
; CHECK: # %bb.0:
; CHECK-NEXT: orb $-124, %dil, %cl # encoding: [0x62,0xf4,0x74,0x18,0x80,0xcf,0x84]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -630,7 +630,7 @@ define i1 @orflag8ri(i8 %a) {
; NF-LABEL: orflag8ri:
; NF: # %bb.0:
; NF-NEXT: orb $-124, %dil, %cl # encoding: [0x62,0xf4,0x74,0x18,0x80,0xcf,0x84]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -646,7 +646,7 @@ define i1 @orflag16ri(i16 %a) {
; CHECK: # %bb.0:
; CHECK-NEXT: orw $-1235, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x81,0xcf,0x2d,0xfb]
; CHECK-NEXT: # imm = 0xFB2D
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -655,7 +655,7 @@ define i1 @orflag16ri(i16 %a) {
; NF: # %bb.0:
; NF-NEXT: orw $-1235, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x81,0xcf,0x2d,0xfb]
; NF-NEXT: # imm = 0xFB2D
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -671,7 +671,7 @@ define i1 @orflag32ri(i32 %a) {
; CHECK: # %bb.0:
; CHECK-NEXT: orl $123456, %edi # EVEX TO LEGACY Compression encoding: [0x81,0xcf,0x40,0xe2,0x01,0x00]
; CHECK-NEXT: # imm = 0x1E240
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movl %edi, d64(%rip) # encoding: [0x89,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -680,7 +680,7 @@ define i1 @orflag32ri(i32 %a) {
; NF: # %bb.0:
; NF-NEXT: orl $123456, %edi # EVEX TO LEGACY Compression encoding: [0x81,0xcf,0x40,0xe2,0x01,0x00]
; NF-NEXT: # imm = 0x1E240
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movl %edi, d64(%rip) # encoding: [0x89,0x3d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -695,7 +695,7 @@ define i1 @orflag64ri(i64 %a) {
; CHECK: # %bb.0:
; CHECK-NEXT: orq $123456, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x81,0xcf,0x40,0xe2,0x01,0x00]
; CHECK-NEXT: # imm = 0x1E240
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -704,7 +704,7 @@ define i1 @orflag64ri(i64 %a) {
; NF: # %bb.0:
; NF-NEXT: orq $123456, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x81,0xcf,0x40,0xe2,0x01,0x00]
; NF-NEXT: # imm = 0x1E240
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -718,7 +718,7 @@ define i1 @orflag16ri8(i16 %a) {
; CHECK-LABEL: orflag16ri8:
; CHECK: # %bb.0:
; CHECK-NEXT: orw $-124, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x83,0xcf,0x84]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -726,7 +726,7 @@ define i1 @orflag16ri8(i16 %a) {
; NF-LABEL: orflag16ri8:
; NF: # %bb.0:
; NF-NEXT: orw $-124, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x83,0xcf,0x84]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -741,7 +741,7 @@ define i1 @orflag32ri8(i32 %a) {
; CHECK-LABEL: orflag32ri8:
; CHECK: # %bb.0:
; CHECK-NEXT: orl $123, %edi # EVEX TO LEGACY Compression encoding: [0x83,0xcf,0x7b]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movl %edi, d64(%rip) # encoding: [0x89,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -749,7 +749,7 @@ define i1 @orflag32ri8(i32 %a) {
; NF-LABEL: orflag32ri8:
; NF: # %bb.0:
; NF-NEXT: orl $123, %edi # EVEX TO LEGACY Compression encoding: [0x83,0xcf,0x7b]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movl %edi, d64(%rip) # encoding: [0x89,0x3d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -763,7 +763,7 @@ define i1 @orflag64ri8(i64 %a) {
; CHECK-LABEL: orflag64ri8:
; CHECK: # %bb.0:
; CHECK-NEXT: orq $123, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x83,0xcf,0x7b]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -771,7 +771,7 @@ define i1 @orflag64ri8(i64 %a) {
; NF-LABEL: orflag64ri8:
; NF: # %bb.0:
; NF-NEXT: orq $123, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x83,0xcf,0x7b]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
diff --git a/llvm/test/CodeGen/X86/apx/setzucc.ll b/llvm/test/CodeGen/X86/apx/setzucc.ll
index 6eb2d6966ecd8..7b5576c961fa1 100644
--- a/llvm/test/CodeGen/X86/apx/setzucc.ll
+++ b/llvm/test/CodeGen/X86/apx/setzucc.ll
@@ -51,20 +51,18 @@ define i32 @flags_copy_lowering() nounwind {
; CHECK-LABEL: flags_copy_lowering:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB4_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: addl %edx, 0
-; CHECK-NEXT: setb %sil
-; CHECK-NEXT: adcl $0, %ecx
-; CHECK-NEXT: testb %sil, %sil
+; CHECK-NEXT: addl %ecx, 0
+; CHECK-NEXT: setzub %cl
+; CHECK-NEXT: adcl $0, %edx
+; CHECK-NEXT: testb %cl, %cl
; CHECK-NEXT: je .LBB4_3
; CHECK-NEXT: # %bb.2: # %bb1
; CHECK-NEXT: # in Loop: Header=BB4_1 Depth=1
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: movb %sil, %dl
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB4_1
; CHECK-NEXT: .LBB4_3: # %bb2
diff --git a/llvm/test/CodeGen/X86/apx/xor.ll b/llvm/test/CodeGen/X86/apx/xor.ll
index e083c6580398c..cf85d18318da4 100644
--- a/llvm/test/CodeGen/X86/apx/xor.ll
+++ b/llvm/test/CodeGen/X86/apx/xor.ll
@@ -431,7 +431,7 @@ define i1 @xorflag8rr(i8 %a, i8 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %edi, %esi # EVEX TO LEGACY Compression encoding: [0x31,0xfe]
; CHECK-NEXT: xorb $-1, %sil, %cl # encoding: [0x62,0xf4,0x74,0x18,0x80,0xf6,0xff]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -440,7 +440,7 @@ define i1 @xorflag8rr(i8 %a, i8 %b) {
; NF: # %bb.0:
; NF-NEXT: xorl %edi, %esi # EVEX TO LEGACY Compression encoding: [0x31,0xfe]
; NF-NEXT: xorb $-1, %sil, %cl # encoding: [0x62,0xf4,0x74,0x18,0x80,0xf6,0xff]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -456,7 +456,7 @@ define i1 @xorflag16rr(i16 %a, i16 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %edi, %esi # EVEX TO LEGACY Compression encoding: [0x31,0xfe]
; CHECK-NEXT: xorw $-1, %si, %cx # encoding: [0x62,0xf4,0x75,0x18,0x83,0xf6,0xff]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -465,7 +465,7 @@ define i1 @xorflag16rr(i16 %a, i16 %b) {
; NF: # %bb.0:
; NF-NEXT: xorl %edi, %esi # EVEX TO LEGACY Compression encoding: [0x31,0xfe]
; NF-NEXT: xorw $-1, %si, %cx # encoding: [0x62,0xf4,0x75,0x18,0x83,0xf6,0xff]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -480,7 +480,7 @@ define i1 @xorflag32rr(i32 %a, i32 %b) {
; CHECK-LABEL: xorflag32rr:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %edi, %esi # EVEX TO LEGACY Compression encoding: [0x31,0xfe]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movl %esi, d64(%rip) # encoding: [0x89,0x35,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -488,7 +488,7 @@ define i1 @xorflag32rr(i32 %a, i32 %b) {
; NF-LABEL: xorflag32rr:
; NF: # %bb.0:
; NF-NEXT: xorl %edi, %esi # EVEX TO LEGACY Compression encoding: [0x31,0xfe]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movl %esi, d64(%rip) # encoding: [0x89,0x35,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -502,7 +502,7 @@ define i1 @xorflag64rr(i64 %a, i64 %b) {
; CHECK-LABEL: xorflag64rr:
; CHECK: # %bb.0:
; CHECK-NEXT: xorq %rdi, %rsi # EVEX TO LEGACY Compression encoding: [0x48,0x31,0xfe]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movq %rsi, d64(%rip) # encoding: [0x48,0x89,0x35,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -510,7 +510,7 @@ define i1 @xorflag64rr(i64 %a, i64 %b) {
; NF-LABEL: xorflag64rr:
; NF: # %bb.0:
; NF-NEXT: xorq %rdi, %rsi # EVEX TO LEGACY Compression encoding: [0x48,0x31,0xfe]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movq %rsi, d64(%rip) # encoding: [0x48,0x89,0x35,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -525,7 +525,7 @@ define i1 @xorflag8rm(ptr %ptr, i8 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: xorb (%rdi), %sil, %al # encoding: [0x62,0xf4,0x7c,0x18,0x32,0x37]
; CHECK-NEXT: xorb $-1, %al, %cl # encoding: [0x62,0xf4,0x74,0x18,0x80,0xf0,0xff]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -534,7 +534,7 @@ define i1 @xorflag8rm(ptr %ptr, i8 %b) {
; NF: # %bb.0:
; NF-NEXT: {nf} xorb (%rdi), %sil, %al # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x32,0x37]
; NF-NEXT: xorb $-1, %al, %cl # encoding: [0x62,0xf4,0x74,0x18,0x80,0xf0,0xff]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -551,7 +551,7 @@ define i1 @xorflag16rm(ptr %ptr, i16 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: xorw (%rdi), %si, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x33,0x37]
; CHECK-NEXT: xorw $-1, %ax, %cx # encoding: [0x62,0xf4,0x75,0x18,0x83,0xf0,0xff]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -560,7 +560,7 @@ define i1 @xorflag16rm(ptr %ptr, i16 %b) {
; NF: # %bb.0:
; NF-NEXT: {nf} xorw (%rdi), %si, %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0x33,0x37]
; NF-NEXT: xorw $-1, %ax, %cx # encoding: [0x62,0xf4,0x75,0x18,0x83,0xf0,0xff]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -576,7 +576,7 @@ define i1 @xorflag32rm(ptr %ptr, i32 %b) {
; CHECK-LABEL: xorflag32rm:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl (%rdi), %esi # EVEX TO LEGACY Compression encoding: [0x33,0x37]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movl %esi, d64(%rip) # encoding: [0x89,0x35,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -584,7 +584,7 @@ define i1 @xorflag32rm(ptr %ptr, i32 %b) {
; NF-LABEL: xorflag32rm:
; NF: # %bb.0:
; NF-NEXT: xorl (%rdi), %esi # EVEX TO LEGACY Compression encoding: [0x33,0x37]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movl %esi, d64(%rip) # encoding: [0x89,0x35,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -599,7 +599,7 @@ define i1 @xorflag64rm(ptr %ptr, i64 %b) {
; CHECK-LABEL: xorflag64rm:
; CHECK: # %bb.0:
; CHECK-NEXT: xorq (%rdi), %rsi # EVEX TO LEGACY Compression encoding: [0x48,0x33,0x37]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movq %rsi, d64(%rip) # encoding: [0x48,0x89,0x35,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -607,7 +607,7 @@ define i1 @xorflag64rm(ptr %ptr, i64 %b) {
; NF-LABEL: xorflag64rm:
; NF: # %bb.0:
; NF-NEXT: xorq (%rdi), %rsi # EVEX TO LEGACY Compression encoding: [0x48,0x33,0x37]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movq %rsi, d64(%rip) # encoding: [0x48,0x89,0x35,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -622,7 +622,7 @@ define i1 @xorflag8ri(i8 %a) {
; CHECK-LABEL: xorflag8ri:
; CHECK: # %bb.0:
; CHECK-NEXT: xorb $-124, %dil, %cl # encoding: [0x62,0xf4,0x74,0x18,0x80,0xf7,0x84]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -630,7 +630,7 @@ define i1 @xorflag8ri(i8 %a) {
; NF-LABEL: xorflag8ri:
; NF: # %bb.0:
; NF-NEXT: xorb $-124, %dil, %cl # encoding: [0x62,0xf4,0x74,0x18,0x80,0xf7,0x84]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -646,7 +646,7 @@ define i1 @xorflag16ri(i16 %a) {
; CHECK: # %bb.0:
; CHECK-NEXT: xorw $-1235, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x81,0xf7,0x2d,0xfb]
; CHECK-NEXT: # imm = 0xFB2D
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -655,7 +655,7 @@ define i1 @xorflag16ri(i16 %a) {
; NF: # %bb.0:
; NF-NEXT: xorw $-1235, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x81,0xf7,0x2d,0xfb]
; NF-NEXT: # imm = 0xFB2D
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -671,7 +671,7 @@ define i1 @xorflag32ri(i32 %a) {
; CHECK: # %bb.0:
; CHECK-NEXT: xorl $123456, %edi # EVEX TO LEGACY Compression encoding: [0x81,0xf7,0x40,0xe2,0x01,0x00]
; CHECK-NEXT: # imm = 0x1E240
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movl %edi, d64(%rip) # encoding: [0x89,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -680,7 +680,7 @@ define i1 @xorflag32ri(i32 %a) {
; NF: # %bb.0:
; NF-NEXT: xorl $123456, %edi # EVEX TO LEGACY Compression encoding: [0x81,0xf7,0x40,0xe2,0x01,0x00]
; NF-NEXT: # imm = 0x1E240
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movl %edi, d64(%rip) # encoding: [0x89,0x3d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -695,7 +695,7 @@ define i1 @xorflag64ri(i64 %a) {
; CHECK: # %bb.0:
; CHECK-NEXT: xorq $123456, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x81,0xf7,0x40,0xe2,0x01,0x00]
; CHECK-NEXT: # imm = 0x1E240
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -704,7 +704,7 @@ define i1 @xorflag64ri(i64 %a) {
; NF: # %bb.0:
; NF-NEXT: xorq $123456, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x81,0xf7,0x40,0xe2,0x01,0x00]
; NF-NEXT: # imm = 0x1E240
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -718,7 +718,7 @@ define i1 @xorflag16ri8(i16 %a) {
; CHECK-LABEL: xorflag16ri8:
; CHECK: # %bb.0:
; CHECK-NEXT: xorw $-124, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x83,0xf7,0x84]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -726,7 +726,7 @@ define i1 @xorflag16ri8(i16 %a) {
; NF-LABEL: xorflag16ri8:
; NF: # %bb.0:
; NF-NEXT: xorw $-124, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x83,0xf7,0x84]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -741,7 +741,7 @@ define i1 @xorflag32ri8(i32 %a) {
; CHECK-LABEL: xorflag32ri8:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl $123, %edi # EVEX TO LEGACY Compression encoding: [0x83,0xf7,0x7b]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movl %edi, d64(%rip) # encoding: [0x89,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -749,7 +749,7 @@ define i1 @xorflag32ri8(i32 %a) {
; NF-LABEL: xorflag32ri8:
; NF: # %bb.0:
; NF-NEXT: xorl $123, %edi # EVEX TO LEGACY Compression encoding: [0x83,0xf7,0x7b]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movl %edi, d64(%rip) # encoding: [0x89,0x3d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -763,7 +763,7 @@ define i1 @xorflag64ri8(i64 %a) {
; CHECK-LABEL: xorflag64ri8:
; CHECK: # %bb.0:
; CHECK-NEXT: xorq $123, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x83,0xf7,0x7b]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; CHECK-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -771,7 +771,7 @@ define i1 @xorflag64ri8(i64 %a) {
; NF-LABEL: xorflag64ri8:
; NF: # %bb.0:
; NF-NEXT: xorq $123, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x83,0xf7,0x7b]
-; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NF-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
diff --git a/llvm/test/CodeGen/X86/cmp.ll b/llvm/test/CodeGen/X86/cmp.ll
index 0965b1c7208f6..887c59c7a4198 100644
--- a/llvm/test/CodeGen/X86/cmp.ll
+++ b/llvm/test/CodeGen/X86/cmp.ll
@@ -1,6 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,NO-NDD
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ndd -show-mc-encoding | FileCheck --check-prefixes=CHECK,NDD %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ndd,+zu -show-mc-encoding | FileCheck --check-prefixes=CHECK,NDD-ZU %s
@d = dso_local global i8 0, align 1
@d64 = dso_local global i64 0
@@ -81,12 +82,25 @@ ReturnBlock:
}
define i64 @test3(i64 %x) nounwind {
-; CHECK-LABEL: test3:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; CHECK-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
-; CHECK-NEXT: retq # encoding: [0xc3]
+; NO-NDD-LABEL: test3:
+; NO-NDD: # %bb.0: # %entry
+; NO-NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; NO-NDD-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff]
+; NO-NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NO-NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-LABEL: test3:
+; NDD: # %bb.0: # %entry
+; NDD-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff]
+; NDD-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: test3:
+; NDD-ZU: # %bb.0: # %entry
+; NDD-ZU-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff]
+; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
entry:
%t = icmp eq i64 %x, 0
%r = zext i1 %t to i64
@@ -94,12 +108,25 @@ entry:
}
define i64 @test4(i64 %x) nounwind {
-; CHECK-LABEL: test4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; CHECK-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff]
-; CHECK-NEXT: setle %al # encoding: [0x0f,0x9e,0xc0]
-; CHECK-NEXT: retq # encoding: [0xc3]
+; NO-NDD-LABEL: test4:
+; NO-NDD: # %bb.0:
+; NO-NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; NO-NDD-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff]
+; NO-NDD-NEXT: setle %al # encoding: [0x0f,0x9e,0xc0]
+; NO-NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-LABEL: test4:
+; NDD: # %bb.0:
+; NDD-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff]
+; NDD-NEXT: setzule %al # encoding: [0x62,0xf4,0x7f,0x18,0x4e,0xc0]
+; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: test4:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff]
+; NDD-ZU-NEXT: setzule %al # encoding: [0x62,0xf4,0x7f,0x18,0x4e,0xc0]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%t = icmp slt i64 %x, 1
%r = zext i1 %t to i64
ret i64 %r
@@ -177,10 +204,16 @@ define i32 @test7(i64 %res) nounwind {
;
; NDD-LABEL: test7:
; NDD: # %bb.0: # %entry
-; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: shrq $32, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x20]
-; NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NDD-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: test7:
+; NDD-ZU: # %bb.0: # %entry
+; NDD-ZU-NEXT: shrq $32, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x20]
+; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
entry:
%lnot = icmp ult i64 %res, 4294967296
%lnot.ext = zext i1 %lnot to i32
@@ -199,10 +232,17 @@ define i32 @test8(i64 %res) nounwind {
; NDD-LABEL: test8:
; NDD: # %bb.0:
; NDD-NEXT: shrq $32, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x20]
-; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: cmpl $3, %edi # encoding: [0x83,0xff,0x03]
-; NDD-NEXT: setb %al # encoding: [0x0f,0x92,0xc0]
+; NDD-NEXT: setzub %al # encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc0]
+; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: test8:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: shrq $32, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x20]
+; NDD-ZU-NEXT: cmpl $3, %edi # encoding: [0x83,0xff,0x03]
+; NDD-ZU-NEXT: setzub %al # encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc0]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%lnot = icmp ult i64 %res, 12884901888
%lnot.ext = zext i1 %lnot to i32
ret i32 %lnot.ext
@@ -218,10 +258,16 @@ define i32 @test9(i64 %res) nounwind {
;
; NDD-LABEL: test9:
; NDD: # %bb.0:
-; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: shrq $33, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x21]
-; NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NDD-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: test9:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: shrq $33, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x21]
+; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%lnot = icmp ult i64 %res, 8589934592
%lnot.ext = zext i1 %lnot to i32
ret i32 %lnot.ext
@@ -237,10 +283,16 @@ define i32 @test10(i64 %res) nounwind {
;
; NDD-LABEL: test10:
; NDD: # %bb.0:
-; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: shrq $32, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x20]
-; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
+; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: test10:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: shrq $32, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x20]
+; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%lnot = icmp uge i64 %res, 4294967296
%lnot.ext = zext i1 %lnot to i32
ret i32 %lnot.ext
@@ -258,10 +310,17 @@ define i32 @test11(i64 %l) nounwind {
; NDD-LABEL: test11:
; NDD: # %bb.0:
; NDD-NEXT: shrq $47, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x2f]
-; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: cmpl $1, %edi # encoding: [0x83,0xff,0x01]
-; NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NDD-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: test11:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: shrq $47, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x2f]
+; NDD-ZU-NEXT: cmpl $1, %edi # encoding: [0x83,0xff,0x01]
+; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%shr.mask = and i64 %l, -140737488355328
%cmp = icmp eq i64 %shr.mask, 140737488355328
%conv = zext i1 %cmp to i32
@@ -315,6 +374,12 @@ define i32 @test13(i32 %mask, i32 %base, i32 %intra) {
; NDD-NEXT: testb $8, %dil # encoding: [0x40,0xf6,0xc7,0x08]
; NDD-NEXT: cmovnel %edx, %esi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x45,0xf2]
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: test13:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: testb $8, %dil # encoding: [0x40,0xf6,0xc7,0x08]
+; NDD-ZU-NEXT: cmovnel %edx, %esi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x45,0xf2]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%and = and i32 %mask, 8
%tobool = icmp ne i32 %and, 0
%cond = select i1 %tobool, i32 %intra, i32 %base
@@ -334,6 +399,12 @@ define i32 @test14(i32 %mask, i32 %base, i32 %intra) {
; NDD-NEXT: shrl $7, %edi # EVEX TO LEGACY Compression encoding: [0xc1,0xef,0x07]
; NDD-NEXT: cmovnsl %edx, %esi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x49,0xf2]
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: test14:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: shrl $7, %edi # EVEX TO LEGACY Compression encoding: [0xc1,0xef,0x07]
+; NDD-ZU-NEXT: cmovnsl %edx, %esi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x49,0xf2]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%s = lshr i32 %mask, 7
%tobool = icmp sgt i32 %s, -1
%cond = select i1 %tobool, i32 %intra, i32 %base
@@ -354,11 +425,20 @@ define zeroext i1 @test15(i32 %bf.load, i32 %n) {
; NDD-LABEL: test15:
; NDD: # %bb.0:
; NDD-NEXT: shrl $16, %edi # EVEX TO LEGACY Compression encoding: [0xc1,0xef,0x10]
-; NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NDD-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NDD-NEXT: cmpl %esi, %edi # encoding: [0x39,0xf7]
-; NDD-NEXT: setae %cl # encoding: [0x0f,0x93,0xc1]
+; NDD-NEXT: setzuae %cl # encoding: [0x62,0xf4,0x7f,0x18,0x43,0xc1]
; NDD-NEXT: orb %cl, %al # EVEX TO LEGACY Compression encoding: [0x08,0xc8]
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: test15:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: shrl $16, %edi # EVEX TO LEGACY Compression encoding: [0xc1,0xef,0x10]
+; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NDD-ZU-NEXT: cmpl %esi, %edi # encoding: [0x39,0xf7]
+; NDD-ZU-NEXT: setzuae %cl # encoding: [0x62,0xf4,0x7f,0x18,0x43,0xc1]
+; NDD-ZU-NEXT: orb %cl, %al # EVEX TO LEGACY Compression encoding: [0x08,0xc8]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%bf.lshr = lshr i32 %bf.load, 16
%cmp2 = icmp eq i32 %bf.lshr, 0
%cmp5 = icmp uge i32 %bf.lshr, %n
@@ -367,11 +447,23 @@ define zeroext i1 @test15(i32 %bf.load, i32 %n) {
}
define i8 @signbit_i16(i16 signext %L) {
-; CHECK-LABEL: signbit_i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: testw %di, %di # encoding: [0x66,0x85,0xff]
-; CHECK-NEXT: setns %al # encoding: [0x0f,0x99,0xc0]
-; CHECK-NEXT: retq # encoding: [0xc3]
+; NO-NDD-LABEL: signbit_i16:
+; NO-NDD: # %bb.0:
+; NO-NDD-NEXT: testw %di, %di # encoding: [0x66,0x85,0xff]
+; NO-NDD-NEXT: setns %al # encoding: [0x0f,0x99,0xc0]
+; NO-NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-LABEL: signbit_i16:
+; NDD: # %bb.0:
+; NDD-NEXT: testw %di, %di # encoding: [0x66,0x85,0xff]
+; NDD-NEXT: setzuns %al # encoding: [0x62,0xf4,0x7f,0x18,0x49,0xc0]
+; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: signbit_i16:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: testw %di, %di # encoding: [0x66,0x85,0xff]
+; NDD-ZU-NEXT: setzuns %al # encoding: [0x62,0xf4,0x7f,0x18,0x49,0xc0]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%lshr = lshr i16 %L, 15
%trunc = trunc i16 %lshr to i8
%not = xor i8 %trunc, 1
@@ -379,11 +471,23 @@ define i8 @signbit_i16(i16 signext %L) {
}
define i8 @signbit_i32(i32 %L) {
-; CHECK-LABEL: signbit_i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: testl %edi, %edi # encoding: [0x85,0xff]
-; CHECK-NEXT: setns %al # encoding: [0x0f,0x99,0xc0]
-; CHECK-NEXT: retq # encoding: [0xc3]
+; NO-NDD-LABEL: signbit_i32:
+; NO-NDD: # %bb.0:
+; NO-NDD-NEXT: testl %edi, %edi # encoding: [0x85,0xff]
+; NO-NDD-NEXT: setns %al # encoding: [0x0f,0x99,0xc0]
+; NO-NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-LABEL: signbit_i32:
+; NDD: # %bb.0:
+; NDD-NEXT: testl %edi, %edi # encoding: [0x85,0xff]
+; NDD-NEXT: setzuns %al # encoding: [0x62,0xf4,0x7f,0x18,0x49,0xc0]
+; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: signbit_i32:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: testl %edi, %edi # encoding: [0x85,0xff]
+; NDD-ZU-NEXT: setzuns %al # encoding: [0x62,0xf4,0x7f,0x18,0x49,0xc0]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%lshr = lshr i32 %L, 31
%trunc = trunc i32 %lshr to i8
%not = xor i8 %trunc, 1
@@ -391,11 +495,23 @@ define i8 @signbit_i32(i32 %L) {
}
define i8 @signbit_i64(i64 %L) {
-; CHECK-LABEL: signbit_i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff]
-; CHECK-NEXT: setns %al # encoding: [0x0f,0x99,0xc0]
-; CHECK-NEXT: retq # encoding: [0xc3]
+; NO-NDD-LABEL: signbit_i64:
+; NO-NDD: # %bb.0:
+; NO-NDD-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff]
+; NO-NDD-NEXT: setns %al # encoding: [0x0f,0x99,0xc0]
+; NO-NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-LABEL: signbit_i64:
+; NDD: # %bb.0:
+; NDD-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff]
+; NDD-NEXT: setzuns %al # encoding: [0x62,0xf4,0x7f,0x18,0x49,0xc0]
+; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: signbit_i64:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff]
+; NDD-ZU-NEXT: setzuns %al # encoding: [0x62,0xf4,0x7f,0x18,0x49,0xc0]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%lshr = lshr i64 %L, 63
%trunc = trunc i64 %lshr to i8
%not = xor i8 %trunc, 1
@@ -403,11 +519,23 @@ define i8 @signbit_i64(i64 %L) {
}
define zeroext i1 @signbit_i32_i1(i32 %L) {
-; CHECK-LABEL: signbit_i32_i1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: testl %edi, %edi # encoding: [0x85,0xff]
-; CHECK-NEXT: setns %al # encoding: [0x0f,0x99,0xc0]
-; CHECK-NEXT: retq # encoding: [0xc3]
+; NO-NDD-LABEL: signbit_i32_i1:
+; NO-NDD: # %bb.0:
+; NO-NDD-NEXT: testl %edi, %edi # encoding: [0x85,0xff]
+; NO-NDD-NEXT: setns %al # encoding: [0x0f,0x99,0xc0]
+; NO-NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-LABEL: signbit_i32_i1:
+; NDD: # %bb.0:
+; NDD-NEXT: testl %edi, %edi # encoding: [0x85,0xff]
+; NDD-NEXT: setzuns %al # encoding: [0x62,0xf4,0x7f,0x18,0x49,0xc0]
+; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: signbit_i32_i1:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: testl %edi, %edi # encoding: [0x85,0xff]
+; NDD-ZU-NEXT: setzuns %al # encoding: [0x62,0xf4,0x7f,0x18,0x49,0xc0]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%lshr = lshr i32 %L, 31
%trunc = trunc i32 %lshr to i1
%not = xor i1 %trunc, true
@@ -433,10 +561,10 @@ define void @test20(i32 %bf.load, i8 %x1, ptr %b_addr) {
;
; NDD-LABEL: test20:
; NDD: # %bb.0:
-; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: testl $16777215, %edi # encoding: [0xf7,0xc7,0xff,0xff,0xff,0x00]
; NDD-NEXT: # imm = 0xFFFFFF
-; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
+; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
; NDD-NEXT: movzbl %sil, %ecx # encoding: [0x40,0x0f,0xb6,0xce]
; NDD-NEXT: addl %ecx, %eax # EVEX TO LEGACY Compression encoding: [0x01,0xc8]
; NDD-NEXT: setne (%rdx) # encoding: [0x0f,0x95,0x02]
@@ -445,6 +573,20 @@ define void @test20(i32 %bf.load, i8 %x1, ptr %b_addr) {
; NDD-NEXT: setne d(%rip) # encoding: [0x0f,0x95,0x05,A,A,A,A]
; NDD-NEXT: # fixup A - offset: 3, value: d-4, kind: reloc_riprel_4byte
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: test20:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: testl $16777215, %edi # encoding: [0xf7,0xc7,0xff,0xff,0xff,0x00]
+; NDD-ZU-NEXT: # imm = 0xFFFFFF
+; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-ZU-NEXT: movzbl %sil, %ecx # encoding: [0x40,0x0f,0xb6,0xce]
+; NDD-ZU-NEXT: addl %ecx, %eax # EVEX TO LEGACY Compression encoding: [0x01,0xc8]
+; NDD-ZU-NEXT: setne (%rdx) # encoding: [0x0f,0x95,0x02]
+; NDD-ZU-NEXT: testl $16777215, %edi # encoding: [0xf7,0xc7,0xff,0xff,0xff,0x00]
+; NDD-ZU-NEXT: # imm = 0xFFFFFF
+; NDD-ZU-NEXT: setne d(%rip) # encoding: [0x0f,0x95,0x05,A,A,A,A]
+; NDD-ZU-NEXT: # fixup A - offset: 3, value: d-4, kind: reloc_riprel_4byte
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%bf.shl = shl i32 %bf.load, 8
%bf.ashr = ashr exact i32 %bf.shl, 8
%tobool4 = icmp ne i32 %bf.ashr, 0
@@ -481,10 +623,16 @@ define i32 @highmask_i64_mask64(i64 %val) {
;
; NDD-LABEL: highmask_i64_mask64:
; NDD: # %bb.0:
-; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: shrq $41, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x29]
-; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
+; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: highmask_i64_mask64:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: shrq $41, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x29]
+; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%and = and i64 %val, -2199023255552
%cmp = icmp ne i64 %and, 0
%ret = zext i1 %cmp to i32
@@ -503,11 +651,18 @@ define i64 @highmask_i64_mask64_extra_use(i64 %val) nounwind {
;
; NDD-LABEL: highmask_i64_mask64_extra_use:
; NDD: # %bb.0:
-; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; NDD-NEXT: shrq $41, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0xc1,0xef,0x29]
-; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
+; NDD-NEXT: shrq $41, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xc1,0xef,0x29]
+; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
; NDD-NEXT: imulq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0xaf,0xc7]
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: highmask_i64_mask64_extra_use:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: shrq $41, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xc1,0xef,0x29]
+; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-ZU-NEXT: imulq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0xaf,0xc7]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%and = and i64 %val, -2199023255552
%cmp = icmp ne i64 %and, 0
%z = zext i1 %cmp to i64
@@ -525,10 +680,16 @@ define i32 @highmask_i64_mask32(i64 %val) {
;
; NDD-LABEL: highmask_i64_mask32:
; NDD: # %bb.0:
-; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: shrq $20, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x14]
-; NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NDD-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: highmask_i64_mask32:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: shrq $20, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x14]
+; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%and = and i64 %val, -1048576
%cmp = icmp eq i64 %and, 0
%ret = zext i1 %cmp to i32
@@ -547,12 +708,20 @@ define i64 @highmask_i64_mask32_extra_use(i64 %val) nounwind {
;
; NDD-LABEL: highmask_i64_mask32_extra_use:
; NDD: # %bb.0:
-; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: testq $-1048576, %rdi # encoding: [0x48,0xf7,0xc7,0x00,0x00,0xf0,0xff]
; NDD-NEXT: # imm = 0xFFF00000
-; NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NDD-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
; NDD-NEXT: imulq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0xaf,0xc7]
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: highmask_i64_mask32_extra_use:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: testq $-1048576, %rdi # encoding: [0x48,0xf7,0xc7,0x00,0x00,0xf0,0xff]
+; NDD-ZU-NEXT: # imm = 0xFFF00000
+; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NDD-ZU-NEXT: imulq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0xaf,0xc7]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%and = and i64 %val, -1048576
%cmp = icmp eq i64 %and, 0
%z = zext i1 %cmp to i64
@@ -561,12 +730,25 @@ define i64 @highmask_i64_mask32_extra_use(i64 %val) nounwind {
}
define i32 @highmask_i64_mask8(i64 %val) {
-; CHECK-LABEL: highmask_i64_mask8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; CHECK-NEXT: testq $-16, %rdi # encoding: [0x48,0xf7,0xc7,0xf0,0xff,0xff,0xff]
-; CHECK-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
-; CHECK-NEXT: retq # encoding: [0xc3]
+; NO-NDD-LABEL: highmask_i64_mask8:
+; NO-NDD: # %bb.0:
+; NO-NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; NO-NDD-NEXT: testq $-16, %rdi # encoding: [0x48,0xf7,0xc7,0xf0,0xff,0xff,0xff]
+; NO-NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
+; NO-NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-LABEL: highmask_i64_mask8:
+; NDD: # %bb.0:
+; NDD-NEXT: testq $-16, %rdi # encoding: [0x48,0xf7,0xc7,0xf0,0xff,0xff,0xff]
+; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: highmask_i64_mask8:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: testq $-16, %rdi # encoding: [0x48,0xf7,0xc7,0xf0,0xff,0xff,0xff]
+; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%and = and i64 %val, -16
%cmp = icmp ne i64 %and, 0
%ret = zext i1 %cmp to i32
@@ -583,10 +765,16 @@ define i32 @lowmask_i64_mask64(i64 %val) {
;
; NDD-LABEL: lowmask_i64_mask64:
; NDD: # %bb.0:
-; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: shlq $16, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xe7,0x10]
-; NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NDD-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: lowmask_i64_mask64:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: shlq $16, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xe7,0x10]
+; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%and = and i64 %val, 281474976710655
%cmp = icmp eq i64 %and, 0
%ret = zext i1 %cmp to i32
@@ -605,11 +793,18 @@ define i64 @lowmask_i64_mask64_extra_use(i64 %val) nounwind {
;
; NDD-LABEL: lowmask_i64_mask64_extra_use:
; NDD: # %bb.0:
-; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; NDD-NEXT: shlq $16, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0xc1,0xe7,0x10]
-; NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NDD-NEXT: shlq $16, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xc1,0xe7,0x10]
+; NDD-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
; NDD-NEXT: imulq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0xaf,0xc7]
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: lowmask_i64_mask64_extra_use:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: shlq $16, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xc1,0xe7,0x10]
+; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NDD-ZU-NEXT: imulq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0xaf,0xc7]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%and = and i64 %val, 281474976710655
%cmp = icmp eq i64 %and, 0
%z = zext i1 %cmp to i64
@@ -627,10 +822,16 @@ define i32 @lowmask_i64_mask32(i64 %val) {
;
; NDD-LABEL: lowmask_i64_mask32:
; NDD: # %bb.0:
-; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: shlq $44, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xe7,0x2c]
-; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
+; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: lowmask_i64_mask32:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: shlq $44, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xe7,0x2c]
+; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%and = and i64 %val, 1048575
%cmp = icmp ne i64 %and, 0
%ret = zext i1 %cmp to i32
@@ -649,12 +850,20 @@ define i64 @lowmask_i64_mask32_extra_use(i64 %val) nounwind {
;
; NDD-LABEL: lowmask_i64_mask32_extra_use:
; NDD: # %bb.0:
-; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: testl $1048575, %edi # encoding: [0xf7,0xc7,0xff,0xff,0x0f,0x00]
; NDD-NEXT: # imm = 0xFFFFF
-; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
+; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
; NDD-NEXT: imulq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0xaf,0xc7]
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: lowmask_i64_mask32_extra_use:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: testl $1048575, %edi # encoding: [0xf7,0xc7,0xff,0xff,0x0f,0x00]
+; NDD-ZU-NEXT: # imm = 0xFFFFF
+; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-ZU-NEXT: imulq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0xaf,0xc7]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%and = and i64 %val, 1048575
%cmp = icmp ne i64 %and, 0
%z = zext i1 %cmp to i64
@@ -663,12 +872,25 @@ define i64 @lowmask_i64_mask32_extra_use(i64 %val) nounwind {
}
define i32 @lowmask_i64_mask8(i64 %val) {
-; CHECK-LABEL: lowmask_i64_mask8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; CHECK-NEXT: testb $31, %dil # encoding: [0x40,0xf6,0xc7,0x1f]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
-; CHECK-NEXT: retq # encoding: [0xc3]
+; NO-NDD-LABEL: lowmask_i64_mask8:
+; NO-NDD: # %bb.0:
+; NO-NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; NO-NDD-NEXT: testb $31, %dil # encoding: [0x40,0xf6,0xc7,0x1f]
+; NO-NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NO-NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-LABEL: lowmask_i64_mask8:
+; NDD: # %bb.0:
+; NDD-NEXT: testb $31, %dil # encoding: [0x40,0xf6,0xc7,0x1f]
+; NDD-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: lowmask_i64_mask8:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: testb $31, %dil # encoding: [0x40,0xf6,0xc7,0x1f]
+; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%and = and i64 %val, 31
%cmp = icmp eq i64 %and, 0
%ret = zext i1 %cmp to i32
@@ -676,13 +898,28 @@ define i32 @lowmask_i64_mask8(i64 %val) {
}
define i32 @highmask_i32_mask32(i32 %val) {
-; CHECK-LABEL: highmask_i32_mask32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; CHECK-NEXT: testl $-1048576, %edi # encoding: [0xf7,0xc7,0x00,0x00,0xf0,0xff]
-; CHECK-NEXT: # imm = 0xFFF00000
-; CHECK-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
-; CHECK-NEXT: retq # encoding: [0xc3]
+; NO-NDD-LABEL: highmask_i32_mask32:
+; NO-NDD: # %bb.0:
+; NO-NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; NO-NDD-NEXT: testl $-1048576, %edi # encoding: [0xf7,0xc7,0x00,0x00,0xf0,0xff]
+; NO-NDD-NEXT: # imm = 0xFFF00000
+; NO-NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
+; NO-NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-LABEL: highmask_i32_mask32:
+; NDD: # %bb.0:
+; NDD-NEXT: testl $-1048576, %edi # encoding: [0xf7,0xc7,0x00,0x00,0xf0,0xff]
+; NDD-NEXT: # imm = 0xFFF00000
+; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: highmask_i32_mask32:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: testl $-1048576, %edi # encoding: [0xf7,0xc7,0x00,0x00,0xf0,0xff]
+; NDD-ZU-NEXT: # imm = 0xFFF00000
+; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%and = and i32 %val, -1048576
%cmp = icmp ne i32 %and, 0
%ret = zext i1 %cmp to i32
@@ -690,12 +927,25 @@ define i32 @highmask_i32_mask32(i32 %val) {
}
define i32 @highmask_i32_mask8(i32 %val) {
-; CHECK-LABEL: highmask_i32_mask8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; CHECK-NEXT: testl $-16, %edi # encoding: [0xf7,0xc7,0xf0,0xff,0xff,0xff]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
-; CHECK-NEXT: retq # encoding: [0xc3]
+; NO-NDD-LABEL: highmask_i32_mask8:
+; NO-NDD: # %bb.0:
+; NO-NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; NO-NDD-NEXT: testl $-16, %edi # encoding: [0xf7,0xc7,0xf0,0xff,0xff,0xff]
+; NO-NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NO-NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-LABEL: highmask_i32_mask8:
+; NDD: # %bb.0:
+; NDD-NEXT: testl $-16, %edi # encoding: [0xf7,0xc7,0xf0,0xff,0xff,0xff]
+; NDD-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: highmask_i32_mask8:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: testl $-16, %edi # encoding: [0xf7,0xc7,0xf0,0xff,0xff,0xff]
+; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%and = and i32 %val, -16
%cmp = icmp eq i32 %and, 0
%ret = zext i1 %cmp to i32
@@ -703,13 +953,28 @@ define i32 @highmask_i32_mask8(i32 %val) {
}
define i32 @lowmask_i32_mask32(i32 %val) {
-; CHECK-LABEL: lowmask_i32_mask32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; CHECK-NEXT: testl $1048575, %edi # encoding: [0xf7,0xc7,0xff,0xff,0x0f,0x00]
-; CHECK-NEXT: # imm = 0xFFFFF
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
-; CHECK-NEXT: retq # encoding: [0xc3]
+; NO-NDD-LABEL: lowmask_i32_mask32:
+; NO-NDD: # %bb.0:
+; NO-NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; NO-NDD-NEXT: testl $1048575, %edi # encoding: [0xf7,0xc7,0xff,0xff,0x0f,0x00]
+; NO-NDD-NEXT: # imm = 0xFFFFF
+; NO-NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NO-NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-LABEL: lowmask_i32_mask32:
+; NDD: # %bb.0:
+; NDD-NEXT: testl $1048575, %edi # encoding: [0xf7,0xc7,0xff,0xff,0x0f,0x00]
+; NDD-NEXT: # imm = 0xFFFFF
+; NDD-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: lowmask_i32_mask32:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: testl $1048575, %edi # encoding: [0xf7,0xc7,0xff,0xff,0x0f,0x00]
+; NDD-ZU-NEXT: # imm = 0xFFFFF
+; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%and = and i32 %val, 1048575
%cmp = icmp eq i32 %and, 0
%ret = zext i1 %cmp to i32
@@ -717,12 +982,25 @@ define i32 @lowmask_i32_mask32(i32 %val) {
}
define i32 @lowmask_i32_mask8(i32 %val) {
-; CHECK-LABEL: lowmask_i32_mask8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; CHECK-NEXT: testb $31, %dil # encoding: [0x40,0xf6,0xc7,0x1f]
-; CHECK-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
-; CHECK-NEXT: retq # encoding: [0xc3]
+; NO-NDD-LABEL: lowmask_i32_mask8:
+; NO-NDD: # %bb.0:
+; NO-NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; NO-NDD-NEXT: testb $31, %dil # encoding: [0x40,0xf6,0xc7,0x1f]
+; NO-NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
+; NO-NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-LABEL: lowmask_i32_mask8:
+; NDD: # %bb.0:
+; NDD-NEXT: testb $31, %dil # encoding: [0x40,0xf6,0xc7,0x1f]
+; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: lowmask_i32_mask8:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: testb $31, %dil # encoding: [0x40,0xf6,0xc7,0x1f]
+; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%and = and i32 %val, 31
%cmp = icmp ne i32 %and, 0
%ret = zext i1 %cmp to i32
@@ -741,8 +1019,15 @@ define i1 @shifted_mask64_testb(i64 %a) {
; NDD: # %bb.0:
; NDD-NEXT: shrq $50, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x32]
; NDD-NEXT: testb %dil, %dil # encoding: [0x40,0x84,0xff]
-; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
+; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: shifted_mask64_testb:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: shrq $50, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x32]
+; NDD-ZU-NEXT: testb %dil, %dil # encoding: [0x40,0x84,0xff]
+; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%v0 = and i64 %a, 287104476244869120 ; 0xff << 50
%v1 = icmp ne i64 %v0, 0
ret i1 %v1
@@ -760,8 +1045,15 @@ define i1 @shifted_mask64_testw(i64 %a) {
; NDD: # %bb.0:
; NDD-NEXT: shrq $33, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x21]
; NDD-NEXT: testw %di, %di # encoding: [0x66,0x85,0xff]
-; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
+; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: shifted_mask64_testw:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: shrq $33, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x21]
+; NDD-ZU-NEXT: testw %di, %di # encoding: [0x66,0x85,0xff]
+; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%v0 = and i64 %a, 562941363486720 ; 0xffff << 33
%v1 = icmp ne i64 %v0, 0
ret i1 %v1
@@ -779,23 +1071,50 @@ define i1 @shifted_mask64_testl(i64 %a) {
; NDD: # %bb.0:
; NDD-NEXT: shrq $7, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x07]
; NDD-NEXT: testl %edi, %edi # encoding: [0x85,0xff]
-; NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NDD-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: shifted_mask64_testl:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: shrq $7, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x07]
+; NDD-ZU-NEXT: testl %edi, %edi # encoding: [0x85,0xff]
+; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%v0 = and i64 %a, 549755813760 ; 0xffffffff << 7
%v1 = icmp eq i64 %v0, 0
ret i1 %v1
}
define i1 @shifted_mask64_extra_use_const(i64 %a) {
-; CHECK-LABEL: shifted_mask64_extra_use_const:
-; CHECK: # %bb.0:
-; CHECK-NEXT: movabsq $287104476244869120, %rcx # encoding: [0x48,0xb9,0x00,0x00,0x00,0x00,0x00,0x00,0xfc,0x03]
-; CHECK-NEXT: # imm = 0x3FC000000000000
-; CHECK-NEXT: testq %rcx, %rdi # encoding: [0x48,0x85,0xcf]
-; CHECK-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
-; CHECK-NEXT: movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A]
-; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
-; CHECK-NEXT: retq # encoding: [0xc3]
+; NO-NDD-LABEL: shifted_mask64_extra_use_const:
+; NO-NDD: # %bb.0:
+; NO-NDD-NEXT: movabsq $287104476244869120, %rcx # encoding: [0x48,0xb9,0x00,0x00,0x00,0x00,0x00,0x00,0xfc,0x03]
+; NO-NDD-NEXT: # imm = 0x3FC000000000000
+; NO-NDD-NEXT: testq %rcx, %rdi # encoding: [0x48,0x85,0xcf]
+; NO-NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
+; NO-NDD-NEXT: movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A]
+; NO-NDD-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
+; NO-NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-LABEL: shifted_mask64_extra_use_const:
+; NDD: # %bb.0:
+; NDD-NEXT: movabsq $287104476244869120, %rcx # encoding: [0x48,0xb9,0x00,0x00,0x00,0x00,0x00,0x00,0xfc,0x03]
+; NDD-NEXT: # imm = 0x3FC000000000000
+; NDD-NEXT: testq %rcx, %rdi # encoding: [0x48,0x85,0xcf]
+; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-NEXT: movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A]
+; NDD-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
+; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: shifted_mask64_extra_use_const:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: movabsq $287104476244869120, %rcx # encoding: [0x48,0xb9,0x00,0x00,0x00,0x00,0x00,0x00,0xfc,0x03]
+; NDD-ZU-NEXT: # imm = 0x3FC000000000000
+; NDD-ZU-NEXT: testq %rcx, %rdi # encoding: [0x48,0x85,0xcf]
+; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-ZU-NEXT: movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A]
+; NDD-ZU-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%v0 = and i64 %a, 287104476244869120 ; 0xff << 50
%v1 = icmp ne i64 %v0, 0
store i64 287104476244869120, ptr @d64
@@ -818,10 +1137,20 @@ define i1 @shifted_mask64_extra_use_and(i64 %a) {
; NDD-NEXT: movabsq $287104476244869120, %rax # encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0x00,0xfc,0x03]
; NDD-NEXT: # imm = 0x3FC000000000000
; NDD-NEXT: andq %rax, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x21,0xc7]
-; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
+; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
; NDD-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
; NDD-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: shifted_mask64_extra_use_and:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: movabsq $287104476244869120, %rax # encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0x00,0xfc,0x03]
+; NDD-ZU-NEXT: # imm = 0x3FC000000000000
+; NDD-ZU-NEXT: andq %rax, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x21,0xc7]
+; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-ZU-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
+; NDD-ZU-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%v0 = and i64 %a, 287104476244869120 ; 0xff << 50
%v1 = icmp ne i64 %v0, 0
store i64 %v0, ptr @d64
@@ -829,27 +1158,61 @@ define i1 @shifted_mask64_extra_use_and(i64 %a) {
}
define i1 @shifted_mask32_testl_immediate(i64 %a) {
-; CHECK-LABEL: shifted_mask32_testl_immediate:
-; CHECK: # %bb.0:
-; CHECK-NEXT: testl $66846720, %edi # encoding: [0xf7,0xc7,0x00,0x00,0xfc,0x03]
-; CHECK-NEXT: # imm = 0x3FC0000
-; CHECK-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
-; CHECK-NEXT: retq # encoding: [0xc3]
+; NO-NDD-LABEL: shifted_mask32_testl_immediate:
+; NO-NDD: # %bb.0:
+; NO-NDD-NEXT: testl $66846720, %edi # encoding: [0xf7,0xc7,0x00,0x00,0xfc,0x03]
+; NO-NDD-NEXT: # imm = 0x3FC0000
+; NO-NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
+; NO-NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-LABEL: shifted_mask32_testl_immediate:
+; NDD: # %bb.0:
+; NDD-NEXT: testl $66846720, %edi # encoding: [0xf7,0xc7,0x00,0x00,0xfc,0x03]
+; NDD-NEXT: # imm = 0x3FC0000
+; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: shifted_mask32_testl_immediate:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: testl $66846720, %edi # encoding: [0xf7,0xc7,0x00,0x00,0xfc,0x03]
+; NDD-ZU-NEXT: # imm = 0x3FC0000
+; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%v0 = and i64 %a, 66846720 ; 0xff << 18
%v1 = icmp ne i64 %v0, 0
ret i1 %v1
}
define i1 @shifted_mask32_extra_use_const(i64 %a) {
-; CHECK-LABEL: shifted_mask32_extra_use_const:
-; CHECK: # %bb.0:
-; CHECK-NEXT: testl $66846720, %edi # encoding: [0xf7,0xc7,0x00,0x00,0xfc,0x03]
-; CHECK-NEXT: # imm = 0x3FC0000
-; CHECK-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
-; CHECK-NEXT: movq $66846720, d64(%rip) # encoding: [0x48,0xc7,0x05,A,A,A,A,0x00,0x00,0xfc,0x03]
-; CHECK-NEXT: # fixup A - offset: 3, value: d64-8, kind: reloc_riprel_4byte
-; CHECK-NEXT: # imm = 0x3FC0000
-; CHECK-NEXT: retq # encoding: [0xc3]
+; NO-NDD-LABEL: shifted_mask32_extra_use_const:
+; NO-NDD: # %bb.0:
+; NO-NDD-NEXT: testl $66846720, %edi # encoding: [0xf7,0xc7,0x00,0x00,0xfc,0x03]
+; NO-NDD-NEXT: # imm = 0x3FC0000
+; NO-NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
+; NO-NDD-NEXT: movq $66846720, d64(%rip) # encoding: [0x48,0xc7,0x05,A,A,A,A,0x00,0x00,0xfc,0x03]
+; NO-NDD-NEXT: # fixup A - offset: 3, value: d64-8, kind: reloc_riprel_4byte
+; NO-NDD-NEXT: # imm = 0x3FC0000
+; NO-NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-LABEL: shifted_mask32_extra_use_const:
+; NDD: # %bb.0:
+; NDD-NEXT: testl $66846720, %edi # encoding: [0xf7,0xc7,0x00,0x00,0xfc,0x03]
+; NDD-NEXT: # imm = 0x3FC0000
+; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-NEXT: movq $66846720, d64(%rip) # encoding: [0x48,0xc7,0x05,A,A,A,A,0x00,0x00,0xfc,0x03]
+; NDD-NEXT: # fixup A - offset: 3, value: d64-8, kind: reloc_riprel_4byte
+; NDD-NEXT: # imm = 0x3FC0000
+; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: shifted_mask32_extra_use_const:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: testl $66846720, %edi # encoding: [0xf7,0xc7,0x00,0x00,0xfc,0x03]
+; NDD-ZU-NEXT: # imm = 0x3FC0000
+; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-ZU-NEXT: movq $66846720, d64(%rip) # encoding: [0x48,0xc7,0x05,A,A,A,A,0x00,0x00,0xfc,0x03]
+; NDD-ZU-NEXT: # fixup A - offset: 3, value: d64-8, kind: reloc_riprel_4byte
+; NDD-ZU-NEXT: # imm = 0x3FC0000
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%v0 = and i64 %a, 66846720 ; 0xff << 18
%v1 = icmp ne i64 %v0, 0
store i64 66846720, ptr @d64
@@ -870,10 +1233,19 @@ define i1 @shifted_mask32_extra_use_and(i64 %a) {
; NDD: # %bb.0:
; NDD-NEXT: andq $66846720, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x81,0xe7,0x00,0x00,0xfc,0x03]
; NDD-NEXT: # imm = 0x3FC0000
-; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
+; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
; NDD-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
; NDD-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: shifted_mask32_extra_use_and:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: andq $66846720, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x81,0xe7,0x00,0x00,0xfc,0x03]
+; NDD-ZU-NEXT: # imm = 0x3FC0000
+; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-ZU-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
+; NDD-ZU-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%v0 = and i64 %a, 66846720 ; 0xff << 50
%v1 = icmp ne i64 %v0, 0
store i64 %v0, ptr @d64
@@ -897,6 +1269,14 @@ define { i64, i64 } @pr39968(i64, i64, i32) {
; NDD-NEXT: cmovneq %rdi, %rsi, %rdx # encoding: [0x62,0xf4,0xec,0x18,0x45,0xf7]
; NDD-NEXT: cmovneq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0x45,0xc7]
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: pr39968:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; NDD-ZU-NEXT: testb $64, %dl # encoding: [0xf6,0xc2,0x40]
+; NDD-ZU-NEXT: cmovneq %rdi, %rsi, %rdx # encoding: [0x62,0xf4,0xec,0x18,0x45,0xf7]
+; NDD-ZU-NEXT: cmovneq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0x45,0xc7]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%4 = and i32 %2, 64
%5 = icmp ne i32 %4, 0
%6 = select i1 %5, i64 %0, i64 %1
@@ -944,12 +1324,26 @@ declare i32 @f()
; The store makes sure the chain result of the load is used which used to
; prevent the post isel peephole from catching this.
define i1 @fold_test_and_with_chain(ptr %x, ptr %y, i32 %z) {
-; CHECK-LABEL: fold_test_and_with_chain:
-; CHECK: # %bb.0:
-; CHECK-NEXT: testl %edx, (%rdi) # encoding: [0x85,0x17]
-; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
-; CHECK-NEXT: movl %edx, (%rsi) # encoding: [0x89,0x16]
-; CHECK-NEXT: retq # encoding: [0xc3]
+; NO-NDD-LABEL: fold_test_and_with_chain:
+; NO-NDD: # %bb.0:
+; NO-NDD-NEXT: testl %edx, (%rdi) # encoding: [0x85,0x17]
+; NO-NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; NO-NDD-NEXT: movl %edx, (%rsi) # encoding: [0x89,0x16]
+; NO-NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-LABEL: fold_test_and_with_chain:
+; NDD: # %bb.0:
+; NDD-NEXT: testl %edx, (%rdi) # encoding: [0x85,0x17]
+; NDD-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NDD-NEXT: movl %edx, (%rsi) # encoding: [0x89,0x16]
+; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: fold_test_and_with_chain:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: testl %edx, (%rdi) # encoding: [0x85,0x17]
+; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NDD-ZU-NEXT: movl %edx, (%rsi) # encoding: [0x89,0x16]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
%a = load i32, ptr %x
%b = and i32 %z, %a
%c = icmp eq i32 %b, 0
diff --git a/llvm/test/CodeGen/X86/is_fpclass.ll b/llvm/test/CodeGen/X86/is_fpclass.ll
index 97136dafa6c2c..174a0da9af86d 100644
--- a/llvm/test/CodeGen/X86/is_fpclass.ll
+++ b/llvm/test/CodeGen/X86/is_fpclass.ll
@@ -14,11 +14,17 @@ define i1 @isnan_f(float %x) {
; X86-NEXT: setp %al
; X86-NEXT: retl
;
-; X64-LABEL: isnan_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: ucomiss %xmm0, %xmm0
-; X64-NEXT: setp %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: isnan_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: ucomiss %xmm0, %xmm0
+; X64-GENERIC-NEXT: setp %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: isnan_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: ucomiss %xmm0, %xmm0
+; X64-NDD-NEXT: setzup %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 3) ; "nan"
ret i1 %0
@@ -35,11 +41,17 @@ define i1 @isnot_nan_f(float %x) {
; X86-NEXT: setnp %al
; X86-NEXT: retl
;
-; X64-LABEL: isnot_nan_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: ucomiss %xmm0, %xmm0
-; X64-NEXT: setnp %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: isnot_nan_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: ucomiss %xmm0, %xmm0
+; X64-GENERIC-NEXT: setnp %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: isnot_nan_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: ucomiss %xmm0, %xmm0
+; X64-NDD-NEXT: setzunp %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1020) ; 0x3fc = "zero|subnormal|normal|inf"
ret i1 %0
@@ -57,16 +69,27 @@ define i1 @issignaling_f(float %x) {
; X86-NEXT: andb %cl, %al
; X86-NEXT: retl
;
-; X64-LABEL: issignaling_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NEXT: setl %cl
-; X64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-NEXT: setge %al
-; X64-NEXT: andb %cl, %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: issignaling_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-GENERIC-NEXT: setl %cl
+; X64-GENERIC-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-GENERIC-NEXT: setge %al
+; X64-GENERIC-NEXT: andb %cl, %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: issignaling_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-NDD-NEXT: setzul %cl
+; X64-NDD-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-NDD-NEXT: setzuge %al
+; X64-NDD-NEXT: andb %cl, %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1) ; "snan"
ret i1 %0
@@ -84,16 +107,27 @@ define i1 @not_issignaling_f(float %x) {
; X86-NEXT: orb %cl, %al
; X86-NEXT: retl
;
-; X64-LABEL: not_issignaling_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NEXT: setge %cl
-; X64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-NEXT: setl %al
-; X64-NEXT: orb %cl, %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_issignaling_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-GENERIC-NEXT: setge %cl
+; X64-GENERIC-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-GENERIC-NEXT: setl %al
+; X64-GENERIC-NEXT: orb %cl, %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: not_issignaling_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-NDD-NEXT: setzuge %cl
+; X64-NDD-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-NDD-NEXT: setzul %al
+; X64-NDD-NEXT: orb %cl, %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1022) ; ~"snan"
ret i1 %0
@@ -108,13 +142,21 @@ define i1 @isquiet_f(float %x) {
; X86-NEXT: setge %al
; X86-NEXT: retl
;
-; X64-LABEL: isquiet_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NEXT: setge %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: isquiet_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-GENERIC-NEXT: setge %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: isquiet_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-NDD-NEXT: setzuge %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 2) ; "qnan"
ret i1 %0
@@ -129,13 +171,21 @@ define i1 @not_isquiet_f(float %x) {
; X86-NEXT: setl %al
; X86-NEXT: retl
;
-; X64-LABEL: not_isquiet_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NEXT: setl %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_isquiet_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-GENERIC-NEXT: setl %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: not_isquiet_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-NDD-NEXT: setzul %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1021) ; ~"qnan"
ret i1 %0
@@ -150,13 +200,21 @@ define i1 @isinf_f(float %x) {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-LABEL: isinf_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: sete %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: isinf_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: sete %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: isinf_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NDD-NEXT: setzue %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 516) ; 0x204 = "inf"
ret i1 %0
@@ -171,13 +229,21 @@ define i1 @not_isinf_f(float %x) {
; X86-NEXT: setne %al
; X86-NEXT: retl
;
-; X64-LABEL: not_isinf_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: setne %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_isinf_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: setne %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: not_isinf_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NDD-NEXT: setzune %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 507) ; ~0x204 = "~inf"
ret i1 %0
@@ -190,12 +256,19 @@ define i1 @is_plus_inf_f(float %x) {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-LABEL: is_plus_inf_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: sete %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: is_plus_inf_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: sete %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: is_plus_inf_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NDD-NEXT: setzue %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 512) ; 0x200 = "+inf"
ret i1 %0
@@ -208,12 +281,19 @@ define i1 @is_minus_inf_f(float %x) {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-LABEL: is_minus_inf_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
-; X64-NEXT: sete %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: is_minus_inf_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
+; X64-GENERIC-NEXT: sete %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: is_minus_inf_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
+; X64-NDD-NEXT: setzue %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 4) ; "-inf"
ret i1 %0
@@ -226,12 +306,19 @@ define i1 @not_is_minus_inf_f(float %x) {
; X86-NEXT: setne %al
; X86-NEXT: retl
;
-; X64-LABEL: not_is_minus_inf_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
-; X64-NEXT: setne %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_is_minus_inf_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
+; X64-GENERIC-NEXT: setne %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: not_is_minus_inf_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
+; X64-NDD-NEXT: setzune %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1019) ; ~"-inf"
ret i1 %0
@@ -246,13 +333,21 @@ define i1 @isfinite_f(float %x) {
; X86-NEXT: setl %al
; X86-NEXT: retl
;
-; X64-LABEL: isfinite_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: setl %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: isfinite_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: setl %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: isfinite_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NDD-NEXT: setzul %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 504) ; 0x1f8 = "finite"
ret i1 %0
@@ -267,13 +362,21 @@ define i1 @not_isfinite_f(float %x) {
; X86-NEXT: setge %al
; X86-NEXT: retl
;
-; X64-LABEL: not_isfinite_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: setge %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_isfinite_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: setge %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: not_isfinite_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NDD-NEXT: setzuge %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 519) ; ~0x1f8 = "~finite"
ret i1 %0
@@ -286,12 +389,19 @@ define i1 @is_plus_finite_f(float %x) {
; X86-NEXT: setb %al
; X86-NEXT: retl
;
-; X64-LABEL: is_plus_finite_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: setb %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: is_plus_finite_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: setb %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: is_plus_finite_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NDD-NEXT: setzub %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 448) ; 0x1c0 = "+finite"
ret i1 %0
@@ -304,12 +414,19 @@ define i1 @not_is_plus_finite_f(float %x) {
; X86-NEXT: setae %al
; X86-NEXT: retl
;
-; X64-LABEL: not_is_plus_finite_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: setae %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_is_plus_finite_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: setae %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: not_is_plus_finite_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NDD-NEXT: setzuae %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 575) ; ~0x1c0 = ~"+finite"
ret i1 %0
@@ -327,16 +444,27 @@ define i1 @is_minus_finite_f(float %x) {
; X86-NEXT: andb %cl, %al
; X86-NEXT: retl
;
-; X64-LABEL: is_minus_finite_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: testl %eax, %eax
-; X64-NEXT: sets %cl
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: setl %al
-; X64-NEXT: andb %cl, %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: is_minus_finite_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: testl %eax, %eax
+; X64-GENERIC-NEXT: sets %cl
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: setl %al
+; X64-GENERIC-NEXT: andb %cl, %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: is_minus_finite_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: testl %eax, %eax
+; X64-NDD-NEXT: setzus %cl
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NDD-NEXT: setzul %al
+; X64-NDD-NEXT: andb %cl, %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 56) ; 0x38 = "-finite"
ret i1 %0
@@ -354,16 +482,27 @@ define i1 @not_is_minus_finite_f(float %x) {
; X86-NEXT: orb %cl, %al
; X86-NEXT: retl
;
-; X64-LABEL: not_is_minus_finite_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: testl %eax, %eax
-; X64-NEXT: setns %cl
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: setge %al
-; X64-NEXT: orb %cl, %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_is_minus_finite_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: testl %eax, %eax
+; X64-GENERIC-NEXT: setns %cl
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: setge %al
+; X64-GENERIC-NEXT: orb %cl, %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: not_is_minus_finite_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: testl %eax, %eax
+; X64-NDD-NEXT: setzuns %cl
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NDD-NEXT: setzuge %al
+; X64-NDD-NEXT: orb %cl, %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 967) ; ~0x38 = ~"-finite"
ret i1 %0
@@ -379,14 +518,23 @@ define i1 @isnormal_f(float %x) #1 {
; X86-NEXT: setb %al
; X86-NEXT: retl
;
-; X64-LABEL: isnormal_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: addl $-8388608, %eax # imm = 0xFF800000
-; X64-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; X64-NEXT: setb %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: isnormal_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: addl $-8388608, %eax # imm = 0xFF800000
+; X64-GENERIC-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
+; X64-GENERIC-NEXT: setb %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: isnormal_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: addl $-8388608, %eax # imm = 0xFF800000
+; X64-NDD-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
+; X64-NDD-NEXT: setzub %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 264) ; 0x108 = "normal"
ret i1 %0
@@ -402,14 +550,23 @@ define i1 @not_isnormal_f(float %x) #1 {
; X86-NEXT: setae %al
; X86-NEXT: retl
;
-; X64-LABEL: not_isnormal_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: addl $-8388608, %eax # imm = 0xFF800000
-; X64-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; X64-NEXT: setae %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_isnormal_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: addl $-8388608, %eax # imm = 0xFF800000
+; X64-GENERIC-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
+; X64-GENERIC-NEXT: setae %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: not_isnormal_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: addl $-8388608, %eax # imm = 0xFF800000
+; X64-NDD-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
+; X64-NDD-NEXT: setzuae %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 759) ; ~0x108 = "~normal"
ret i1 %0
@@ -428,17 +585,29 @@ define i1 @is_plus_normal_f(float %x) {
; X86-NEXT: andb %cl, %al
; X86-NEXT: retl
;
-; X64-LABEL: is_plus_normal_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: testl %eax, %eax
-; X64-NEXT: setns %cl
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: addl $-8388608, %eax # imm = 0xFF800000
-; X64-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; X64-NEXT: setb %al
-; X64-NEXT: andb %cl, %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: is_plus_normal_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: testl %eax, %eax
+; X64-GENERIC-NEXT: setns %cl
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: addl $-8388608, %eax # imm = 0xFF800000
+; X64-GENERIC-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
+; X64-GENERIC-NEXT: setb %al
+; X64-GENERIC-NEXT: andb %cl, %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: is_plus_normal_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: testl %eax, %eax
+; X64-NDD-NEXT: setzuns %cl
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: addl $-8388608, %eax # imm = 0xFF800000
+; X64-NDD-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
+; X64-NDD-NEXT: setzub %al
+; X64-NDD-NEXT: andb %cl, %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 256) ; 0x100 = "+normal"
ret i1 %0
@@ -454,14 +623,23 @@ define i1 @issubnormal_f(float %x) {
; X86-NEXT: setb %al
; X86-NEXT: retl
;
-; X64-LABEL: issubnormal_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: decl %eax
-; X64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
-; X64-NEXT: setb %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: issubnormal_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: decl %eax
+; X64-GENERIC-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-GENERIC-NEXT: setb %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: issubnormal_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: decl %eax
+; X64-NDD-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-NDD-NEXT: setzub %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 144) ; 0x90 = "subnormal"
ret i1 %0
@@ -477,14 +655,23 @@ define i1 @issubnormal_f_daz(float %x) #0 {
; X86-NEXT: setb %al
; X86-NEXT: retl
;
-; X64-LABEL: issubnormal_f_daz:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: decl %eax
-; X64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
-; X64-NEXT: setb %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: issubnormal_f_daz:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: decl %eax
+; X64-GENERIC-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-GENERIC-NEXT: setb %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: issubnormal_f_daz:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: decl %eax
+; X64-NDD-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-NDD-NEXT: setzub %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 144) ; 0x90 = "subnormal"
ret i1 %0
@@ -500,14 +687,23 @@ define i1 @issubnormal_f_maybe_daz(float %x) #1 {
; X86-NEXT: setb %al
; X86-NEXT: retl
;
-; X64-LABEL: issubnormal_f_maybe_daz:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: decl %eax
-; X64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
-; X64-NEXT: setb %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: issubnormal_f_maybe_daz:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: decl %eax
+; X64-GENERIC-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-GENERIC-NEXT: setb %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: issubnormal_f_maybe_daz:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: decl %eax
+; X64-NDD-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-NDD-NEXT: setzub %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 144) ; 0x90 = "subnormal"
ret i1 %0
@@ -523,14 +719,23 @@ define i1 @not_issubnormal_f(float %x) {
; X86-NEXT: setae %al
; X86-NEXT: retl
;
-; X64-LABEL: not_issubnormal_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: decl %eax
-; X64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
-; X64-NEXT: setae %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_issubnormal_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: decl %eax
+; X64-GENERIC-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-GENERIC-NEXT: setae %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: not_issubnormal_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: decl %eax
+; X64-NDD-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-NDD-NEXT: setzuae %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 879) ; ~0x90 = "~subnormal"
ret i1 %0
@@ -546,14 +751,23 @@ define i1 @not_issubnormal_f_daz(float %x) #0 {
; X86-NEXT: setae %al
; X86-NEXT: retl
;
-; X64-LABEL: not_issubnormal_f_daz:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: decl %eax
-; X64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
-; X64-NEXT: setae %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_issubnormal_f_daz:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: decl %eax
+; X64-GENERIC-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-GENERIC-NEXT: setae %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: not_issubnormal_f_daz:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: decl %eax
+; X64-NDD-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-NDD-NEXT: setzuae %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 879) ; ~0x90 = "~subnormal"
ret i1 %0
@@ -569,14 +783,23 @@ define i1 @not_issubnormal_f_maybe_daz(float %x) #1 {
; X86-NEXT: setae %al
; X86-NEXT: retl
;
-; X64-LABEL: not_issubnormal_f_maybe_daz:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: decl %eax
-; X64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
-; X64-NEXT: setae %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_issubnormal_f_maybe_daz:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: decl %eax
+; X64-GENERIC-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-GENERIC-NEXT: setae %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: not_issubnormal_f_maybe_daz:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: decl %eax
+; X64-NDD-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-NDD-NEXT: setzuae %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 879) ; ~0x90 = "~subnormal"
ret i1 %0
@@ -591,13 +814,21 @@ define i1 @is_plus_subnormal_f(float %x) {
; X86-NEXT: setb %al
; X86-NEXT: retl
;
-; X64-LABEL: is_plus_subnormal_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: decl %eax
-; X64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
-; X64-NEXT: setb %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: is_plus_subnormal_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: decl %eax
+; X64-GENERIC-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-GENERIC-NEXT: setb %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: is_plus_subnormal_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: decl %eax
+; X64-NDD-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-NDD-NEXT: setzub %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 128) ; 0x80 = "+subnormal"
ret i1 %0
@@ -612,13 +843,21 @@ define i1 @not_is_plus_subnormal_f(float %x) {
; X86-NEXT: setae %al
; X86-NEXT: retl
;
-; X64-LABEL: not_is_plus_subnormal_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: decl %eax
-; X64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
-; X64-NEXT: setae %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_is_plus_subnormal_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: decl %eax
+; X64-GENERIC-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-GENERIC-NEXT: setae %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: not_is_plus_subnormal_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: decl %eax
+; X64-NDD-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-NDD-NEXT: setzuae %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 895) ; ~0x80 = ~"+subnormal"
ret i1 %0
@@ -637,17 +876,29 @@ define i1 @is_minus_subnormal_f(float %x) {
; X86-NEXT: andb %cl, %al
; X86-NEXT: retl
;
-; X64-LABEL: is_minus_subnormal_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: testl %eax, %eax
-; X64-NEXT: sets %cl
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: decl %eax
-; X64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
-; X64-NEXT: setb %al
-; X64-NEXT: andb %cl, %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: is_minus_subnormal_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: testl %eax, %eax
+; X64-GENERIC-NEXT: sets %cl
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: decl %eax
+; X64-GENERIC-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-GENERIC-NEXT: setb %al
+; X64-GENERIC-NEXT: andb %cl, %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: is_minus_subnormal_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: testl %eax, %eax
+; X64-NDD-NEXT: setzus %cl
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: decl %eax
+; X64-NDD-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-NDD-NEXT: setzub %al
+; X64-NDD-NEXT: andb %cl, %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 16) ; 0x10 = "-subnormal"
ret i1 %0
@@ -666,17 +917,29 @@ define i1 @not_is_minus_subnormal_f(float %x) {
; X86-NEXT: orb %cl, %al
; X86-NEXT: retl
;
-; X64-LABEL: not_is_minus_subnormal_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: testl %eax, %eax
-; X64-NEXT: setns %cl
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: decl %eax
-; X64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
-; X64-NEXT: setae %al
-; X64-NEXT: orb %cl, %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_is_minus_subnormal_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: testl %eax, %eax
+; X64-GENERIC-NEXT: setns %cl
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: decl %eax
+; X64-GENERIC-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-GENERIC-NEXT: setae %al
+; X64-GENERIC-NEXT: orb %cl, %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: not_is_minus_subnormal_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: testl %eax, %eax
+; X64-NDD-NEXT: setzuns %cl
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: decl %eax
+; X64-NDD-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-NDD-NEXT: setzuae %al
+; X64-NDD-NEXT: orb %cl, %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1007) ; ~0x10 = ~"-subnormal"
ret i1 %0
@@ -689,12 +952,19 @@ define i1 @iszero_f(float %x) {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-LABEL: iszero_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: sete %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: iszero_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: sete %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: iszero_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: setzue %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 96) ; 0x60 = "zero"
ret i1 %0
@@ -707,12 +977,19 @@ define i1 @iszero_f_daz(float %x) #0 {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-LABEL: iszero_f_daz:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: sete %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: iszero_f_daz:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: sete %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: iszero_f_daz:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: setzue %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 96) ; 0x60 = "zero"
ret i1 %0
@@ -725,12 +1002,19 @@ define i1 @iszero_f_maybe_daz(float %x) #1 {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-LABEL: iszero_f_maybe_daz:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: sete %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: iszero_f_maybe_daz:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: sete %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: iszero_f_maybe_daz:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: setzue %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 96) ; 0x60 = "zero"
ret i1 %0
@@ -743,12 +1027,19 @@ define i1 @not_iszero_f(float %x) {
; X86-NEXT: setne %al
; X86-NEXT: retl
;
-; X64-LABEL: not_iszero_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: setne %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_iszero_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: setne %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: not_iszero_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: setzune %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 927) ; ~0x60 = "~zero"
ret i1 %0
@@ -761,12 +1052,19 @@ define i1 @not_iszero_f_daz(float %x) #0 {
; X86-NEXT: setne %al
; X86-NEXT: retl
;
-; X64-LABEL: not_iszero_f_daz:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: setne %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_iszero_f_daz:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: setne %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: not_iszero_f_daz:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: setzune %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 927) ; ~0x60 = "~zero"
ret i1 %0
@@ -779,12 +1077,19 @@ define i1 @not_iszero_f_maybe_daz(float %x) #1 {
; X86-NEXT: setne %al
; X86-NEXT: retl
;
-; X64-LABEL: not_iszero_f_maybe_daz:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: setne %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_iszero_f_maybe_daz:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: setne %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: not_iszero_f_maybe_daz:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: setzune %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 927) ; ~0x60 = "~zero"
ret i1 %0
@@ -797,12 +1102,19 @@ define i1 @issubnormal_or_zero_f(float %x) {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-LABEL: issubnormal_or_zero_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: testl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: sete %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: issubnormal_or_zero_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: sete %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: issubnormal_or_zero_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; X64-NDD-NEXT: setzue %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 240) ; 0xf0 = "subnormal|zero"
ret i1 %0
@@ -815,12 +1127,19 @@ define i1 @issubnormal_or_zero_f_daz(float %x) #0 {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-LABEL: issubnormal_or_zero_f_daz:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: testl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: sete %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: issubnormal_or_zero_f_daz:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: sete %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: issubnormal_or_zero_f_daz:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; X64-NDD-NEXT: setzue %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 240) ; 0xf0 = "subnormal|zero"
ret i1 %0
@@ -833,12 +1152,19 @@ define i1 @issubnormal_or_zero_f_maybe_daz(float %x) #1 {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-LABEL: issubnormal_or_zero_f_maybe_daz:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: testl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: sete %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: issubnormal_or_zero_f_maybe_daz:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: sete %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: issubnormal_or_zero_f_maybe_daz:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; X64-NDD-NEXT: setzue %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 240) ; 0xf0 = "subnormal|zero"
ret i1 %0
@@ -851,12 +1177,19 @@ define i1 @not_issubnormal_or_zero_f(float %x) {
; X86-NEXT: setne %al
; X86-NEXT: retl
;
-; X64-LABEL: not_issubnormal_or_zero_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: testl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: setne %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_issubnormal_or_zero_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: setne %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: not_issubnormal_or_zero_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; X64-NDD-NEXT: setzune %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 783) ; ~0xf0 = "~(subnormal|zero)"
ret i1 %0
@@ -869,12 +1202,19 @@ define i1 @not_issubnormal_or_zero_f_daz(float %x) #0 {
; X86-NEXT: setne %al
; X86-NEXT: retl
;
-; X64-LABEL: not_issubnormal_or_zero_f_daz:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: testl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: setne %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_issubnormal_or_zero_f_daz:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: setne %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: not_issubnormal_or_zero_f_daz:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; X64-NDD-NEXT: setzune %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 783) ; ~0xf0 = "~(subnormal|zero)"
ret i1 %0
@@ -887,12 +1227,19 @@ define i1 @not_issubnormal_or_zero_f_maybe_daz(float %x) #1 {
; X86-NEXT: setne %al
; X86-NEXT: retl
;
-; X64-LABEL: not_issubnormal_or_zero_f_maybe_daz:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: testl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: setne %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_issubnormal_or_zero_f_maybe_daz:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: setne %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: not_issubnormal_or_zero_f_maybe_daz:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; X64-NDD-NEXT: setzune %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 783) ; ~0xf0 = "~(subnormal|zero)"
ret i1 %0
@@ -905,12 +1252,19 @@ define i1 @is_plus_zero_f(float %x) {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-LABEL: is_plus_zero_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: testl %eax, %eax
-; X64-NEXT: sete %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: is_plus_zero_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: testl %eax, %eax
+; X64-GENERIC-NEXT: sete %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: is_plus_zero_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: testl %eax, %eax
+; X64-NDD-NEXT: setzue %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 64) ; 0x40 = "+zero"
ret i1 %0
@@ -923,12 +1277,19 @@ define i1 @not_is_plus_zero_f(float %x) {
; X86-NEXT: setne %al
; X86-NEXT: retl
;
-; X64-LABEL: not_is_plus_zero_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: testl %eax, %eax
-; X64-NEXT: setne %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_is_plus_zero_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: testl %eax, %eax
+; X64-GENERIC-NEXT: setne %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: not_is_plus_zero_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: testl %eax, %eax
+; X64-NDD-NEXT: setzune %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 959) ; ~0x40 = ~"+zero"
ret i1 %0
@@ -942,12 +1303,19 @@ define i1 @is_minus_zero_f(float %x) {
; X86-NEXT: seto %al
; X86-NEXT: retl
;
-; X64-LABEL: is_minus_zero_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: negl %eax
-; X64-NEXT: seto %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: is_minus_zero_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: negl %eax
+; X64-GENERIC-NEXT: seto %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: is_minus_zero_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: negl %eax
+; X64-NDD-NEXT: setzuo %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 32) ; 0x20 = "-zero"
ret i1 %0
@@ -961,12 +1329,19 @@ define i1 @not_is_minus_zero_f(float %x) {
; X86-NEXT: setno %al
; X86-NEXT: retl
;
-; X64-LABEL: not_is_minus_zero_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: negl %eax
-; X64-NEXT: setno %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_is_minus_zero_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: negl %eax
+; X64-GENERIC-NEXT: setno %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: not_is_minus_zero_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: negl %eax
+; X64-NDD-NEXT: setzuno %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 991) ; ~0x20 = ~"-zero"
ret i1 %0
@@ -981,13 +1356,21 @@ define i1 @isnan_f_strictfp(float %x) strictfp {
; X86-NEXT: setge %al
; X86-NEXT: retl
;
-; X64-LABEL: isnan_f_strictfp:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-NEXT: setge %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: isnan_f_strictfp:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-GENERIC-NEXT: setge %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: isnan_f_strictfp:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-NDD-NEXT: setzuge %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 3) strictfp ; "nan"
ret i1 %0
@@ -1002,13 +1385,21 @@ define i1 @not_isnan_f_strictfp(float %x) strictfp {
; X86-NEXT: setl %al
; X86-NEXT: retl
;
-; X64-LABEL: not_isnan_f_strictfp:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-NEXT: setl %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_isnan_f_strictfp:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-GENERIC-NEXT: setl %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: not_isnan_f_strictfp:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-NDD-NEXT: setzul %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1020) strictfp ; ~"nan"
ret i1 %0
@@ -1023,13 +1414,21 @@ define i1 @isfinite_f_strictfp(float %x) strictfp {
; X86-NEXT: setl %al
; X86-NEXT: retl
;
-; X64-LABEL: isfinite_f_strictfp:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: setl %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: isfinite_f_strictfp:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: setl %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: isfinite_f_strictfp:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NDD-NEXT: setzul %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 504) strictfp ; 0x1f8 = "finite"
ret i1 %0
@@ -1044,13 +1443,21 @@ define i1 @not_isfinite_f_strictfp(float %x) strictfp {
; X86-NEXT: setge %al
; X86-NEXT: retl
;
-; X64-LABEL: not_isfinite_f_strictfp:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: setge %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_isfinite_f_strictfp:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: setge %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: not_isfinite_f_strictfp:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NDD-NEXT: setzuge %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 519) strictfp ; ~0x1f8 = ~"finite"
ret i1 %0
@@ -1063,12 +1470,19 @@ define i1 @iszero_f_strictfp(float %x) strictfp {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-LABEL: iszero_f_strictfp:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: sete %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: iszero_f_strictfp:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: sete %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: iszero_f_strictfp:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: setzue %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 96) strictfp ; 0x60 = "zero"
ret i1 %0
@@ -1081,12 +1495,19 @@ define i1 @not_iszero_f_strictfp(float %x) strictfp {
; X86-NEXT: setne %al
; X86-NEXT: retl
;
-; X64-LABEL: not_iszero_f_strictfp:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: setne %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_iszero_f_strictfp:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: setne %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: not_iszero_f_strictfp:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: setzune %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 927) strictfp ; ~0x60 = ~"zero"
ret i1 %0
@@ -1103,11 +1524,17 @@ define i1 @isnan_d(double %x) {
; X86-NEXT: setp %al
; X86-NEXT: retl
;
-; X64-LABEL: isnan_d:
-; X64: # %bb.0: # %entry
-; X64-NEXT: ucomisd %xmm0, %xmm0
-; X64-NEXT: setp %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: isnan_d:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: ucomisd %xmm0, %xmm0
+; X64-GENERIC-NEXT: setp %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: isnan_d:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: ucomisd %xmm0, %xmm0
+; X64-NDD-NEXT: setzup %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 3) ; "nan"
ret i1 %0
@@ -1140,7 +1567,7 @@ define i1 @isinf_d(double %x) {
; X64-NDD-NEXT: andq %rcx, %rax
; X64-NDD-NEXT: movabsq $9218868437227405312, %rcx # imm = 0x7FF0000000000000
; X64-NDD-NEXT: cmpq %rcx, %rax
-; X64-NDD-NEXT: sete %al
+; X64-NDD-NEXT: setzue %al
; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 516) ; 0x204 = "inf"
@@ -1173,7 +1600,7 @@ define i1 @isfinite_d(double %x) {
; X64-NDD-NEXT: andq %rcx, %rax
; X64-NDD-NEXT: movabsq $9218868437227405312, %rcx # imm = 0x7FF0000000000000
; X64-NDD-NEXT: cmpq %rcx, %rax
-; X64-NDD-NEXT: setl %al
+; X64-NDD-NEXT: setzul %al
; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 504) ; 0x1f8 = "finite"
@@ -1212,7 +1639,7 @@ define i1 @isnormal_d(double %x) {
; X64-NDD-NEXT: addq %rcx, %rax
; X64-NDD-NEXT: shrq $53, %rax
; X64-NDD-NEXT: cmpl $1023, %eax # imm = 0x3FF
-; X64-NDD-NEXT: setb %al
+; X64-NDD-NEXT: setzub %al
; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 264) ; 0x108 = "normal"
@@ -1251,7 +1678,7 @@ define i1 @issubnormal_d(double %x) {
; X64-NDD-NEXT: decq %rax
; X64-NDD-NEXT: movabsq $4503599627370495, %rcx # imm = 0xFFFFFFFFFFFFF
; X64-NDD-NEXT: cmpq %rcx, %rax
-; X64-NDD-NEXT: setb %al
+; X64-NDD-NEXT: setzub %al
; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 144) ; 0x90 = "subnormal"
@@ -1267,13 +1694,21 @@ define i1 @iszero_d(double %x) {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-LABEL: iszero_d:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movq %xmm0, %rax
-; X64-NEXT: shlq %rax
-; X64-NEXT: testq %rax, %rax
-; X64-NEXT: sete %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: iszero_d:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movq %xmm0, %rax
+; X64-GENERIC-NEXT: shlq %rax
+; X64-GENERIC-NEXT: testq %rax, %rax
+; X64-GENERIC-NEXT: sete %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: iszero_d:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movq %xmm0, %rax
+; X64-NDD-NEXT: shlq %rax
+; X64-NDD-NEXT: testq %rax, %rax
+; X64-NDD-NEXT: setzue %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 96) ; 0x60 = "zero"
ret i1 %0
@@ -1315,10 +1750,10 @@ define i1 @issignaling_d(double %x) {
; X64-NDD-NEXT: andq %rcx, %rax
; X64-NDD-NEXT: movabsq $9221120237041090560, %rcx # imm = 0x7FF8000000000000
; X64-NDD-NEXT: cmpq %rcx, %rax
-; X64-NDD-NEXT: setl %cl
+; X64-NDD-NEXT: setzul %cl
; X64-NDD-NEXT: movabsq $9218868437227405312, %rdx # imm = 0x7FF0000000000000
; X64-NDD-NEXT: cmpq %rdx, %rax
-; X64-NDD-NEXT: setg %al
+; X64-NDD-NEXT: setzug %al
; X64-NDD-NEXT: andb %cl, %al
; X64-NDD-NEXT: retq
entry:
@@ -1352,7 +1787,7 @@ define i1 @isquiet_d(double %x) {
; X64-NDD-NEXT: andq %rcx, %rax
; X64-NDD-NEXT: movabsq $9221120237041090559, %rcx # imm = 0x7FF7FFFFFFFFFFFF
; X64-NDD-NEXT: cmpq %rcx, %rax
-; X64-NDD-NEXT: setg %al
+; X64-NDD-NEXT: setzug %al
; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 2) ; "qnan"
@@ -1388,7 +1823,7 @@ define i1 @isnan_d_strictfp(double %x) strictfp {
; X64-NDD-NEXT: andq %rcx, %rax
; X64-NDD-NEXT: movabsq $9218868437227405312, %rcx # imm = 0x7FF0000000000000
; X64-NDD-NEXT: cmpq %rcx, %rax
-; X64-NDD-NEXT: setg %al
+; X64-NDD-NEXT: setzug %al
; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 3) strictfp ; "nan"
@@ -1404,13 +1839,21 @@ define i1 @iszero_d_strictfp(double %x) strictfp {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-LABEL: iszero_d_strictfp:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movq %xmm0, %rax
-; X64-NEXT: shlq %rax
-; X64-NEXT: testq %rax, %rax
-; X64-NEXT: sete %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: iszero_d_strictfp:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movq %xmm0, %rax
+; X64-GENERIC-NEXT: shlq %rax
+; X64-GENERIC-NEXT: testq %rax, %rax
+; X64-GENERIC-NEXT: sete %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: iszero_d_strictfp:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movq %xmm0, %rax
+; X64-NDD-NEXT: shlq %rax
+; X64-NDD-NEXT: testq %rax, %rax
+; X64-NDD-NEXT: setzue %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 96) strictfp ; 0x60 = "zero"
ret i1 %0
@@ -1429,11 +1872,17 @@ define <1 x i1> @isnan_v1f(<1 x float> %x) {
; X86-NEXT: setp %al
; X86-NEXT: retl
;
-; X64-LABEL: isnan_v1f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: ucomiss %xmm0, %xmm0
-; X64-NEXT: setp %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: isnan_v1f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: ucomiss %xmm0, %xmm0
+; X64-GENERIC-NEXT: setp %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: isnan_v1f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: ucomiss %xmm0, %xmm0
+; X64-NDD-NEXT: setzup %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call <1 x i1> @llvm.is.fpclass.v1f32(<1 x float> %x, i32 3) ; "nan"
ret <1 x i1> %0
@@ -1448,13 +1897,21 @@ define <1 x i1> @isnan_v1f_strictfp(<1 x float> %x) strictfp {
; X86-NEXT: setge %al
; X86-NEXT: retl
;
-; X64-LABEL: isnan_v1f_strictfp:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-NEXT: setge %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: isnan_v1f_strictfp:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-GENERIC-NEXT: setge %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: isnan_v1f_strictfp:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-NDD-NEXT: setzuge %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call <1 x i1> @llvm.is.fpclass.v1f32(<1 x float> %x, i32 3) strictfp ; "nan"
ret <1 x i1> %0
@@ -1675,12 +2132,19 @@ define i1 @iszero_or_nan_f(float %x) {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-LABEL: iszero_or_nan_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: xorps %xmm1, %xmm1
-; X64-NEXT: ucomiss %xmm1, %xmm0
-; X64-NEXT: sete %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: iszero_or_nan_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: xorps %xmm1, %xmm1
+; X64-GENERIC-NEXT: ucomiss %xmm1, %xmm0
+; X64-GENERIC-NEXT: sete %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: iszero_or_nan_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: xorps %xmm1, %xmm1
+; X64-NDD-NEXT: ucomiss %xmm1, %xmm0
+; X64-NDD-NEXT: setzue %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 99) ; 0x60|0x3 = "zero|nan"
ret i1 %0
@@ -1698,16 +2162,27 @@ define i1 @iszero_or_nan_f_daz(float %x) #0 {
; X86-NEXT: orb %cl, %al
; X86-NEXT: retl
;
-; X64-LABEL: iszero_or_nan_f_daz:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-NEXT: setge %cl
-; X64-NEXT: testl %eax, %eax
-; X64-NEXT: sete %al
-; X64-NEXT: orb %cl, %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: iszero_or_nan_f_daz:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-GENERIC-NEXT: setge %cl
+; X64-GENERIC-NEXT: testl %eax, %eax
+; X64-GENERIC-NEXT: sete %al
+; X64-GENERIC-NEXT: orb %cl, %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: iszero_or_nan_f_daz:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-NDD-NEXT: setzuge %cl
+; X64-NDD-NEXT: testl %eax, %eax
+; X64-NDD-NEXT: setzue %al
+; X64-NDD-NEXT: orb %cl, %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 99) ; 0x60|0x3 = "zero|nan"
ret i1 %0
@@ -1725,16 +2200,27 @@ define i1 @iszero_or_nan_f_maybe_daz(float %x) #1 {
; X86-NEXT: orb %cl, %al
; X86-NEXT: retl
;
-; X64-LABEL: iszero_or_nan_f_maybe_daz:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-NEXT: setge %cl
-; X64-NEXT: testl %eax, %eax
-; X64-NEXT: sete %al
-; X64-NEXT: orb %cl, %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: iszero_or_nan_f_maybe_daz:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-GENERIC-NEXT: setge %cl
+; X64-GENERIC-NEXT: testl %eax, %eax
+; X64-GENERIC-NEXT: sete %al
+; X64-GENERIC-NEXT: orb %cl, %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: iszero_or_nan_f_maybe_daz:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-NDD-NEXT: setzuge %cl
+; X64-NDD-NEXT: testl %eax, %eax
+; X64-NDD-NEXT: setzue %al
+; X64-NDD-NEXT: orb %cl, %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 99) ; 0x60|0x3 = "zero|nan"
ret i1 %0
@@ -1752,12 +2238,19 @@ define i1 @not_iszero_or_nan_f(float %x) {
; X86-NEXT: setne %al
; X86-NEXT: retl
;
-; X64-LABEL: not_iszero_or_nan_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: xorps %xmm1, %xmm1
-; X64-NEXT: ucomiss %xmm1, %xmm0
-; X64-NEXT: setne %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_iszero_or_nan_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: xorps %xmm1, %xmm1
+; X64-GENERIC-NEXT: ucomiss %xmm1, %xmm0
+; X64-GENERIC-NEXT: setne %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: not_iszero_or_nan_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: xorps %xmm1, %xmm1
+; X64-NDD-NEXT: ucomiss %xmm1, %xmm0
+; X64-NDD-NEXT: setzune %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 924) ; ~0x60 = "~(zero|nan)"
ret i1 %0
@@ -1775,16 +2268,27 @@ define i1 @not_iszero_or_nan_f_daz(float %x) #0 {
; X86-NEXT: andb %cl, %al
; X86-NEXT: retl
;
-; X64-LABEL: not_iszero_or_nan_f_daz:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-NEXT: setl %cl
-; X64-NEXT: testl %eax, %eax
-; X64-NEXT: setne %al
-; X64-NEXT: andb %cl, %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_iszero_or_nan_f_daz:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-GENERIC-NEXT: setl %cl
+; X64-GENERIC-NEXT: testl %eax, %eax
+; X64-GENERIC-NEXT: setne %al
+; X64-GENERIC-NEXT: andb %cl, %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: not_iszero_or_nan_f_daz:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-NDD-NEXT: setzul %cl
+; X64-NDD-NEXT: testl %eax, %eax
+; X64-NDD-NEXT: setzune %al
+; X64-NDD-NEXT: andb %cl, %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 924) ; ~(0x60|0x3) = "~(zero|nan)"
ret i1 %0
@@ -1802,16 +2306,27 @@ define i1 @not_iszero_or_nan_f_maybe_daz(float %x) #1 {
; X86-NEXT: andb %cl, %al
; X86-NEXT: retl
;
-; X64-LABEL: not_iszero_or_nan_f_maybe_daz:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-NEXT: setl %cl
-; X64-NEXT: testl %eax, %eax
-; X64-NEXT: setne %al
-; X64-NEXT: andb %cl, %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_iszero_or_nan_f_maybe_daz:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-GENERIC-NEXT: setl %cl
+; X64-GENERIC-NEXT: testl %eax, %eax
+; X64-GENERIC-NEXT: setne %al
+; X64-GENERIC-NEXT: andb %cl, %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: not_iszero_or_nan_f_maybe_daz:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-NDD-NEXT: setzul %cl
+; X64-NDD-NEXT: testl %eax, %eax
+; X64-NDD-NEXT: setzune %al
+; X64-NDD-NEXT: andb %cl, %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 924) ; ~(0x60|0x3) = "~(zero|nan)"
ret i1 %0
@@ -1829,16 +2344,27 @@ define i1 @iszero_or_qnan_f(float %x) {
; X86-NEXT: orb %cl, %al
; X86-NEXT: retl
;
-; X64-LABEL: iszero_or_qnan_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NEXT: setge %cl
-; X64-NEXT: testl %eax, %eax
-; X64-NEXT: sete %al
-; X64-NEXT: orb %cl, %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: iszero_or_qnan_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-GENERIC-NEXT: setge %cl
+; X64-GENERIC-NEXT: testl %eax, %eax
+; X64-GENERIC-NEXT: sete %al
+; X64-GENERIC-NEXT: orb %cl, %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: iszero_or_qnan_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-NDD-NEXT: setzuge %cl
+; X64-NDD-NEXT: testl %eax, %eax
+; X64-NDD-NEXT: setzue %al
+; X64-NDD-NEXT: orb %cl, %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 98) ; 0x60|0x2 = "zero|qnan"
ret i1 %0
@@ -1878,12 +2404,12 @@ define i1 @iszero_or_snan_f(float %x) {
; X64-NDD-NEXT: movd %xmm0, %eax
; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
; X64-NDD-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NDD-NEXT: setl %cl
+; X64-NDD-NEXT: setzul %cl
; X64-NDD-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-NDD-NEXT: setge %dl
+; X64-NDD-NEXT: setzuge %dl
; X64-NDD-NEXT: andb %dl, %cl
; X64-NDD-NEXT: testl %eax, %eax
-; X64-NDD-NEXT: sete %al
+; X64-NDD-NEXT: setzue %al
; X64-NDD-NEXT: orb %cl, %al
; X64-NDD-NEXT: retq
entry:
@@ -1946,19 +2472,19 @@ define i1 @not_iszero_or_qnan_f(float %x) {
; X64-NDD-NEXT: movd %xmm0, %eax
; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
; X64-NDD-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NDD-NEXT: setl %cl
+; X64-NDD-NEXT: setzul %cl
; X64-NDD-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-NDD-NEXT: setge %dl
+; X64-NDD-NEXT: setzuge %dl
; X64-NDD-NEXT: andb %dl, %cl
; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: sete %dl
+; X64-NDD-NEXT: setzue %dl
; X64-NDD-NEXT: decl %eax, %esi
; X64-NDD-NEXT: cmpl $8388607, %esi # imm = 0x7FFFFF
-; X64-NDD-NEXT: setb %sil
+; X64-NDD-NEXT: setzub %sil
; X64-NDD-NEXT: orb %sil, %dl
; X64-NDD-NEXT: addl $-8388608, %eax # imm = 0xFF800000
; X64-NDD-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; X64-NDD-NEXT: setb %al
+; X64-NDD-NEXT: setzub %al
; X64-NDD-NEXT: orb %cl, %al
; X64-NDD-NEXT: orb %dl, %al
; X64-NDD-NEXT: retq
@@ -2011,17 +2537,17 @@ define i1 @not_iszero_or_snan_f(float %x) {
; X64-NDD-NEXT: movd %xmm0, %eax
; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: sete %cl
+; X64-NDD-NEXT: setzue %cl
; X64-NDD-NEXT: decl %eax, %edx
; X64-NDD-NEXT: cmpl $8388607, %edx # imm = 0x7FFFFF
-; X64-NDD-NEXT: setb %dl
+; X64-NDD-NEXT: setzub %dl
; X64-NDD-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NDD-NEXT: setge %sil
+; X64-NDD-NEXT: setzuge %sil
; X64-NDD-NEXT: orb %sil, %cl
; X64-NDD-NEXT: orb %dl, %cl
; X64-NDD-NEXT: addl $-8388608, %eax # imm = 0xFF800000
; X64-NDD-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; X64-NDD-NEXT: setb %al
+; X64-NDD-NEXT: setzub %al
; X64-NDD-NEXT: orb %cl, %al
; X64-NDD-NEXT: retq
entry:
@@ -2038,13 +2564,21 @@ define i1 @isinf_or_nan_f(float %x) {
; X86-NEXT: setge %al
; X86-NEXT: retl
;
-; X64-LABEL: isinf_or_nan_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: setge %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: isinf_or_nan_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: setge %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: isinf_or_nan_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NDD-NEXT: setzuge %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 519) ; 0x204|0x3 = "inf|nan"
ret i1 %0
@@ -2059,13 +2593,21 @@ define i1 @not_isinf_or_nan_f(float %x) {
; X86-NEXT: setl %al
; X86-NEXT: retl
;
-; X64-LABEL: not_isinf_or_nan_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: setl %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_isinf_or_nan_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: setl %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: not_isinf_or_nan_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NDD-NEXT: setzul %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 504) ; ~(0x204|0x3) = "~(inf|nan)"
ret i1 %0
@@ -2080,13 +2622,21 @@ define i1 @isfinite_or_nan_f(float %x) {
; X86-NEXT: setne %al
; X86-NEXT: retl
;
-; X64-LABEL: isfinite_or_nan_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: setne %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: isfinite_or_nan_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: setne %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: isfinite_or_nan_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NDD-NEXT: setzune %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 507) ; 0x1f8|0x3 = "finite|nan"
ret i1 %0
@@ -2101,13 +2651,21 @@ define i1 @not_isfinite_or_nan_f(float %x) {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-LABEL: not_isfinite_or_nan_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: sete %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_isfinite_or_nan_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: sete %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: not_isfinite_or_nan_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NDD-NEXT: setzue %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 516) ; ~(0x1f8|0x3) = "~(finite|nan)"
ret i1 %0
@@ -2125,11 +2683,17 @@ define i1 @is_plus_inf_or_nan_f(float %x) {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-LABEL: is_plus_inf_or_nan_f:
-; X64: # %bb.0:
-; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; X64-NEXT: sete %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: is_plus_inf_or_nan_f:
+; X64-GENERIC: # %bb.0:
+; X64-GENERIC-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-GENERIC-NEXT: sete %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: is_plus_inf_or_nan_f:
+; X64-NDD: # %bb.0:
+; X64-NDD-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-NDD-NEXT: setzue %al
+; X64-NDD-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 515) ; 0x200|0x3 = "+inf|nan"
ret i1 %class
}
@@ -2146,11 +2710,17 @@ define i1 @is_minus_inf_or_nan_f(float %x) {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-LABEL: is_minus_inf_or_nan_f:
-; X64: # %bb.0:
-; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; X64-NEXT: sete %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: is_minus_inf_or_nan_f:
+; X64-GENERIC: # %bb.0:
+; X64-GENERIC-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-GENERIC-NEXT: sete %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: is_minus_inf_or_nan_f:
+; X64-NDD: # %bb.0:
+; X64-NDD-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-NDD-NEXT: setzue %al
+; X64-NDD-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 7) ; "-inf|nan"
ret i1 %class
}
@@ -2167,11 +2737,17 @@ define i1 @not_is_plus_inf_or_nan_f(float %x) {
; X86-NEXT: setne %al
; X86-NEXT: retl
;
-; X64-LABEL: not_is_plus_inf_or_nan_f:
-; X64: # %bb.0:
-; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; X64-NEXT: setne %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_is_plus_inf_or_nan_f:
+; X64-GENERIC: # %bb.0:
+; X64-GENERIC-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-GENERIC-NEXT: setne %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: not_is_plus_inf_or_nan_f:
+; X64-NDD: # %bb.0:
+; X64-NDD-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-NDD-NEXT: setzune %al
+; X64-NDD-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 508) ; ~(0x200|0x3) = "~(+inf|nan)"
ret i1 %class
}
@@ -2188,11 +2764,17 @@ define i1 @not_is_minus_inf_or_nan_f(float %x) {
; X86-NEXT: setne %al
; X86-NEXT: retl
;
-; X64-LABEL: not_is_minus_inf_or_nan_f:
-; X64: # %bb.0:
-; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; X64-NEXT: setne %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_is_minus_inf_or_nan_f:
+; X64-GENERIC: # %bb.0:
+; X64-GENERIC-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-GENERIC-NEXT: setne %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: not_is_minus_inf_or_nan_f:
+; X64-NDD: # %bb.0:
+; X64-NDD-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-NDD-NEXT: setzune %al
+; X64-NDD-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1016) ; "~(-inf|nan)"
ret i1 %class
}
@@ -2233,12 +2815,12 @@ define i1 @is_plus_inf_or_snan_f(float %x) {
; X64-NDD-NEXT: movd %xmm0, %eax
; X64-NDD-NEXT: andl $2147483647, %eax, %ecx # imm = 0x7FFFFFFF
; X64-NDD-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
-; X64-NDD-NEXT: setl %dl
+; X64-NDD-NEXT: setzul %dl
; X64-NDD-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
-; X64-NDD-NEXT: setge %cl
+; X64-NDD-NEXT: setzuge %cl
; X64-NDD-NEXT: andb %dl, %cl
; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: sete %al
+; X64-NDD-NEXT: setzue %al
; X64-NDD-NEXT: orb %cl, %al
; X64-NDD-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 513) ; 0x200|0x1 = "+inf|snan"
@@ -2257,16 +2839,27 @@ define i1 @is_plus_inf_or_qnan_f(float %x) {
; X86-NEXT: orb %cl, %al
; X86-NEXT: retl
;
-; X64-LABEL: is_plus_inf_or_qnan_f:
-; X64: # %bb.0:
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: sete %cl
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NEXT: setge %al
-; X64-NEXT: orb %cl, %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: is_plus_inf_or_qnan_f:
+; X64-GENERIC: # %bb.0:
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: sete %cl
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-GENERIC-NEXT: setge %al
+; X64-GENERIC-NEXT: orb %cl, %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: is_plus_inf_or_qnan_f:
+; X64-NDD: # %bb.0:
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NDD-NEXT: setzue %cl
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-NDD-NEXT: setzuge %al
+; X64-NDD-NEXT: orb %cl, %al
+; X64-NDD-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 514) ; 0x200|0x1 = "+inf|qnan"
ret i1 %class
}
@@ -2304,13 +2897,13 @@ define i1 @not_is_plus_inf_or_snan_f(float %x) {
; X64-NDD: # %bb.0:
; X64-NDD-NEXT: movd %xmm0, %eax
; X64-NDD-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
-; X64-NDD-NEXT: sete %cl
+; X64-NDD-NEXT: setzue %cl
; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setl %dl
+; X64-NDD-NEXT: setzul %dl
; X64-NDD-NEXT: orb %dl, %cl
; X64-NDD-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NDD-NEXT: setge %al
+; X64-NDD-NEXT: setzuge %al
; X64-NDD-NEXT: orb %cl, %al
; X64-NDD-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 510) ; ~(+inf|snan)
@@ -2359,14 +2952,14 @@ define i1 @not_is_plus_inf_or_qnan_f(float %x) {
; X64-NDD-NEXT: movd %xmm0, %eax
; X64-NDD-NEXT: andl $2147483647, %eax, %ecx # imm = 0x7FFFFFFF
; X64-NDD-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
-; X64-NDD-NEXT: setl %dl
+; X64-NDD-NEXT: setzul %dl
; X64-NDD-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
-; X64-NDD-NEXT: setge %sil
+; X64-NDD-NEXT: setzuge %sil
; X64-NDD-NEXT: andb %sil, %dl
; X64-NDD-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
-; X64-NDD-NEXT: sete %al
+; X64-NDD-NEXT: setzue %al
; X64-NDD-NEXT: cmpl $2139095040, %ecx # imm = 0x7F800000
-; X64-NDD-NEXT: setl %cl
+; X64-NDD-NEXT: setzul %cl
; X64-NDD-NEXT: orb %cl, %al
; X64-NDD-NEXT: orb %dl, %al
; X64-NDD-NEXT: retq
@@ -2410,12 +3003,12 @@ define i1 @is_minus_inf_or_snan_f(float %x) {
; X64-NDD-NEXT: movd %xmm0, %eax
; X64-NDD-NEXT: andl $2147483647, %eax, %ecx # imm = 0x7FFFFFFF
; X64-NDD-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
-; X64-NDD-NEXT: setl %dl
+; X64-NDD-NEXT: setzul %dl
; X64-NDD-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
-; X64-NDD-NEXT: setge %cl
+; X64-NDD-NEXT: setzuge %cl
; X64-NDD-NEXT: andb %dl, %cl
; X64-NDD-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
-; X64-NDD-NEXT: sete %al
+; X64-NDD-NEXT: setzue %al
; X64-NDD-NEXT: orb %cl, %al
; X64-NDD-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 5) ; "-inf|snan"
@@ -2434,16 +3027,27 @@ define i1 @is_minus_inf_or_qnan_f(float %x) {
; X86-NEXT: orb %cl, %al
; X86-NEXT: retl
;
-; X64-LABEL: is_minus_inf_or_qnan_f:
-; X64: # %bb.0:
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
-; X64-NEXT: sete %cl
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NEXT: setge %al
-; X64-NEXT: orb %cl, %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: is_minus_inf_or_qnan_f:
+; X64-GENERIC: # %bb.0:
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
+; X64-GENERIC-NEXT: sete %cl
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-GENERIC-NEXT: setge %al
+; X64-GENERIC-NEXT: orb %cl, %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: is_minus_inf_or_qnan_f:
+; X64-NDD: # %bb.0:
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
+; X64-NDD-NEXT: setzue %cl
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-NDD-NEXT: setzuge %al
+; X64-NDD-NEXT: orb %cl, %al
+; X64-NDD-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 6) ; "-inf|qnan"
ret i1 %class
}
@@ -2481,13 +3085,13 @@ define i1 @not_is_minus_inf_or_snan_f(float %x) {
; X64-NDD: # %bb.0:
; X64-NDD-NEXT: movd %xmm0, %eax
; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: sete %cl
+; X64-NDD-NEXT: setzue %cl
; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setl %dl
+; X64-NDD-NEXT: setzul %dl
; X64-NDD-NEXT: orb %dl, %cl
; X64-NDD-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NDD-NEXT: setge %al
+; X64-NDD-NEXT: setzuge %al
; X64-NDD-NEXT: orb %cl, %al
; X64-NDD-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1018) ; "~(-inf|snan)"
@@ -2536,14 +3140,14 @@ define i1 @not_is_minus_inf_or_qnan_f(float %x) {
; X64-NDD-NEXT: movd %xmm0, %eax
; X64-NDD-NEXT: andl $2147483647, %eax, %ecx # imm = 0x7FFFFFFF
; X64-NDD-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
-; X64-NDD-NEXT: setl %dl
+; X64-NDD-NEXT: setzul %dl
; X64-NDD-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
-; X64-NDD-NEXT: setge %sil
+; X64-NDD-NEXT: setzuge %sil
; X64-NDD-NEXT: andb %sil, %dl
; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: sete %al
+; X64-NDD-NEXT: setzue %al
; X64-NDD-NEXT: cmpl $2139095040, %ecx # imm = 0x7F800000
-; X64-NDD-NEXT: setl %cl
+; X64-NDD-NEXT: setzul %cl
; X64-NDD-NEXT: orb %cl, %al
; X64-NDD-NEXT: orb %dl, %al
; X64-NDD-NEXT: retq
@@ -2564,17 +3168,29 @@ define i1 @issubnormal_or_nan_f(float %x) {
; X86-NEXT: orb %cl, %al
; X86-NEXT: retl
;
-; X64-LABEL: issubnormal_or_nan_f:
-; X64: # %bb.0:
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-NEXT: setge %cl
-; X64-NEXT: decl %eax
-; X64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
-; X64-NEXT: setb %al
-; X64-NEXT: orb %cl, %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: issubnormal_or_nan_f:
+; X64-GENERIC: # %bb.0:
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-GENERIC-NEXT: setge %cl
+; X64-GENERIC-NEXT: decl %eax
+; X64-GENERIC-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-GENERIC-NEXT: setb %al
+; X64-GENERIC-NEXT: orb %cl, %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: issubnormal_or_nan_f:
+; X64-NDD: # %bb.0:
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-NDD-NEXT: setzuge %cl
+; X64-NDD-NEXT: decl %eax
+; X64-NDD-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-NDD-NEXT: setzub %al
+; X64-NDD-NEXT: orb %cl, %al
+; X64-NDD-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 147) ; 0x90|0x3 = "subnormal|nan"
ret i1 %class
}
@@ -2593,12 +3209,19 @@ define i1 @issubnormal_or_zero_or_nan_f(float %x) {
; X86-NEXT: setb %al
; X86-NEXT: retl
;
-; X64-LABEL: issubnormal_or_zero_or_nan_f:
-; X64: # %bb.0:
-; X64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; X64-NEXT: setb %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: issubnormal_or_zero_or_nan_f:
+; X64-GENERIC: # %bb.0:
+; X64-GENERIC-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-GENERIC-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-GENERIC-NEXT: setb %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: issubnormal_or_zero_or_nan_f:
+; X64-NDD: # %bb.0:
+; X64-NDD-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-NDD-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-NDD-NEXT: setzub %al
+; X64-NDD-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 243) ; 0xf0|0x3 = "subnormal|zero|nan"
ret i1 %class
}
@@ -2615,12 +3238,19 @@ define i1 @issubnormal_or_zero_or_nan_f_daz(float %x) #0 {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-LABEL: issubnormal_or_zero_or_nan_f_daz:
-; X64: # %bb.0:
-; X64-NEXT: xorps %xmm1, %xmm1
-; X64-NEXT: ucomiss %xmm1, %xmm0
-; X64-NEXT: sete %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: issubnormal_or_zero_or_nan_f_daz:
+; X64-GENERIC: # %bb.0:
+; X64-GENERIC-NEXT: xorps %xmm1, %xmm1
+; X64-GENERIC-NEXT: ucomiss %xmm1, %xmm0
+; X64-GENERIC-NEXT: sete %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: issubnormal_or_zero_or_nan_f_daz:
+; X64-NDD: # %bb.0:
+; X64-NDD-NEXT: xorps %xmm1, %xmm1
+; X64-NDD-NEXT: ucomiss %xmm1, %xmm0
+; X64-NDD-NEXT: setzue %al
+; X64-NDD-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 243) ; 0xf0|0x3 = "subnormal|zero|nan"
ret i1 %class
}
@@ -2661,12 +3291,12 @@ define i1 @issubnormal_or_zero_or_snan_f(float %x) {
; X64-NDD-NEXT: movd %xmm0, %eax
; X64-NDD-NEXT: andl $2147483647, %eax, %ecx # imm = 0x7FFFFFFF
; X64-NDD-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
-; X64-NDD-NEXT: setl %dl
+; X64-NDD-NEXT: setzul %dl
; X64-NDD-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
-; X64-NDD-NEXT: setge %cl
+; X64-NDD-NEXT: setzuge %cl
; X64-NDD-NEXT: andb %dl, %cl
; X64-NDD-NEXT: testl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: sete %al
+; X64-NDD-NEXT: setzue %al
; X64-NDD-NEXT: orb %cl, %al
; X64-NDD-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 241) ; 0x90|0x1 = "subnormal|snan"
@@ -2685,16 +3315,27 @@ define i1 @issubnormal_or_zero_or_qnan_f(float %x) {
; X86-NEXT: orb %cl, %al
; X86-NEXT: retl
;
-; X64-LABEL: issubnormal_or_zero_or_qnan_f:
-; X64: # %bb.0:
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: testl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: sete %cl
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NEXT: setge %al
-; X64-NEXT: orb %cl, %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: issubnormal_or_zero_or_qnan_f:
+; X64-GENERIC: # %bb.0:
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: sete %cl
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-GENERIC-NEXT: setge %al
+; X64-GENERIC-NEXT: orb %cl, %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: issubnormal_or_zero_or_qnan_f:
+; X64-NDD: # %bb.0:
+; X64-NDD-NEXT: movd %xmm0, %eax
+; X64-NDD-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; X64-NDD-NEXT: setzue %cl
+; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NDD-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-NDD-NEXT: setzuge %al
+; X64-NDD-NEXT: orb %cl, %al
+; X64-NDD-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 242) ; 0x90|0x2 = "subnormal|qnan"
ret i1 %class
}
@@ -2735,13 +3376,13 @@ define i1 @not_issubnormal_or_nan_f(float %x) {
; X64-NDD-NEXT: movd %xmm0, %eax
; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: sete %cl
+; X64-NDD-NEXT: setzue %cl
; X64-NDD-NEXT: testl %eax, %eax
-; X64-NDD-NEXT: sete %dl
+; X64-NDD-NEXT: setzue %dl
; X64-NDD-NEXT: orb %dl, %cl
; X64-NDD-NEXT: addl $-8388608, %eax # imm = 0xFF800000
; X64-NDD-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; X64-NDD-NEXT: setb %al
+; X64-NDD-NEXT: setzub %al
; X64-NDD-NEXT: orb %cl, %al
; X64-NDD-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 876) ; ~(0x90|0x3) = ~"subnormal|nan"
@@ -2762,12 +3403,19 @@ define i1 @not_issubnormal_or_zero_or_nan_f(float %x) {
; X86-NEXT: setae %al
; X86-NEXT: retl
;
-; X64-LABEL: not_issubnormal_or_zero_or_nan_f:
-; X64: # %bb.0:
-; X64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; X64-NEXT: setae %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_issubnormal_or_zero_or_nan_f:
+; X64-GENERIC: # %bb.0:
+; X64-GENERIC-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-GENERIC-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-GENERIC-NEXT: setae %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: not_issubnormal_or_zero_or_nan_f:
+; X64-NDD: # %bb.0:
+; X64-NDD-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-NDD-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-NDD-NEXT: setzuae %al
+; X64-NDD-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 780) ; ~(0xf0|0x3) = ~"subnormal|zero|nan"
ret i1 %class
}
@@ -2784,12 +3432,19 @@ define i1 @not_issubnormal_or_zero_or_nan_f_daz(float %x) #0 {
; X86-NEXT: setne %al
; X86-NEXT: retl
;
-; X64-LABEL: not_issubnormal_or_zero_or_nan_f_daz:
-; X64: # %bb.0:
-; X64-NEXT: xorps %xmm1, %xmm1
-; X64-NEXT: ucomiss %xmm1, %xmm0
-; X64-NEXT: setne %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_issubnormal_or_zero_or_nan_f_daz:
+; X64-GENERIC: # %bb.0:
+; X64-GENERIC-NEXT: xorps %xmm1, %xmm1
+; X64-GENERIC-NEXT: ucomiss %xmm1, %xmm0
+; X64-GENERIC-NEXT: setne %al
+; X64-GENERIC-NEXT: retq
+;
+; X64-NDD-LABEL: not_issubnormal_or_zero_or_nan_f_daz:
+; X64-NDD: # %bb.0:
+; X64-NDD-NEXT: xorps %xmm1, %xmm1
+; X64-NDD-NEXT: ucomiss %xmm1, %xmm0
+; X64-NDD-NEXT: setzune %al
+; X64-NDD-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 780) ; ~(0xf0|0x3) = ~"subnormal|zero|nan"
ret i1 %class
}
@@ -2830,13 +3485,13 @@ define i1 @not_issubnormal_or_zero_or_snan_f(float %x) {
; X64-NDD-NEXT: movd %xmm0, %eax
; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
; X64-NDD-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NDD-NEXT: setge %cl
+; X64-NDD-NEXT: setzuge %cl
; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: sete %dl
+; X64-NDD-NEXT: setzue %dl
; X64-NDD-NEXT: orb %dl, %cl
; X64-NDD-NEXT: addl $-8388608, %eax # imm = 0xFF800000
; X64-NDD-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; X64-NDD-NEXT: setb %al
+; X64-NDD-NEXT: setzub %al
; X64-NDD-NEXT: orb %cl, %al
; X64-NDD-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 782) ; ~(0x90|0x1) = ~"subnormal|snan"
@@ -2885,16 +3540,16 @@ define i1 @not_issubnormal_or_zero_or_qnan_f(float %x) {
; X64-NDD-NEXT: movd %xmm0, %eax
; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
; X64-NDD-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NDD-NEXT: setl %cl
+; X64-NDD-NEXT: setzul %cl
; X64-NDD-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-NDD-NEXT: setge %dl
+; X64-NDD-NEXT: setzuge %dl
; X64-NDD-NEXT: andb %dl, %cl
; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: sete %dl
+; X64-NDD-NEXT: setzue %dl
; X64-NDD-NEXT: orb %dl, %cl
; X64-NDD-NEXT: addl $-8388608, %eax # imm = 0xFF800000
; X64-NDD-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; X64-NDD-NEXT: setb %al
+; X64-NDD-NEXT: setzub %al
; X64-NDD-NEXT: orb %cl, %al
; X64-NDD-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 781) ; ~(0x90|0x2) = ~"subnormal|qnan"
diff --git a/llvm/test/CodeGen/X86/select_const_i128.ll b/llvm/test/CodeGen/X86/select_const_i128.ll
index f0f0c584a7fc8..a464a1048d145 100644
--- a/llvm/test/CodeGen/X86/select_const_i128.ll
+++ b/llvm/test/CodeGen/X86/select_const_i128.ll
@@ -1,6 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v2 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v2 -mattr=+ndd | FileCheck --check-prefix=NDD %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v2 -mattr=+ndd,+zu | FileCheck --check-prefix=NDD-ZU %s
define i128 @select_eq_i128(ptr %a) {
; CHECK-LABEL: select_eq_i128:
@@ -19,13 +20,24 @@ define i128 @select_eq_i128(ptr %a) {
; NDD: # %bb.0:
; NDD-NEXT: movdqa (%rdi), %xmm0
; NDD-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; NDD-NEXT: xorl %eax, %eax
; NDD-NEXT: ptest %xmm0, %xmm0
-; NDD-NEXT: setne %al
+; NDD-NEXT: setzune %al
+; NDD-NEXT: movzbl %al, %eax
; NDD-NEXT: addq $-1, %rax
; NDD-NEXT: movabsq $9223372036854775807, %rdx # imm = 0x7FFFFFFFFFFFFFFF
; NDD-NEXT: adcq $0, %rdx
; NDD-NEXT: retq
+;
+; NDD-ZU-LABEL: select_eq_i128:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: movdqa (%rdi), %xmm0
+; NDD-ZU-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; NDD-ZU-NEXT: ptest %xmm0, %xmm0
+; NDD-ZU-NEXT: setzune %al
+; NDD-ZU-NEXT: addq $-1, %rax
+; NDD-ZU-NEXT: movabsq $9223372036854775807, %rdx # imm = 0x7FFFFFFFFFFFFFFF
+; NDD-ZU-NEXT: adcq $0, %rdx
+; NDD-ZU-NEXT: retq
%1 = load i128, ptr %a, align 16
%cmp = icmp eq i128 %1, 1
%cond = select i1 %cmp, i128 170141183460469231731687303715884105727, i128 -170141183460469231731687303715884105728
>From 46c148b93d8f0fe54015584e8d16569196ba61fd Mon Sep 17 00:00:00 2001
From: Feng Zou <feng.zou at intel.com>
Date: Sun, 1 Jun 2025 20:35:47 +0800
Subject: [PATCH 2/6] Emit SetZUCC in fast-isel
---
llvm/lib/Target/X86/X86FastISel.cpp | 33 +-
.../X86/2009-04-12-FastIselOverflowCrash.ll | 13 +
.../CodeGen/X86/apx/flags-copy-lowering.mir | 251 +++++
llvm/test/CodeGen/X86/cmp.ll | 884 ++++++++++++++++--
llvm/test/CodeGen/X86/fast-isel-fcmp.ll | 382 ++++++++
.../CodeGen/X86/fast-isel-select-cmov2.ll | 105 +++
llvm/test/CodeGen/X86/pr27591.ll | 25 +
llvm/test/CodeGen/X86/pr32284.ll | 183 ++++
llvm/test/CodeGen/X86/pr54369.ll | 23 +
9 files changed, 1799 insertions(+), 100 deletions(-)
diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp
index 0ff7f235ed392..282d32669d522 100644
--- a/llvm/lib/Target/X86/X86FastISel.cpp
+++ b/llvm/lib/Target/X86/X86FastISel.cpp
@@ -1503,10 +1503,12 @@ bool X86FastISel::X86SelectCmp(const Instruction *I) {
Register FlagReg1 = createResultReg(&X86::GR8RegClass);
Register FlagReg2 = createResultReg(&X86::GR8RegClass);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::SETCCr),
- FlagReg1).addImm(SETFOpc[0]);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::SETCCr),
- FlagReg2).addImm(SETFOpc[1]);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
+ TII.get(Subtarget->hasZU() ? X86::SETZUCCr : X86::SETCCr), FlagReg1)
+ .addImm(SETFOpc[0]);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
+ TII.get(Subtarget->hasZU() ? X86::SETZUCCr : X86::SETCCr), FlagReg2)
+ .addImm(SETFOpc[1]);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(SETFOpc[2]),
ResultReg).addReg(FlagReg1).addReg(FlagReg2);
updateValueMap(I, ResultReg);
@@ -1525,8 +1527,9 @@ bool X86FastISel::X86SelectCmp(const Instruction *I) {
if (!X86FastEmitCompare(LHS, RHS, VT, I->getDebugLoc()))
return false;
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::SETCCr),
- ResultReg).addImm(CC);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
+ TII.get(Subtarget->hasZU() ? X86::SETZUCCr : X86::SETCCr), ResultReg)
+ .addImm(CC);
updateValueMap(I, ResultReg);
return true;
}
@@ -2083,10 +2086,14 @@ bool X86FastISel::X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I) {
if (SETFOpc) {
Register FlagReg1 = createResultReg(&X86::GR8RegClass);
Register FlagReg2 = createResultReg(&X86::GR8RegClass);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::SETCCr),
- FlagReg1).addImm(SETFOpc[0]);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::SETCCr),
- FlagReg2).addImm(SETFOpc[1]);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
+ TII.get(Subtarget->hasZU() ? X86::SETZUCCr : X86::SETCCr),
+ FlagReg1)
+ .addImm(SETFOpc[0]);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
+ TII.get(Subtarget->hasZU() ? X86::SETZUCCr : X86::SETCCr),
+ FlagReg2)
+ .addImm(SETFOpc[1]);
auto const &II = TII.get(SETFOpc[2]);
if (II.getNumDefs()) {
Register TmpReg = createResultReg(&X86::GR8RegClass);
@@ -2989,8 +2996,10 @@ bool X86FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
// Assign to a GPR since the overflow return value is lowered to a SETcc.
Register ResultReg2 = createResultReg(&X86::GR8RegClass);
assert((ResultReg+1) == ResultReg2 && "Nonconsecutive result registers.");
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::SETCCr),
- ResultReg2).addImm(CondCode);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
+ TII.get(Subtarget->hasZU() ? X86::SETZUCCr : X86::SETCCr),
+ ResultReg2)
+ .addImm(CondCode);
updateValueMap(II, ResultReg, 2);
return true;
diff --git a/llvm/test/CodeGen/X86/2009-04-12-FastIselOverflowCrash.ll b/llvm/test/CodeGen/X86/2009-04-12-FastIselOverflowCrash.ll
index 94e1db3840b1c..ea2e90655a260 100644
--- a/llvm/test/CodeGen/X86/2009-04-12-FastIselOverflowCrash.ll
+++ b/llvm/test/CodeGen/X86/2009-04-12-FastIselOverflowCrash.ll
@@ -3,6 +3,8 @@
; RUN: llc < %s -fast-isel | FileCheck %s --check-prefix=FASTISEL
; PR30981
; RUN: llc < %s -O0 -mcpu=x86-64 -mattr=+avx512f | FileCheck %s --check-prefix=AVX512F
+; RUN: llc < %s -O0 -mcpu=x86-64 -mattr=+zu | FileCheck %s --check-prefix=ZU
+
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-apple-darwin10"
@@ -26,6 +28,17 @@ define fastcc i32 @test() nounwind {
; AVX512F-NEXT: LBB0_2: ## %.backedge
; AVX512F-NEXT: xorl %eax, %eax
; AVX512F-NEXT: retq
+;
+; ZU-LABEL: test:
+; ZU: ## %bb.0: ## %entry
+; ZU-NEXT: movl $1, %eax
+; ZU-NEXT: addl $0, %eax
+; ZU-NEXT: setzuo %al
+; ZU-NEXT: jo LBB0_2
+; ZU-NEXT: ## %bb.1: ## %BB3
+; ZU-NEXT: LBB0_2: ## %.backedge
+; ZU-NEXT: xorl %eax, %eax
+; ZU-NEXT: retq
entry:
%tmp1 = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 1, i32 0)
%tmp2 = extractvalue { i32, i1 } %tmp1, 1
diff --git a/llvm/test/CodeGen/X86/apx/flags-copy-lowering.mir b/llvm/test/CodeGen/X86/apx/flags-copy-lowering.mir
index 36f0e4d063991..a7db26ae51942 100644
--- a/llvm/test/CodeGen/X86/apx/flags-copy-lowering.mir
+++ b/llvm/test/CodeGen/X86/apx/flags-copy-lowering.mir
@@ -2,6 +2,7 @@
# RUN: llc -mtriple=x86_64 -run-pass x86-flags-copy-lowering -mattr=+ndd -verify-machineinstrs -o - %s | FileCheck --check-prefixes=NDD %s
# RUN: llc -mtriple=x86_64 -run-pass x86-flags-copy-lowering -mattr=+ndd,+nf -verify-machineinstrs -o - %s | FileCheck --check-prefixes=NDD-NF %s
# RUN: llc -mtriple=x86_64 -run-pass x86-flags-copy-lowering -mattr=+ndd,+nf,+zu -verify-machineinstrs -o - %s | FileCheck --check-prefixes=NDD-NF-ZU %s
+# RUN: llc -O0 -mtriple=x86_64 -run-pass x86-flags-copy-lowering -mattr=+ndd,+nf,+zu -verify-machineinstrs -o - %s | FileCheck --check-prefixes=O0-NDD-NF-ZU %s
# RUN: llc -mtriple=x86_64 -run-pass x86-flags-copy-lowering -mattr=+ndd,+nf -x86-enable-apx-for-relocation=true -verify-machineinstrs -o - %s | FileCheck --check-prefixes=NDD-NF %s
# Lower various interesting copy patterns of EFLAGS without using LAHF/SAHF.
@@ -54,6 +55,20 @@ body: |
; NDD-NF-ZU-NEXT: [[ADC64ri32_ND1:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADC64ri32_ND]], 42, implicit-def $eflags, implicit $eflags
; NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[ADC64ri32_ND1]]
; NDD-NF-ZU-NEXT: RET 0
+ ;
+ ; O0-NDD-NF-ZU-LABEL: name: test_adc
+ ; O0-NDD-NF-ZU: liveins: $rdi, $rsi
+ ; O0-NDD-NF-ZU-NEXT: {{ $}}
+ ; O0-NDD-NF-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; O0-NDD-NF-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; O0-NDD-NF-ZU-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; O0-NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; O0-NDD-NF-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr]], 255, implicit-def $eflags
+ ; O0-NDD-NF-ZU-NEXT: [[ADC64ri32_ND:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADD64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
+ ; O0-NDD-NF-ZU-NEXT: [[ADC64ri32_ND1:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADC64ri32_ND]], 42, implicit-def $eflags, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[ADC64ri32_ND1]]
+ ; O0-NDD-NF-ZU-NEXT: RET 0
%0:gr64 = COPY $rdi
%1:gr64 = COPY $rsi
%2:gr64 = ADD64rr_ND %0, %1, implicit-def $eflags
@@ -116,6 +131,20 @@ body: |
; NDD-NF-ZU-NEXT: [[SBB64ri32_ND1:%[0-9]+]]:gr64 = SBB64ri32_ND [[SBB64ri32_ND]], 42, implicit-def dead $eflags, implicit killed $eflags
; NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[SBB64ri32_ND1]]
; NDD-NF-ZU-NEXT: RET 0
+ ;
+ ; O0-NDD-NF-ZU-LABEL: name: test_sbb
+ ; O0-NDD-NF-ZU: liveins: $rdi, $rsi
+ ; O0-NDD-NF-ZU-NEXT: {{ $}}
+ ; O0-NDD-NF-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; O0-NDD-NF-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; O0-NDD-NF-ZU-NEXT: [[SUB64rr_ND:%[0-9]+]]:gr64 = SUB64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; O0-NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; O0-NDD-NF-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr]], 255, implicit-def $eflags
+ ; O0-NDD-NF-ZU-NEXT: [[SBB64ri32_ND:%[0-9]+]]:gr64 = SBB64ri32_ND [[SUB64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
+ ; O0-NDD-NF-ZU-NEXT: [[SBB64ri32_ND1:%[0-9]+]]:gr64 = SBB64ri32_ND [[SBB64ri32_ND]], 42, implicit-def dead $eflags, implicit killed $eflags
+ ; O0-NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[SBB64ri32_ND1]]
+ ; O0-NDD-NF-ZU-NEXT: RET 0
%0:gr64 = COPY $rdi
%1:gr64 = COPY $rsi
%2:gr64 = SUB64rr_ND %0, %1, implicit-def $eflags
@@ -178,6 +207,20 @@ body: |
; NDD-NF-ZU-NEXT: [[RCL64r1_ND1:%[0-9]+]]:gr64 = RCL64r1_ND [[RCL64r1_ND]], implicit-def $eflags, implicit $eflags
; NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCL64r1_ND1]]
; NDD-NF-ZU-NEXT: RET 0
+ ;
+ ; O0-NDD-NF-ZU-LABEL: name: test_rcl
+ ; O0-NDD-NF-ZU: liveins: $rdi, $rsi
+ ; O0-NDD-NF-ZU-NEXT: {{ $}}
+ ; O0-NDD-NF-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; O0-NDD-NF-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; O0-NDD-NF-ZU-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; O0-NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; O0-NDD-NF-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr]], 255, implicit-def $eflags
+ ; O0-NDD-NF-ZU-NEXT: [[RCL64r1_ND:%[0-9]+]]:gr64 = RCL64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
+ ; O0-NDD-NF-ZU-NEXT: [[RCL64r1_ND1:%[0-9]+]]:gr64 = RCL64r1_ND [[RCL64r1_ND]], implicit-def $eflags, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCL64r1_ND1]]
+ ; O0-NDD-NF-ZU-NEXT: RET 0
%0:gr64 = COPY $rdi
%1:gr64 = COPY $rsi
%2:gr64 = ADD64rr_ND %0, %1, implicit-def $eflags
@@ -240,6 +283,20 @@ body: |
; NDD-NF-ZU-NEXT: [[RCR64r1_ND1:%[0-9]+]]:gr64 = RCR64r1_ND [[RCR64r1_ND]], implicit-def $eflags, implicit $eflags
; NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCR64r1_ND1]]
; NDD-NF-ZU-NEXT: RET 0
+ ;
+ ; O0-NDD-NF-ZU-LABEL: name: test_rcr
+ ; O0-NDD-NF-ZU: liveins: $rdi, $rsi
+ ; O0-NDD-NF-ZU-NEXT: {{ $}}
+ ; O0-NDD-NF-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; O0-NDD-NF-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; O0-NDD-NF-ZU-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; O0-NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; O0-NDD-NF-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr]], 255, implicit-def $eflags
+ ; O0-NDD-NF-ZU-NEXT: [[RCR64r1_ND:%[0-9]+]]:gr64 = RCR64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
+ ; O0-NDD-NF-ZU-NEXT: [[RCR64r1_ND1:%[0-9]+]]:gr64 = RCR64r1_ND [[RCR64r1_ND]], implicit-def $eflags, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCR64r1_ND1]]
+ ; O0-NDD-NF-ZU-NEXT: RET 0
%0:gr64 = COPY $rdi
%1:gr64 = COPY $rsi
%2:gr64 = ADD64rr_ND %0, %1, implicit-def $eflags
@@ -332,6 +389,30 @@ body: |
; NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND2]]
; NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND3]]
; NDD-NF-ZU-NEXT: RET 0
+ ;
+ ; O0-NDD-NF-ZU-LABEL: name: test_cmov
+ ; O0-NDD-NF-ZU: liveins: $rdi, $rsi
+ ; O0-NDD-NF-ZU-NEXT: {{ $}}
+ ; O0-NDD-NF-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; O0-NDD-NF-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; O0-NDD-NF-ZU-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
+ ; O0-NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: [[SETZUCCr2:%[0-9]+]]:gr8 = SETZUCCr 4, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; O0-NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; O0-NDD-NF-ZU-NEXT: [[CMOV64rr_ND:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; O0-NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr1]], [[SETZUCCr1]], implicit-def $eflags
+ ; O0-NDD-NF-ZU-NEXT: [[CMOV64rr_ND1:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; O0-NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
+ ; O0-NDD-NF-ZU-NEXT: [[CMOV64rr_ND2:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; O0-NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
+ ; O0-NDD-NF-ZU-NEXT: [[CMOV64rr_ND3:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
+ ; O0-NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND]]
+ ; O0-NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND1]]
+ ; O0-NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND2]]
+ ; O0-NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND3]]
+ ; O0-NDD-NF-ZU-NEXT: RET 0
%0:gr64 = COPY $rdi
%1:gr64 = COPY $rsi
CMP64rr %0, %1, implicit-def $eflags
@@ -428,6 +509,30 @@ body: |
; NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND]]
; NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND1]]
; NDD-NF-ZU-NEXT: RET 0
+ ;
+ ; O0-NDD-NF-ZU-LABEL: name: test_cfcmov
+ ; O0-NDD-NF-ZU: liveins: $rdi, $rsi
+ ; O0-NDD-NF-ZU-NEXT: {{ $}}
+ ; O0-NDD-NF-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; O0-NDD-NF-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; O0-NDD-NF-ZU-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
+ ; O0-NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: [[SETZUCCr2:%[0-9]+]]:gr8 = SETZUCCr 4, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; O0-NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; O0-NDD-NF-ZU-NEXT: [[CFCMOV64rr:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
+ ; O0-NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr1]], [[SETZUCCr1]], implicit-def $eflags
+ ; O0-NDD-NF-ZU-NEXT: [[CFCMOV64rr1:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
+ ; O0-NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
+ ; O0-NDD-NF-ZU-NEXT: [[CFCMOV64rr_ND:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; O0-NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
+ ; O0-NDD-NF-ZU-NEXT: [[CFCMOV64rr_ND1:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
+ ; O0-NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr]]
+ ; O0-NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr1]]
+ ; O0-NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND]]
+ ; O0-NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND1]]
+ ; O0-NDD-NF-ZU-NEXT: RET 0
%0:gr64 = COPY $rdi
%1:gr64 = COPY $rsi
CMP64rr %0, %1, implicit-def $eflags
@@ -478,6 +583,14 @@ body: |
; NDD-NF-ZU-NEXT: [[ADD32rr_NF:%[0-9]+]]:gr32 = ADD32rr_NF $edi, $edi
; NDD-NF-ZU-NEXT: CCMP32rr [[ADD32rr_NF]], [[ADD32rr_NF]], 0, 1, implicit-def $eflags, implicit $eflags
; NDD-NF-ZU-NEXT: RET 0, $al
+ ;
+ ; O0-NDD-NF-ZU-LABEL: name: test_ccmp
+ ; O0-NDD-NF-ZU: liveins: $edi
+ ; O0-NDD-NF-ZU-NEXT: {{ $}}
+ ; O0-NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; O0-NDD-NF-ZU-NEXT: [[ADD32rr_NF:%[0-9]+]]:gr32 = ADD32rr_NF $edi, $edi
+ ; O0-NDD-NF-ZU-NEXT: CCMP32rr [[ADD32rr_NF]], [[ADD32rr_NF]], 0, 1, implicit-def $eflags, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: RET 0, $al
MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
%1:gr64 = COPY $eflags
%2:gr32 = ADD32rr $edi, $edi, implicit-def dead $eflags
@@ -517,6 +630,14 @@ body: |
; NDD-NF-ZU-NEXT: [[ADD32rr_NF:%[0-9]+]]:gr32 = ADD32rr_NF $edi, $edi
; NDD-NF-ZU-NEXT: CTEST32rr [[ADD32rr_NF]], [[ADD32rr_NF]], 0, 1, implicit-def $eflags, implicit $eflags
; NDD-NF-ZU-NEXT: RET 0, $al
+ ;
+ ; O0-NDD-NF-ZU-LABEL: name: test_ctest
+ ; O0-NDD-NF-ZU: liveins: $edi
+ ; O0-NDD-NF-ZU-NEXT: {{ $}}
+ ; O0-NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; O0-NDD-NF-ZU-NEXT: [[ADD32rr_NF:%[0-9]+]]:gr32 = ADD32rr_NF $edi, $edi
+ ; O0-NDD-NF-ZU-NEXT: CTEST32rr [[ADD32rr_NF]], [[ADD32rr_NF]], 0, 1, implicit-def $eflags, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: RET 0, $al
MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
%1:gr64 = COPY $eflags
%2:gr32 = ADD32rr $edi, $edi, implicit-def dead $eflags
@@ -556,6 +677,14 @@ body: |
; NDD-NF-ZU-NEXT: [[ADD32rr_NF_ND:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $edi
; NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND]], 7, implicit $eflags
; NDD-NF-ZU-NEXT: RET 0, $al
+ ;
+ ; O0-NDD-NF-ZU-LABEL: name: test_evitable_clobber
+ ; O0-NDD-NF-ZU: liveins: $edi
+ ; O0-NDD-NF-ZU-NEXT: {{ $}}
+ ; O0-NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; O0-NDD-NF-ZU-NEXT: [[ADD32rr_NF_ND:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $edi
+ ; O0-NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND]], 7, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: RET 0, $al
MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
%1:gr64 = COPY $eflags
%2:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
@@ -599,6 +728,16 @@ body: |
; NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
; NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
; NDD-NF-ZU-NEXT: RET 0, $al
+ ;
+ ; O0-NDD-NF-ZU-LABEL: name: test_inevitable_clobber
+ ; O0-NDD-NF-ZU: liveins: $edi
+ ; O0-NDD-NF-ZU-NEXT: {{ $}}
+ ; O0-NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; O0-NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; O0-NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
+ ; O0-NDD-NF-ZU-NEXT: RET 0, $al
MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
%1:gr64 = COPY $eflags
%2:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
@@ -645,6 +784,16 @@ body: |
; NDD-NF-ZU-NEXT: [[ADD32rr_NF_ND1:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $eax
; NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND1]], 9, implicit $eflags
; NDD-NF-ZU-NEXT: RET 0, $al
+ ;
+ ; O0-NDD-NF-ZU-LABEL: name: test_evitable_clobber_multiple_uses
+ ; O0-NDD-NF-ZU: liveins: $edi
+ ; O0-NDD-NF-ZU-NEXT: {{ $}}
+ ; O0-NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; O0-NDD-NF-ZU-NEXT: [[ADD32rr_NF_ND:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $edi
+ ; O0-NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND]], 7, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: [[ADD32rr_NF_ND1:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $eax
+ ; O0-NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND1]], 9, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: RET 0, $al
MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
%1:gr64 = COPY $eflags
%2:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
@@ -702,6 +851,19 @@ body: |
; NDD-NF-ZU-NEXT: [[ADD32rr_NF_ND:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $edi
; NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND]], 1, implicit $eflags
; NDD-NF-ZU-NEXT: RET 0, $al
+ ;
+ ; O0-NDD-NF-ZU-LABEL: name: test_mixed_clobber
+ ; O0-NDD-NF-ZU: liveins: $edi
+ ; O0-NDD-NF-ZU-NEXT: {{ $}}
+ ; O0-NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; O0-NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; O0-NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
+ ; O0-NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; O0-NDD-NF-ZU-NEXT: [[ADD32rr_NF_ND:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $edi
+ ; O0-NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND]], 1, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: RET 0, $al
MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
%1:gr64 = COPY $eflags
%2:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
@@ -769,6 +931,23 @@ body: |
; NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND]], 7, implicit $eflags
; NDD-NF-ZU-NEXT: $eax = ADC32rr_ND $eax, $edi, implicit-def dead $eflags, implicit $eflags
; NDD-NF-ZU-NEXT: RET 0, $al
+ ;
+ ; O0-NDD-NF-ZU-LABEL: name: test_evitable_clobber_crossbb
+ ; O0-NDD-NF-ZU: bb.0:
+ ; O0-NDD-NF-ZU-NEXT: successors: %bb.1(0x80000000)
+ ; O0-NDD-NF-ZU-NEXT: liveins: $edi
+ ; O0-NDD-NF-ZU-NEXT: {{ $}}
+ ; O0-NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; O0-NDD-NF-ZU-NEXT: [[ADD32rr_NF_ND:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $edi
+ ; O0-NDD-NF-ZU-NEXT: JCC_1 %bb.1, 4, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: RET 0, $al
+ ; O0-NDD-NF-ZU-NEXT: {{ $}}
+ ; O0-NDD-NF-ZU-NEXT: bb.1:
+ ; O0-NDD-NF-ZU-NEXT: liveins: $eflags
+ ; O0-NDD-NF-ZU-NEXT: {{ $}}
+ ; O0-NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND]], 7, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: $eax = ADC32rr_ND $eax, $edi, implicit-def dead $eflags, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: RET 0, $al
bb.0:
liveins: $edi
@@ -834,6 +1013,22 @@ body: |
; NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
; NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
; NDD-NF-ZU-NEXT: RET 0, $al
+ ;
+ ; O0-NDD-NF-ZU-LABEL: name: test_inevitable_clobber_crossbb
+ ; O0-NDD-NF-ZU: bb.0:
+ ; O0-NDD-NF-ZU-NEXT: successors: %bb.1(0x80000000)
+ ; O0-NDD-NF-ZU-NEXT: liveins: $edi
+ ; O0-NDD-NF-ZU-NEXT: {{ $}}
+ ; O0-NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; O0-NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: JCC_1 %bb.1, 4, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: RET 0, $al
+ ; O0-NDD-NF-ZU-NEXT: {{ $}}
+ ; O0-NDD-NF-ZU-NEXT: bb.1:
+ ; O0-NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; O0-NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
+ ; O0-NDD-NF-ZU-NEXT: RET 0, $al
bb.0:
liveins: $edi
@@ -935,6 +1130,35 @@ body: |
; NDD-NF-ZU-NEXT: {{ $}}
; NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[SUB32rr_NF_ND]], 7, implicit $eflags
; NDD-NF-ZU-NEXT: RET 0, $al
+ ;
+ ; O0-NDD-NF-ZU-LABEL: name: test_evitable_clobber_crossbb_complex
+ ; O0-NDD-NF-ZU: bb.0:
+ ; O0-NDD-NF-ZU-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; O0-NDD-NF-ZU-NEXT: liveins: $edi
+ ; O0-NDD-NF-ZU-NEXT: {{ $}}
+ ; O0-NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; O0-NDD-NF-ZU-NEXT: [[SUB32rr_NF_ND:%[0-9]+]]:gr32 = SUB32rr_NF_ND $edi, $edi
+ ; O0-NDD-NF-ZU-NEXT: JCC_1 %bb.2, 4, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: {{ $}}
+ ; O0-NDD-NF-ZU-NEXT: bb.1:
+ ; O0-NDD-NF-ZU-NEXT: successors: %bb.3(0x80000000)
+ ; O0-NDD-NF-ZU-NEXT: liveins: $eflags
+ ; O0-NDD-NF-ZU-NEXT: {{ $}}
+ ; O0-NDD-NF-ZU-NEXT: $eax = IMUL32rr_NF_ND $eax, $edi
+ ; O0-NDD-NF-ZU-NEXT: JMP_1 %bb.3
+ ; O0-NDD-NF-ZU-NEXT: {{ $}}
+ ; O0-NDD-NF-ZU-NEXT: bb.2:
+ ; O0-NDD-NF-ZU-NEXT: successors: %bb.3(0x80000000)
+ ; O0-NDD-NF-ZU-NEXT: liveins: $eflags
+ ; O0-NDD-NF-ZU-NEXT: {{ $}}
+ ; O0-NDD-NF-ZU-NEXT: $eax = IMUL32rr_NF $eax, $esi
+ ; O0-NDD-NF-ZU-NEXT: JMP_1 %bb.3
+ ; O0-NDD-NF-ZU-NEXT: {{ $}}
+ ; O0-NDD-NF-ZU-NEXT: bb.3:
+ ; O0-NDD-NF-ZU-NEXT: liveins: $eflags
+ ; O0-NDD-NF-ZU-NEXT: {{ $}}
+ ; O0-NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[SUB32rr_NF_ND]], 7, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: RET 0, $al
bb.0:
liveins: $edi
@@ -1039,6 +1263,33 @@ body: |
; NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
; NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[SUB32rr_ND]], 5, implicit killed $eflags
; NDD-NF-ZU-NEXT: RET 0, $al
+ ;
+ ; O0-NDD-NF-ZU-LABEL: name: test_inevitable_clobber_crossbb_complex
+ ; O0-NDD-NF-ZU: bb.0:
+ ; O0-NDD-NF-ZU-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; O0-NDD-NF-ZU-NEXT: liveins: $edi
+ ; O0-NDD-NF-ZU-NEXT: {{ $}}
+ ; O0-NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; O0-NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: [[SUB32rr_ND:%[0-9]+]]:gr32 = SUB32rr_ND $edi, $edi, implicit-def dead $eflags
+ ; O0-NDD-NF-ZU-NEXT: JCC_1 %bb.2, 4, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: {{ $}}
+ ; O0-NDD-NF-ZU-NEXT: bb.1:
+ ; O0-NDD-NF-ZU-NEXT: successors: %bb.3(0x80000000)
+ ; O0-NDD-NF-ZU-NEXT: {{ $}}
+ ; O0-NDD-NF-ZU-NEXT: $eax = IMUL32rr_ND $eax, $edi, implicit-def dead $eflags
+ ; O0-NDD-NF-ZU-NEXT: JMP_1 %bb.3
+ ; O0-NDD-NF-ZU-NEXT: {{ $}}
+ ; O0-NDD-NF-ZU-NEXT: bb.2:
+ ; O0-NDD-NF-ZU-NEXT: successors: %bb.3(0x80000000)
+ ; O0-NDD-NF-ZU-NEXT: {{ $}}
+ ; O0-NDD-NF-ZU-NEXT: $eax = SBB32rr $eax, $esi, implicit-def dead $eflags, implicit $eflags
+ ; O0-NDD-NF-ZU-NEXT: JMP_1 %bb.3
+ ; O0-NDD-NF-ZU-NEXT: {{ $}}
+ ; O0-NDD-NF-ZU-NEXT: bb.3:
+ ; O0-NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; O0-NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[SUB32rr_ND]], 5, implicit killed $eflags
+ ; O0-NDD-NF-ZU-NEXT: RET 0, $al
bb.0:
liveins: $edi
diff --git a/llvm/test/CodeGen/X86/cmp.ll b/llvm/test/CodeGen/X86/cmp.ll
index 887c59c7a4198..64dd19ca42c50 100644
--- a/llvm/test/CodeGen/X86/cmp.ll
+++ b/llvm/test/CodeGen/X86/cmp.ll
@@ -2,6 +2,7 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,NO-NDD
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ndd -show-mc-encoding | FileCheck --check-prefixes=CHECK,NDD %s
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ndd,+zu -show-mc-encoding | FileCheck --check-prefixes=CHECK,NDD-ZU %s
+; RUN: llc -O0 < %s -mtriple=x86_64-unknown-unknown -mattr=+ndd,+zu -show-mc-encoding | FileCheck --check-prefixes=CHECK,O0-NDD-ZU %s
@d = dso_local global i8 0, align 1
@d64 = dso_local global i64 0
@@ -31,18 +32,57 @@ ReturnBlock:
}
define i32 @test2(i32 %X, ptr %y) nounwind {
-; CHECK-LABEL: test2:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: testl $536870911, (%rsi) # encoding: [0xf7,0x06,0xff,0xff,0xff,0x1f]
-; CHECK-NEXT: # imm = 0x1FFFFFFF
-; CHECK-NEXT: je .LBB1_2 # encoding: [0x74,A]
-; CHECK-NEXT: # fixup A - offset: 1, value: .LBB1_2-1, kind: FK_PCRel_1
-; CHECK-NEXT: # %bb.1: # %cond_true
-; CHECK-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
-; CHECK-NEXT: retq # encoding: [0xc3]
-; CHECK-NEXT: .LBB1_2: # %ReturnBlock
-; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; CHECK-NEXT: retq # encoding: [0xc3]
+; NO-NDD-LABEL: test2:
+; NO-NDD: # %bb.0: # %entry
+; NO-NDD-NEXT: testl $536870911, (%rsi) # encoding: [0xf7,0x06,0xff,0xff,0xff,0x1f]
+; NO-NDD-NEXT: # imm = 0x1FFFFFFF
+; NO-NDD-NEXT: je .LBB1_2 # encoding: [0x74,A]
+; NO-NDD-NEXT: # fixup A - offset: 1, value: .LBB1_2-1, kind: FK_PCRel_1
+; NO-NDD-NEXT: # %bb.1: # %cond_true
+; NO-NDD-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
+; NO-NDD-NEXT: retq # encoding: [0xc3]
+; NO-NDD-NEXT: .LBB1_2: # %ReturnBlock
+; NO-NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; NO-NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-LABEL: test2:
+; NDD: # %bb.0: # %entry
+; NDD-NEXT: testl $536870911, (%rsi) # encoding: [0xf7,0x06,0xff,0xff,0xff,0x1f]
+; NDD-NEXT: # imm = 0x1FFFFFFF
+; NDD-NEXT: je .LBB1_2 # encoding: [0x74,A]
+; NDD-NEXT: # fixup A - offset: 1, value: .LBB1_2-1, kind: FK_PCRel_1
+; NDD-NEXT: # %bb.1: # %cond_true
+; NDD-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
+; NDD-NEXT: retq # encoding: [0xc3]
+; NDD-NEXT: .LBB1_2: # %ReturnBlock
+; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: test2:
+; NDD-ZU: # %bb.0: # %entry
+; NDD-ZU-NEXT: testl $536870911, (%rsi) # encoding: [0xf7,0x06,0xff,0xff,0xff,0x1f]
+; NDD-ZU-NEXT: # imm = 0x1FFFFFFF
+; NDD-ZU-NEXT: je .LBB1_2 # encoding: [0x74,A]
+; NDD-ZU-NEXT: # fixup A - offset: 1, value: .LBB1_2-1, kind: FK_PCRel_1
+; NDD-ZU-NEXT: # %bb.1: # %cond_true
+; NDD-ZU-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
+; NDD-ZU-NEXT: .LBB1_2: # %ReturnBlock
+; NDD-ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: test2:
+; O0-NDD-ZU: # %bb.0: # %entry
+; O0-NDD-ZU-NEXT: shll $3, (%rsi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0xc1,0x26,0x03]
+; O0-NDD-ZU-NEXT: cmpl $0, %eax # encoding: [0x83,0xf8,0x00]
+; O0-NDD-ZU-NEXT: je .LBB1_2 # encoding: [0x74,A]
+; O0-NDD-ZU-NEXT: # fixup A - offset: 1, value: .LBB1_2-1, kind: FK_PCRel_1
+; O0-NDD-ZU-NEXT: # %bb.1: # %cond_true
+; O0-NDD-ZU-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; O0-NDD-ZU-NEXT: .LBB1_2: # %ReturnBlock
+; O0-NDD-ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
entry:
%tmp = load i32, ptr %y
%tmp1 = shl i32 %tmp, 3
@@ -57,17 +97,55 @@ ReturnBlock:
}
define i8 @test2b(i8 %X, ptr %y) nounwind {
-; CHECK-LABEL: test2b:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: testb $31, (%rsi) # encoding: [0xf6,0x06,0x1f]
-; CHECK-NEXT: je .LBB2_2 # encoding: [0x74,A]
-; CHECK-NEXT: # fixup A - offset: 1, value: .LBB2_2-1, kind: FK_PCRel_1
-; CHECK-NEXT: # %bb.1: # %cond_true
-; CHECK-NEXT: movb $1, %al # encoding: [0xb0,0x01]
-; CHECK-NEXT: retq # encoding: [0xc3]
-; CHECK-NEXT: .LBB2_2: # %ReturnBlock
-; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; CHECK-NEXT: retq # encoding: [0xc3]
+; NO-NDD-LABEL: test2b:
+; NO-NDD: # %bb.0: # %entry
+; NO-NDD-NEXT: testb $31, (%rsi) # encoding: [0xf6,0x06,0x1f]
+; NO-NDD-NEXT: je .LBB2_2 # encoding: [0x74,A]
+; NO-NDD-NEXT: # fixup A - offset: 1, value: .LBB2_2-1, kind: FK_PCRel_1
+; NO-NDD-NEXT: # %bb.1: # %cond_true
+; NO-NDD-NEXT: movb $1, %al # encoding: [0xb0,0x01]
+; NO-NDD-NEXT: retq # encoding: [0xc3]
+; NO-NDD-NEXT: .LBB2_2: # %ReturnBlock
+; NO-NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; NO-NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-LABEL: test2b:
+; NDD: # %bb.0: # %entry
+; NDD-NEXT: testb $31, (%rsi) # encoding: [0xf6,0x06,0x1f]
+; NDD-NEXT: je .LBB2_2 # encoding: [0x74,A]
+; NDD-NEXT: # fixup A - offset: 1, value: .LBB2_2-1, kind: FK_PCRel_1
+; NDD-NEXT: # %bb.1: # %cond_true
+; NDD-NEXT: movb $1, %al # encoding: [0xb0,0x01]
+; NDD-NEXT: retq # encoding: [0xc3]
+; NDD-NEXT: .LBB2_2: # %ReturnBlock
+; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: test2b:
+; NDD-ZU: # %bb.0: # %entry
+; NDD-ZU-NEXT: testb $31, (%rsi) # encoding: [0xf6,0x06,0x1f]
+; NDD-ZU-NEXT: je .LBB2_2 # encoding: [0x74,A]
+; NDD-ZU-NEXT: # fixup A - offset: 1, value: .LBB2_2-1, kind: FK_PCRel_1
+; NDD-ZU-NEXT: # %bb.1: # %cond_true
+; NDD-ZU-NEXT: movb $1, %al # encoding: [0xb0,0x01]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
+; NDD-ZU-NEXT: .LBB2_2: # %ReturnBlock
+; NDD-ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: test2b:
+; O0-NDD-ZU: # %bb.0: # %entry
+; O0-NDD-ZU-NEXT: shlb $3, (%rsi), %al # encoding: [0x62,0xf4,0x7c,0x18,0xc0,0x26,0x03]
+; O0-NDD-ZU-NEXT: cmpb $0, %al # encoding: [0x3c,0x00]
+; O0-NDD-ZU-NEXT: je .LBB2_2 # encoding: [0x74,A]
+; O0-NDD-ZU-NEXT: # fixup A - offset: 1, value: .LBB2_2-1, kind: FK_PCRel_1
+; O0-NDD-ZU-NEXT: # %bb.1: # %cond_true
+; O0-NDD-ZU-NEXT: movb $1, %al # encoding: [0xb0,0x01]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; O0-NDD-ZU-NEXT: .LBB2_2: # %ReturnBlock
+; O0-NDD-ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; O0-NDD-ZU-NEXT: # kill: def $al killed $al killed $eax
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
entry:
%tmp = load i8, ptr %y
%tmp1 = shl i8 %tmp, 3
@@ -101,6 +179,15 @@ define i64 @test3(i64 %x) nounwind {
; NDD-ZU-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff]
; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: test3:
+; O0-NDD-ZU: # %bb.0: # %entry
+; O0-NDD-ZU-NEXT: cmpq $0, %rdi # encoding: [0x48,0x83,0xff,0x00]
+; O0-NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
+; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-NDD-ZU-NEXT: # kill: def $rax killed $eax
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
entry:
%t = icmp eq i64 %x, 0
%r = zext i1 %t to i64
@@ -127,31 +214,108 @@ define i64 @test4(i64 %x) nounwind {
; NDD-ZU-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff]
; NDD-ZU-NEXT: setzule %al # encoding: [0x62,0xf4,0x7f,0x18,0x4e,0xc0]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: test4:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: cmpq $1, %rdi # encoding: [0x48,0x83,0xff,0x01]
+; O0-NDD-ZU-NEXT: setzul %al # encoding: [0x62,0xf4,0x7f,0x18,0x4c,0xc0]
+; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
+; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-NDD-ZU-NEXT: # kill: def $rax killed $eax
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%t = icmp slt i64 %x, 1
%r = zext i1 %t to i64
ret i64 %r
}
define i32 @test5(double %A) nounwind {
-; CHECK-LABEL: test5:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # encoding: [0x66,0x0f,0x2e,0x05,A,A,A,A]
-; CHECK-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; CHECK-NEXT: ja .LBB5_3 # encoding: [0x77,A]
-; CHECK-NEXT: # fixup A - offset: 1, value: .LBB5_3-1, kind: FK_PCRel_1
-; CHECK-NEXT: # %bb.1: # %entry
-; CHECK-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # encoding: [0x66,0x0f,0x2e,0x05,A,A,A,A]
-; CHECK-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; CHECK-NEXT: jb .LBB5_3 # encoding: [0x72,A]
-; CHECK-NEXT: # fixup A - offset: 1, value: .LBB5_3-1, kind: FK_PCRel_1
-; CHECK-NEXT: # %bb.2: # %bb12
-; CHECK-NEXT: movl $32, %eax # encoding: [0xb8,0x20,0x00,0x00,0x00]
-; CHECK-NEXT: retq # encoding: [0xc3]
-; CHECK-NEXT: .LBB5_3: # %bb8
-; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; CHECK-NEXT: jmp foo at PLT # TAILCALL
-; CHECK-NEXT: # encoding: [0xeb,A]
-; CHECK-NEXT: # fixup A - offset: 1, value: foo at PLT-1, kind: FK_PCRel_1
+; NO-NDD-LABEL: test5:
+; NO-NDD: # %bb.0: # %entry
+; NO-NDD-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # encoding: [0x66,0x0f,0x2e,0x05,A,A,A,A]
+; NO-NDD-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; NO-NDD-NEXT: ja .LBB5_3 # encoding: [0x77,A]
+; NO-NDD-NEXT: # fixup A - offset: 1, value: .LBB5_3-1, kind: FK_PCRel_1
+; NO-NDD-NEXT: # %bb.1: # %entry
+; NO-NDD-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # encoding: [0x66,0x0f,0x2e,0x05,A,A,A,A]
+; NO-NDD-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; NO-NDD-NEXT: jb .LBB5_3 # encoding: [0x72,A]
+; NO-NDD-NEXT: # fixup A - offset: 1, value: .LBB5_3-1, kind: FK_PCRel_1
+; NO-NDD-NEXT: # %bb.2: # %bb12
+; NO-NDD-NEXT: movl $32, %eax # encoding: [0xb8,0x20,0x00,0x00,0x00]
+; NO-NDD-NEXT: retq # encoding: [0xc3]
+; NO-NDD-NEXT: .LBB5_3: # %bb8
+; NO-NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; NO-NDD-NEXT: jmp foo at PLT # TAILCALL
+; NO-NDD-NEXT: # encoding: [0xeb,A]
+; NO-NDD-NEXT: # fixup A - offset: 1, value: foo at PLT-1, kind: FK_PCRel_1
+;
+; NDD-LABEL: test5:
+; NDD: # %bb.0: # %entry
+; NDD-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # encoding: [0x66,0x0f,0x2e,0x05,A,A,A,A]
+; NDD-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; NDD-NEXT: ja .LBB5_3 # encoding: [0x77,A]
+; NDD-NEXT: # fixup A - offset: 1, value: .LBB5_3-1, kind: FK_PCRel_1
+; NDD-NEXT: # %bb.1: # %entry
+; NDD-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # encoding: [0x66,0x0f,0x2e,0x05,A,A,A,A]
+; NDD-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; NDD-NEXT: jb .LBB5_3 # encoding: [0x72,A]
+; NDD-NEXT: # fixup A - offset: 1, value: .LBB5_3-1, kind: FK_PCRel_1
+; NDD-NEXT: # %bb.2: # %bb12
+; NDD-NEXT: movl $32, %eax # encoding: [0xb8,0x20,0x00,0x00,0x00]
+; NDD-NEXT: retq # encoding: [0xc3]
+; NDD-NEXT: .LBB5_3: # %bb8
+; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; NDD-NEXT: jmp foo at PLT # TAILCALL
+; NDD-NEXT: # encoding: [0xeb,A]
+; NDD-NEXT: # fixup A - offset: 1, value: foo at PLT-1, kind: FK_PCRel_1
+;
+; NDD-ZU-LABEL: test5:
+; NDD-ZU: # %bb.0: # %entry
+; NDD-ZU-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # encoding: [0x66,0x0f,0x2e,0x05,A,A,A,A]
+; NDD-ZU-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; NDD-ZU-NEXT: ja .LBB5_3 # encoding: [0x77,A]
+; NDD-ZU-NEXT: # fixup A - offset: 1, value: .LBB5_3-1, kind: FK_PCRel_1
+; NDD-ZU-NEXT: # %bb.1: # %entry
+; NDD-ZU-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # encoding: [0x66,0x0f,0x2e,0x05,A,A,A,A]
+; NDD-ZU-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; NDD-ZU-NEXT: jb .LBB5_3 # encoding: [0x72,A]
+; NDD-ZU-NEXT: # fixup A - offset: 1, value: .LBB5_3-1, kind: FK_PCRel_1
+; NDD-ZU-NEXT: # %bb.2: # %bb12
+; NDD-ZU-NEXT: movl $32, %eax # encoding: [0xb8,0x20,0x00,0x00,0x00]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
+; NDD-ZU-NEXT: .LBB5_3: # %bb8
+; NDD-ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; NDD-ZU-NEXT: jmp foo at PLT # TAILCALL
+; NDD-ZU-NEXT: # encoding: [0xeb,A]
+; NDD-ZU-NEXT: # fixup A - offset: 1, value: foo at PLT-1, kind: FK_PCRel_1
+;
+; O0-NDD-ZU-LABEL: test5:
+; O0-NDD-ZU: # %bb.0: # %entry
+; O0-NDD-ZU-NEXT: movsd {{.*#+}} xmm1 = [1.5E+2,0.0E+0]
+; O0-NDD-ZU-NEXT: # encoding: [0xf2,0x0f,0x10,0x0d,A,A,A,A]
+; O0-NDD-ZU-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; O0-NDD-ZU-NEXT: ucomisd %xmm1, %xmm0 # encoding: [0x66,0x0f,0x2e,0xc1]
+; O0-NDD-ZU-NEXT: setzua %al # encoding: [0x62,0xf4,0x7f,0x18,0x47,0xc0]
+; O0-NDD-ZU-NEXT: movsd {{.*#+}} xmm1 = [7.5E+1,0.0E+0]
+; O0-NDD-ZU-NEXT: # encoding: [0xf2,0x0f,0x10,0x0d,A,A,A,A]
+; O0-NDD-ZU-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; O0-NDD-ZU-NEXT: ucomisd %xmm1, %xmm0 # encoding: [0x66,0x0f,0x2e,0xc1]
+; O0-NDD-ZU-NEXT: setzub %cl # encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc1]
+; O0-NDD-ZU-NEXT: orb %cl, %al # EVEX TO LEGACY Compression encoding: [0x08,0xc8]
+; O0-NDD-ZU-NEXT: testb $1, %al # encoding: [0xa8,0x01]
+; O0-NDD-ZU-NEXT: jne .LBB5_1 # encoding: [0x75,A]
+; O0-NDD-ZU-NEXT: # fixup A - offset: 1, value: .LBB5_1-1, kind: FK_PCRel_1
+; O0-NDD-ZU-NEXT: jmp .LBB5_2 # encoding: [0xeb,A]
+; O0-NDD-ZU-NEXT: # fixup A - offset: 1, value: .LBB5_2-1, kind: FK_PCRel_1
+; O0-NDD-ZU-NEXT: .LBB5_1: # %bb8
+; O0-NDD-ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; O0-NDD-ZU-NEXT: # kill: def $al killed $al killed $eax
+; O0-NDD-ZU-NEXT: jmp foo at PLT # TAILCALL
+; O0-NDD-ZU-NEXT: # encoding: [0xeb,A]
+; O0-NDD-ZU-NEXT: # fixup A - offset: 1, value: foo at PLT-1, kind: FK_PCRel_1
+; O0-NDD-ZU-NEXT: .LBB5_2: # %bb12
+; O0-NDD-ZU-NEXT: movl $32, %eax # encoding: [0xb8,0x20,0x00,0x00,0x00]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
entry:
%tmp2 = fcmp ogt double %A, 1.500000e+02
%tmp5 = fcmp ult double %A, 7.500000e+01
@@ -169,17 +333,53 @@ bb12:
declare i32 @foo(...)
define i32 @test6() nounwind align 2 {
-; CHECK-LABEL: test6:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: cmpq $0, -{{[0-9]+}}(%rsp) # encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00]
-; CHECK-NEXT: je .LBB6_1 # encoding: [0x74,A]
-; CHECK-NEXT: # fixup A - offset: 1, value: .LBB6_1-1, kind: FK_PCRel_1
-; CHECK-NEXT: # %bb.2: # %F
-; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; CHECK-NEXT: retq # encoding: [0xc3]
-; CHECK-NEXT: .LBB6_1: # %T
-; CHECK-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
-; CHECK-NEXT: retq # encoding: [0xc3]
+; NO-NDD-LABEL: test6:
+; NO-NDD: # %bb.0: # %entry
+; NO-NDD-NEXT: cmpq $0, -{{[0-9]+}}(%rsp) # encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00]
+; NO-NDD-NEXT: je .LBB6_1 # encoding: [0x74,A]
+; NO-NDD-NEXT: # fixup A - offset: 1, value: .LBB6_1-1, kind: FK_PCRel_1
+; NO-NDD-NEXT: # %bb.2: # %F
+; NO-NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; NO-NDD-NEXT: retq # encoding: [0xc3]
+; NO-NDD-NEXT: .LBB6_1: # %T
+; NO-NDD-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
+; NO-NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-LABEL: test6:
+; NDD: # %bb.0: # %entry
+; NDD-NEXT: cmpq $0, -{{[0-9]+}}(%rsp) # encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00]
+; NDD-NEXT: je .LBB6_1 # encoding: [0x74,A]
+; NDD-NEXT: # fixup A - offset: 1, value: .LBB6_1-1, kind: FK_PCRel_1
+; NDD-NEXT: # %bb.2: # %F
+; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; NDD-NEXT: retq # encoding: [0xc3]
+; NDD-NEXT: .LBB6_1: # %T
+; NDD-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
+; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: test6:
+; NDD-ZU: # %bb.0: # %entry
+; NDD-ZU-NEXT: cmpq $0, -{{[0-9]+}}(%rsp) # encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00]
+; NDD-ZU-NEXT: je .LBB6_1 # encoding: [0x74,A]
+; NDD-ZU-NEXT: # fixup A - offset: 1, value: .LBB6_1-1, kind: FK_PCRel_1
+; NDD-ZU-NEXT: # %bb.2: # %F
+; NDD-ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
+; NDD-ZU-NEXT: .LBB6_1: # %T
+; NDD-ZU-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: test6:
+; O0-NDD-ZU: # %bb.0: # %entry
+; O0-NDD-ZU-NEXT: cmpq $0, -{{[0-9]+}}(%rsp) # encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00]
+; O0-NDD-ZU-NEXT: jne .LBB6_2 # encoding: [0x75,A]
+; O0-NDD-ZU-NEXT: # fixup A - offset: 1, value: .LBB6_2-1, kind: FK_PCRel_1
+; O0-NDD-ZU-NEXT: # %bb.1: # %T
+; O0-NDD-ZU-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; O0-NDD-ZU-NEXT: .LBB6_2: # %F
+; O0-NDD-ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
entry:
%A = alloca { i64, i64 }, align 8
%B = getelementptr inbounds { i64, i64 }, ptr %A, i64 0, i32 1
@@ -214,6 +414,16 @@ define i32 @test7(i64 %res) nounwind {
; NDD-ZU-NEXT: shrq $32, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x20]
; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: test7:
+; O0-NDD-ZU: # %bb.0: # %entry
+; O0-NDD-ZU-NEXT: movabsq $4294967296, %rax # encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00]
+; O0-NDD-ZU-NEXT: # imm = 0x100000000
+; O0-NDD-ZU-NEXT: cmpq %rax, %rdi # encoding: [0x48,0x39,0xc7]
+; O0-NDD-ZU-NEXT: setzub %al # encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc0]
+; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
+; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
entry:
%lnot = icmp ult i64 %res, 4294967296
%lnot.ext = zext i1 %lnot to i32
@@ -243,6 +453,16 @@ define i32 @test8(i64 %res) nounwind {
; NDD-ZU-NEXT: cmpl $3, %edi # encoding: [0x83,0xff,0x03]
; NDD-ZU-NEXT: setzub %al # encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc0]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: test8:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: movabsq $12884901888, %rax # encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x03,0x00,0x00,0x00]
+; O0-NDD-ZU-NEXT: # imm = 0x300000000
+; O0-NDD-ZU-NEXT: cmpq %rax, %rdi # encoding: [0x48,0x39,0xc7]
+; O0-NDD-ZU-NEXT: setzub %al # encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc0]
+; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
+; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%lnot = icmp ult i64 %res, 12884901888
%lnot.ext = zext i1 %lnot to i32
ret i32 %lnot.ext
@@ -268,6 +488,16 @@ define i32 @test9(i64 %res) nounwind {
; NDD-ZU-NEXT: shrq $33, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x21]
; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: test9:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: movabsq $8589934592, %rax # encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00]
+; O0-NDD-ZU-NEXT: # imm = 0x200000000
+; O0-NDD-ZU-NEXT: cmpq %rax, %rdi # encoding: [0x48,0x39,0xc7]
+; O0-NDD-ZU-NEXT: setzub %al # encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc0]
+; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
+; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%lnot = icmp ult i64 %res, 8589934592
%lnot.ext = zext i1 %lnot to i32
ret i32 %lnot.ext
@@ -293,6 +523,16 @@ define i32 @test10(i64 %res) nounwind {
; NDD-ZU-NEXT: shrq $32, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x20]
; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: test10:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: movabsq $4294967296, %rax # encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00]
+; O0-NDD-ZU-NEXT: # imm = 0x100000000
+; O0-NDD-ZU-NEXT: cmpq %rax, %rdi # encoding: [0x48,0x39,0xc7]
+; O0-NDD-ZU-NEXT: setzuae %al # encoding: [0x62,0xf4,0x7f,0x18,0x43,0xc0]
+; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
+; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%lnot = icmp uge i64 %res, 4294967296
%lnot.ext = zext i1 %lnot to i32
ret i32 %lnot.ext
@@ -321,6 +561,19 @@ define i32 @test11(i64 %l) nounwind {
; NDD-ZU-NEXT: cmpl $1, %edi # encoding: [0x83,0xff,0x01]
; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: test11:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: movabsq $-140737488355328, %rax # encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0x80,0xff,0xff]
+; O0-NDD-ZU-NEXT: # imm = 0xFFFF800000000000
+; O0-NDD-ZU-NEXT: andq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x21,0xf8]
+; O0-NDD-ZU-NEXT: movabsq $140737488355328, %rcx # encoding: [0x48,0xb9,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00]
+; O0-NDD-ZU-NEXT: # imm = 0x800000000000
+; O0-NDD-ZU-NEXT: cmpq %rcx, %rax # encoding: [0x48,0x39,0xc8]
+; O0-NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
+; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%shr.mask = and i64 %l, -140737488355328
%cmp = icmp eq i64 %shr.mask, 140737488355328
%conv = zext i1 %cmp to i32
@@ -328,26 +581,91 @@ define i32 @test11(i64 %l) nounwind {
}
define i32 @test12() ssp uwtable {
-; CHECK-LABEL: test12:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: pushq %rax # encoding: [0x50]
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq test12b at PLT # encoding: [0xe8,A,A,A,A]
-; CHECK-NEXT: # fixup A - offset: 1, value: test12b at PLT-4, kind: FK_PCRel_4
-; CHECK-NEXT: testb %al, %al # encoding: [0x84,0xc0]
-; CHECK-NEXT: je .LBB12_2 # encoding: [0x74,A]
-; CHECK-NEXT: # fixup A - offset: 1, value: .LBB12_2-1, kind: FK_PCRel_1
-; CHECK-NEXT: # %bb.1: # %T
-; CHECK-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
-; CHECK-NEXT: popq %rcx # encoding: [0x59]
-; CHECK-NEXT: .cfi_def_cfa_offset 8
-; CHECK-NEXT: retq # encoding: [0xc3]
-; CHECK-NEXT: .LBB12_2: # %F
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: movl $2, %eax # encoding: [0xb8,0x02,0x00,0x00,0x00]
-; CHECK-NEXT: popq %rcx # encoding: [0x59]
-; CHECK-NEXT: .cfi_def_cfa_offset 8
-; CHECK-NEXT: retq # encoding: [0xc3]
+; NO-NDD-LABEL: test12:
+; NO-NDD: # %bb.0: # %entry
+; NO-NDD-NEXT: pushq %rax # encoding: [0x50]
+; NO-NDD-NEXT: .cfi_def_cfa_offset 16
+; NO-NDD-NEXT: callq test12b at PLT # encoding: [0xe8,A,A,A,A]
+; NO-NDD-NEXT: # fixup A - offset: 1, value: test12b at PLT-4, kind: FK_PCRel_4
+; NO-NDD-NEXT: testb %al, %al # encoding: [0x84,0xc0]
+; NO-NDD-NEXT: je .LBB12_2 # encoding: [0x74,A]
+; NO-NDD-NEXT: # fixup A - offset: 1, value: .LBB12_2-1, kind: FK_PCRel_1
+; NO-NDD-NEXT: # %bb.1: # %T
+; NO-NDD-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
+; NO-NDD-NEXT: popq %rcx # encoding: [0x59]
+; NO-NDD-NEXT: .cfi_def_cfa_offset 8
+; NO-NDD-NEXT: retq # encoding: [0xc3]
+; NO-NDD-NEXT: .LBB12_2: # %F
+; NO-NDD-NEXT: .cfi_def_cfa_offset 16
+; NO-NDD-NEXT: movl $2, %eax # encoding: [0xb8,0x02,0x00,0x00,0x00]
+; NO-NDD-NEXT: popq %rcx # encoding: [0x59]
+; NO-NDD-NEXT: .cfi_def_cfa_offset 8
+; NO-NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-LABEL: test12:
+; NDD: # %bb.0: # %entry
+; NDD-NEXT: pushq %rax # encoding: [0x50]
+; NDD-NEXT: .cfi_def_cfa_offset 16
+; NDD-NEXT: callq test12b at PLT # encoding: [0xe8,A,A,A,A]
+; NDD-NEXT: # fixup A - offset: 1, value: test12b at PLT-4, kind: FK_PCRel_4
+; NDD-NEXT: testb %al, %al # encoding: [0x84,0xc0]
+; NDD-NEXT: je .LBB12_2 # encoding: [0x74,A]
+; NDD-NEXT: # fixup A - offset: 1, value: .LBB12_2-1, kind: FK_PCRel_1
+; NDD-NEXT: # %bb.1: # %T
+; NDD-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
+; NDD-NEXT: popq %rcx # encoding: [0x59]
+; NDD-NEXT: .cfi_def_cfa_offset 8
+; NDD-NEXT: retq # encoding: [0xc3]
+; NDD-NEXT: .LBB12_2: # %F
+; NDD-NEXT: .cfi_def_cfa_offset 16
+; NDD-NEXT: movl $2, %eax # encoding: [0xb8,0x02,0x00,0x00,0x00]
+; NDD-NEXT: popq %rcx # encoding: [0x59]
+; NDD-NEXT: .cfi_def_cfa_offset 8
+; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: test12:
+; NDD-ZU: # %bb.0: # %entry
+; NDD-ZU-NEXT: pushq %rax # encoding: [0x50]
+; NDD-ZU-NEXT: .cfi_def_cfa_offset 16
+; NDD-ZU-NEXT: callq test12b at PLT # encoding: [0xe8,A,A,A,A]
+; NDD-ZU-NEXT: # fixup A - offset: 1, value: test12b at PLT-4, kind: FK_PCRel_4
+; NDD-ZU-NEXT: testb %al, %al # encoding: [0x84,0xc0]
+; NDD-ZU-NEXT: je .LBB12_2 # encoding: [0x74,A]
+; NDD-ZU-NEXT: # fixup A - offset: 1, value: .LBB12_2-1, kind: FK_PCRel_1
+; NDD-ZU-NEXT: # %bb.1: # %T
+; NDD-ZU-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
+; NDD-ZU-NEXT: popq %rcx # encoding: [0x59]
+; NDD-ZU-NEXT: .cfi_def_cfa_offset 8
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
+; NDD-ZU-NEXT: .LBB12_2: # %F
+; NDD-ZU-NEXT: .cfi_def_cfa_offset 16
+; NDD-ZU-NEXT: movl $2, %eax # encoding: [0xb8,0x02,0x00,0x00,0x00]
+; NDD-ZU-NEXT: popq %rcx # encoding: [0x59]
+; NDD-ZU-NEXT: .cfi_def_cfa_offset 8
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: test12:
+; O0-NDD-ZU: # %bb.0: # %entry
+; O0-NDD-ZU-NEXT: pushq %rax # encoding: [0x50]
+; O0-NDD-ZU-NEXT: .cfi_def_cfa_offset 16
+; O0-NDD-ZU-NEXT: callq test12b at PLT # encoding: [0xe8,A,A,A,A]
+; O0-NDD-ZU-NEXT: # fixup A - offset: 1, value: test12b at PLT-4, kind: FK_PCRel_4
+; O0-NDD-ZU-NEXT: testb $1, %al # encoding: [0xa8,0x01]
+; O0-NDD-ZU-NEXT: jne .LBB12_1 # encoding: [0x75,A]
+; O0-NDD-ZU-NEXT: # fixup A - offset: 1, value: .LBB12_1-1, kind: FK_PCRel_1
+; O0-NDD-ZU-NEXT: jmp .LBB12_2 # encoding: [0xeb,A]
+; O0-NDD-ZU-NEXT: # fixup A - offset: 1, value: .LBB12_2-1, kind: FK_PCRel_1
+; O0-NDD-ZU-NEXT: .LBB12_1: # %T
+; O0-NDD-ZU-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
+; O0-NDD-ZU-NEXT: popq %rcx # encoding: [0x59]
+; O0-NDD-ZU-NEXT: .cfi_def_cfa_offset 8
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; O0-NDD-ZU-NEXT: .LBB12_2: # %F
+; O0-NDD-ZU-NEXT: .cfi_def_cfa_offset 16
+; O0-NDD-ZU-NEXT: movl $2, %eax # encoding: [0xb8,0x02,0x00,0x00,0x00]
+; O0-NDD-ZU-NEXT: popq %rcx # encoding: [0x59]
+; O0-NDD-ZU-NEXT: .cfi_def_cfa_offset 8
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
entry:
%tmp1 = call zeroext i1 @test12b()
br i1 %tmp1, label %T, label %F
@@ -380,6 +698,13 @@ define i32 @test13(i32 %mask, i32 %base, i32 %intra) {
; NDD-ZU-NEXT: testb $8, %dil # encoding: [0x40,0xf6,0xc7,0x08]
; NDD-ZU-NEXT: cmovnel %edx, %esi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x45,0xf2]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: test13:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: andl $8, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xe7,0x08]
+; O0-NDD-ZU-NEXT: cmpl $0, %eax # encoding: [0x83,0xf8,0x00]
+; O0-NDD-ZU-NEXT: cmovnel %edx, %esi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x45,0xf2]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%and = and i32 %mask, 8
%tobool = icmp ne i32 %and, 0
%cond = select i1 %tobool, i32 %intra, i32 %base
@@ -405,6 +730,13 @@ define i32 @test14(i32 %mask, i32 %base, i32 %intra) {
; NDD-ZU-NEXT: shrl $7, %edi # EVEX TO LEGACY Compression encoding: [0xc1,0xef,0x07]
; NDD-ZU-NEXT: cmovnsl %edx, %esi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x49,0xf2]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: test14:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: shrl $7, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0xc1,0xef,0x07]
+; O0-NDD-ZU-NEXT: cmpl $-1, %eax # encoding: [0x83,0xf8,0xff]
+; O0-NDD-ZU-NEXT: cmovgl %edx, %esi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x4f,0xf2]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%s = lshr i32 %mask, 7
%tobool = icmp sgt i32 %s, -1
%cond = select i1 %tobool, i32 %intra, i32 %base
@@ -439,6 +771,17 @@ define zeroext i1 @test15(i32 %bf.load, i32 %n) {
; NDD-ZU-NEXT: setzuae %cl # encoding: [0x62,0xf4,0x7f,0x18,0x43,0xc1]
; NDD-ZU-NEXT: orb %cl, %al # EVEX TO LEGACY Compression encoding: [0x08,0xc8]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: test15:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: shrl $16, %edi, %ecx # encoding: [0x62,0xf4,0x74,0x18,0xc1,0xef,0x10]
+; O0-NDD-ZU-NEXT: cmpl $0, %ecx # encoding: [0x83,0xf9,0x00]
+; O0-NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; O0-NDD-ZU-NEXT: cmpl %esi, %ecx # encoding: [0x39,0xf1]
+; O0-NDD-ZU-NEXT: setzuae %cl # encoding: [0x62,0xf4,0x7f,0x18,0x43,0xc1]
+; O0-NDD-ZU-NEXT: orb %cl, %al # EVEX TO LEGACY Compression encoding: [0x08,0xc8]
+; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%bf.lshr = lshr i32 %bf.load, 16
%cmp2 = icmp eq i32 %bf.lshr, 0
%cmp5 = icmp uge i32 %bf.lshr, %n
@@ -464,6 +807,14 @@ define i8 @signbit_i16(i16 signext %L) {
; NDD-ZU-NEXT: testw %di, %di # encoding: [0x66,0x85,0xff]
; NDD-ZU-NEXT: setzuns %al # encoding: [0x62,0xf4,0x7f,0x18,0x49,0xc0]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: signbit_i16:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: movw %di, %ax # encoding: [0x66,0x89,0xf8]
+; O0-NDD-ZU-NEXT: shrw $15, %ax # EVEX TO LEGACY Compression encoding: [0x66,0xc1,0xe8,0x0f]
+; O0-NDD-ZU-NEXT: # kill: def $al killed $al killed $ax
+; O0-NDD-ZU-NEXT: xorb $1, %al # EVEX TO LEGACY Compression encoding: [0x34,0x01]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%lshr = lshr i16 %L, 15
%trunc = trunc i16 %lshr to i8
%not = xor i8 %trunc, 1
@@ -488,6 +839,13 @@ define i8 @signbit_i32(i32 %L) {
; NDD-ZU-NEXT: testl %edi, %edi # encoding: [0x85,0xff]
; NDD-ZU-NEXT: setzuns %al # encoding: [0x62,0xf4,0x7f,0x18,0x49,0xc0]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: signbit_i32:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: shrl $31, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0xc1,0xef,0x1f]
+; O0-NDD-ZU-NEXT: # kill: def $al killed $al killed $eax
+; O0-NDD-ZU-NEXT: xorb $1, %al # EVEX TO LEGACY Compression encoding: [0x34,0x01]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%lshr = lshr i32 %L, 31
%trunc = trunc i32 %lshr to i8
%not = xor i8 %trunc, 1
@@ -512,6 +870,13 @@ define i8 @signbit_i64(i64 %L) {
; NDD-ZU-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff]
; NDD-ZU-NEXT: setzuns %al # encoding: [0x62,0xf4,0x7f,0x18,0x49,0xc0]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: signbit_i64:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: shrq $63, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xc1,0xef,0x3f]
+; O0-NDD-ZU-NEXT: # kill: def $al killed $al killed $rax
+; O0-NDD-ZU-NEXT: xorb $1, %al # EVEX TO LEGACY Compression encoding: [0x34,0x01]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%lshr = lshr i64 %L, 63
%trunc = trunc i64 %lshr to i8
%not = xor i8 %trunc, 1
@@ -536,6 +901,14 @@ define zeroext i1 @signbit_i32_i1(i32 %L) {
; NDD-ZU-NEXT: testl %edi, %edi # encoding: [0x85,0xff]
; NDD-ZU-NEXT: setzuns %al # encoding: [0x62,0xf4,0x7f,0x18,0x49,0xc0]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: signbit_i32_i1:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: shrl $31, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0xc1,0xef,0x1f]
+; O0-NDD-ZU-NEXT: # kill: def $al killed $al killed $eax
+; O0-NDD-ZU-NEXT: xorb $-1, %al # EVEX TO LEGACY Compression encoding: [0x34,0xff]
+; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%lshr = lshr i32 %L, 31
%trunc = trunc i32 %lshr to i1
%not = xor i1 %trunc, true
@@ -587,6 +960,28 @@ define void @test20(i32 %bf.load, i8 %x1, ptr %b_addr) {
; NDD-ZU-NEXT: setne d(%rip) # encoding: [0x0f,0x95,0x05,A,A,A,A]
; NDD-ZU-NEXT: # fixup A - offset: 3, value: d-4, kind: reloc_riprel_4byte
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: test20:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: # kill: def $sil killed $sil killed $esi
+; O0-NDD-ZU-NEXT: shll $8, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0xc1,0xe7,0x08]
+; O0-NDD-ZU-NEXT: sarl $8, %eax, %ecx # encoding: [0x62,0xf4,0x74,0x18,0xc1,0xf8,0x08]
+; O0-NDD-ZU-NEXT: cmpl $0, %ecx # encoding: [0x83,0xf9,0x00]
+; O0-NDD-ZU-NEXT: setzune %cl # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc1]
+; O0-NDD-ZU-NEXT: andb $1, %cl # EVEX TO LEGACY Compression encoding: [0x80,0xe1,0x01]
+; O0-NDD-ZU-NEXT: movzbl %cl, %ecx # encoding: [0x0f,0xb6,0xc9]
+; O0-NDD-ZU-NEXT: movzbl %sil, %esi # encoding: [0x40,0x0f,0xb6,0xf6]
+; O0-NDD-ZU-NEXT: addl %esi, %ecx # EVEX TO LEGACY Compression encoding: [0x01,0xf1]
+; O0-NDD-ZU-NEXT: cmpl $0, %ecx # encoding: [0x83,0xf9,0x00]
+; O0-NDD-ZU-NEXT: setzune %cl # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc1]
+; O0-NDD-ZU-NEXT: andb $1, %cl # EVEX TO LEGACY Compression encoding: [0x80,0xe1,0x01]
+; O0-NDD-ZU-NEXT: movb %cl, (%rdx) # encoding: [0x88,0x0a]
+; O0-NDD-ZU-NEXT: cmpl $0, %eax # encoding: [0x83,0xf8,0x00]
+; O0-NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
+; O0-NDD-ZU-NEXT: movb %al, d # encoding: [0x88,0x04,0x25,A,A,A,A]
+; O0-NDD-ZU-NEXT: # fixup A - offset: 3, value: d, kind: reloc_signed_4byte
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%bf.shl = shl i32 %bf.load, 8
%bf.ashr = ashr exact i32 %bf.shl, 8
%tobool4 = icmp ne i32 %bf.ashr, 0
@@ -603,10 +998,31 @@ define void @test20(i32 %bf.load, i8 %x1, ptr %b_addr) {
}
define i32 @highmask_i64_simplify(i64 %val) {
-; CHECK-LABEL: highmask_i64_simplify:
-; CHECK: # %bb.0:
-; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; CHECK-NEXT: retq # encoding: [0xc3]
+; NO-NDD-LABEL: highmask_i64_simplify:
+; NO-NDD: # %bb.0:
+; NO-NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; NO-NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-LABEL: highmask_i64_simplify:
+; NDD: # %bb.0:
+; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; NDD-NEXT: retq # encoding: [0xc3]
+;
+; NDD-ZU-LABEL: highmask_i64_simplify:
+; NDD-ZU: # %bb.0:
+; NDD-ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: highmask_i64_simplify:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: movabsq $-2199023255552, %rax # encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0xfe,0xff,0xff]
+; O0-NDD-ZU-NEXT: # imm = 0xFFFFFE0000000000
+; O0-NDD-ZU-NEXT: andq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x21,0xf8]
+; O0-NDD-ZU-NEXT: cmpq $0, %rax # encoding: [0x48,0x83,0xf8,0x00]
+; O0-NDD-ZU-NEXT: setzub %al # encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc0]
+; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
+; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%and = and i64 %val, -2199023255552
%cmp = icmp ult i64 %and, 0
%ret = zext i1 %cmp to i32
@@ -633,6 +1049,17 @@ define i32 @highmask_i64_mask64(i64 %val) {
; NDD-ZU-NEXT: shrq $41, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x29]
; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: highmask_i64_mask64:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: movabsq $-2199023255552, %rax # encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0xfe,0xff,0xff]
+; O0-NDD-ZU-NEXT: # imm = 0xFFFFFE0000000000
+; O0-NDD-ZU-NEXT: andq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x21,0xf8]
+; O0-NDD-ZU-NEXT: cmpq $0, %rax # encoding: [0x48,0x83,0xf8,0x00]
+; O0-NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
+; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%and = and i64 %val, -2199023255552
%cmp = icmp ne i64 %and, 0
%ret = zext i1 %cmp to i32
@@ -663,6 +1090,19 @@ define i64 @highmask_i64_mask64_extra_use(i64 %val) nounwind {
; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
; NDD-ZU-NEXT: imulq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0xaf,0xc7]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: highmask_i64_mask64_extra_use:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: movabsq $-2199023255552, %rax # encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0xfe,0xff,0xff]
+; O0-NDD-ZU-NEXT: # imm = 0xFFFFFE0000000000
+; O0-NDD-ZU-NEXT: andq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x21,0xf8]
+; O0-NDD-ZU-NEXT: cmpq $0, %rax # encoding: [0x48,0x83,0xf8,0x00]
+; O0-NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
+; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-NDD-ZU-NEXT: # kill: def $rax killed $eax
+; O0-NDD-ZU-NEXT: imulq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0xaf,0xc7]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%and = and i64 %val, -2199023255552
%cmp = icmp ne i64 %and, 0
%z = zext i1 %cmp to i64
@@ -690,6 +1130,16 @@ define i32 @highmask_i64_mask32(i64 %val) {
; NDD-ZU-NEXT: shrq $20, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x14]
; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: highmask_i64_mask32:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: andq $-1048576, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0xe7,0x00,0x00,0xf0,0xff]
+; O0-NDD-ZU-NEXT: # imm = 0xFFF00000
+; O0-NDD-ZU-NEXT: cmpq $0, %rax # encoding: [0x48,0x83,0xf8,0x00]
+; O0-NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
+; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%and = and i64 %val, -1048576
%cmp = icmp eq i64 %and, 0
%ret = zext i1 %cmp to i32
@@ -722,6 +1172,18 @@ define i64 @highmask_i64_mask32_extra_use(i64 %val) nounwind {
; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NDD-ZU-NEXT: imulq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0xaf,0xc7]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: highmask_i64_mask32_extra_use:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: andq $-1048576, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0xe7,0x00,0x00,0xf0,0xff]
+; O0-NDD-ZU-NEXT: # imm = 0xFFF00000
+; O0-NDD-ZU-NEXT: cmpq $0, %rax # encoding: [0x48,0x83,0xf8,0x00]
+; O0-NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
+; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-NDD-ZU-NEXT: # kill: def $rax killed $eax
+; O0-NDD-ZU-NEXT: imulq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0xaf,0xc7]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%and = and i64 %val, -1048576
%cmp = icmp eq i64 %and, 0
%z = zext i1 %cmp to i64
@@ -749,6 +1211,15 @@ define i32 @highmask_i64_mask8(i64 %val) {
; NDD-ZU-NEXT: testq $-16, %rdi # encoding: [0x48,0xf7,0xc7,0xf0,0xff,0xff,0xff]
; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: highmask_i64_mask8:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: andq $-16, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0xe7,0xf0]
+; O0-NDD-ZU-NEXT: cmpq $0, %rax # encoding: [0x48,0x83,0xf8,0x00]
+; O0-NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
+; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%and = and i64 %val, -16
%cmp = icmp ne i64 %and, 0
%ret = zext i1 %cmp to i32
@@ -775,6 +1246,17 @@ define i32 @lowmask_i64_mask64(i64 %val) {
; NDD-ZU-NEXT: shlq $16, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xe7,0x10]
; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: lowmask_i64_mask64:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: movabsq $281474976710655, %rax # encoding: [0x48,0xb8,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00]
+; O0-NDD-ZU-NEXT: # imm = 0xFFFFFFFFFFFF
+; O0-NDD-ZU-NEXT: andq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x21,0xf8]
+; O0-NDD-ZU-NEXT: cmpq $0, %rax # encoding: [0x48,0x83,0xf8,0x00]
+; O0-NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
+; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%and = and i64 %val, 281474976710655
%cmp = icmp eq i64 %and, 0
%ret = zext i1 %cmp to i32
@@ -805,6 +1287,19 @@ define i64 @lowmask_i64_mask64_extra_use(i64 %val) nounwind {
; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NDD-ZU-NEXT: imulq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0xaf,0xc7]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: lowmask_i64_mask64_extra_use:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: movabsq $281474976710655, %rax # encoding: [0x48,0xb8,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00]
+; O0-NDD-ZU-NEXT: # imm = 0xFFFFFFFFFFFF
+; O0-NDD-ZU-NEXT: andq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x21,0xf8]
+; O0-NDD-ZU-NEXT: cmpq $0, %rax # encoding: [0x48,0x83,0xf8,0x00]
+; O0-NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
+; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-NDD-ZU-NEXT: # kill: def $rax killed $eax
+; O0-NDD-ZU-NEXT: imulq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0xaf,0xc7]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%and = and i64 %val, 281474976710655
%cmp = icmp eq i64 %and, 0
%z = zext i1 %cmp to i64
@@ -832,6 +1327,16 @@ define i32 @lowmask_i64_mask32(i64 %val) {
; NDD-ZU-NEXT: shlq $44, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xe7,0x2c]
; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: lowmask_i64_mask32:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: andq $1048575, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0xe7,0xff,0xff,0x0f,0x00]
+; O0-NDD-ZU-NEXT: # imm = 0xFFFFF
+; O0-NDD-ZU-NEXT: cmpq $0, %rax # encoding: [0x48,0x83,0xf8,0x00]
+; O0-NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
+; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%and = and i64 %val, 1048575
%cmp = icmp ne i64 %and, 0
%ret = zext i1 %cmp to i32
@@ -864,6 +1369,18 @@ define i64 @lowmask_i64_mask32_extra_use(i64 %val) nounwind {
; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
; NDD-ZU-NEXT: imulq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0xaf,0xc7]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: lowmask_i64_mask32_extra_use:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: andq $1048575, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0xe7,0xff,0xff,0x0f,0x00]
+; O0-NDD-ZU-NEXT: # imm = 0xFFFFF
+; O0-NDD-ZU-NEXT: cmpq $0, %rax # encoding: [0x48,0x83,0xf8,0x00]
+; O0-NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
+; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-NDD-ZU-NEXT: # kill: def $rax killed $eax
+; O0-NDD-ZU-NEXT: imulq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0xaf,0xc7]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%and = and i64 %val, 1048575
%cmp = icmp ne i64 %and, 0
%z = zext i1 %cmp to i64
@@ -891,6 +1408,15 @@ define i32 @lowmask_i64_mask8(i64 %val) {
; NDD-ZU-NEXT: testb $31, %dil # encoding: [0x40,0xf6,0xc7,0x1f]
; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: lowmask_i64_mask8:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: andq $31, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0xe7,0x1f]
+; O0-NDD-ZU-NEXT: cmpq $0, %rax # encoding: [0x48,0x83,0xf8,0x00]
+; O0-NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
+; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%and = and i64 %val, 31
%cmp = icmp eq i64 %and, 0
%ret = zext i1 %cmp to i32
@@ -920,6 +1446,16 @@ define i32 @highmask_i32_mask32(i32 %val) {
; NDD-ZU-NEXT: # imm = 0xFFF00000
; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: highmask_i32_mask32:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: andl $-1048576, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xe7,0x00,0x00,0xf0,0xff]
+; O0-NDD-ZU-NEXT: # imm = 0xFFF00000
+; O0-NDD-ZU-NEXT: cmpl $0, %eax # encoding: [0x83,0xf8,0x00]
+; O0-NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
+; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%and = and i32 %val, -1048576
%cmp = icmp ne i32 %and, 0
%ret = zext i1 %cmp to i32
@@ -946,6 +1482,15 @@ define i32 @highmask_i32_mask8(i32 %val) {
; NDD-ZU-NEXT: testl $-16, %edi # encoding: [0xf7,0xc7,0xf0,0xff,0xff,0xff]
; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: highmask_i32_mask8:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: andl $-16, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xe7,0xf0]
+; O0-NDD-ZU-NEXT: cmpl $0, %eax # encoding: [0x83,0xf8,0x00]
+; O0-NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
+; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%and = and i32 %val, -16
%cmp = icmp eq i32 %and, 0
%ret = zext i1 %cmp to i32
@@ -975,6 +1520,16 @@ define i32 @lowmask_i32_mask32(i32 %val) {
; NDD-ZU-NEXT: # imm = 0xFFFFF
; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: lowmask_i32_mask32:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: andl $1048575, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xe7,0xff,0xff,0x0f,0x00]
+; O0-NDD-ZU-NEXT: # imm = 0xFFFFF
+; O0-NDD-ZU-NEXT: cmpl $0, %eax # encoding: [0x83,0xf8,0x00]
+; O0-NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
+; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%and = and i32 %val, 1048575
%cmp = icmp eq i32 %and, 0
%ret = zext i1 %cmp to i32
@@ -1001,6 +1556,15 @@ define i32 @lowmask_i32_mask8(i32 %val) {
; NDD-ZU-NEXT: testb $31, %dil # encoding: [0x40,0xf6,0xc7,0x1f]
; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: lowmask_i32_mask8:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: andl $31, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xe7,0x1f]
+; O0-NDD-ZU-NEXT: cmpl $0, %eax # encoding: [0x83,0xf8,0x00]
+; O0-NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
+; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%and = and i32 %val, 31
%cmp = icmp ne i32 %and, 0
%ret = zext i1 %cmp to i32
@@ -1028,6 +1592,14 @@ define i1 @shifted_mask64_testb(i64 %a) {
; NDD-ZU-NEXT: testb %dil, %dil # encoding: [0x40,0x84,0xff]
; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: shifted_mask64_testb:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: shrq $50, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xc1,0xef,0x32]
+; O0-NDD-ZU-NEXT: # kill: def $al killed $al killed $rax
+; O0-NDD-ZU-NEXT: testb %al, %al # encoding: [0x84,0xc0]
+; O0-NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%v0 = and i64 %a, 287104476244869120 ; 0xff << 50
%v1 = icmp ne i64 %v0, 0
ret i1 %v1
@@ -1054,6 +1626,14 @@ define i1 @shifted_mask64_testw(i64 %a) {
; NDD-ZU-NEXT: testw %di, %di # encoding: [0x66,0x85,0xff]
; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: shifted_mask64_testw:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: shrq $33, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xc1,0xef,0x21]
+; O0-NDD-ZU-NEXT: # kill: def $ax killed $ax killed $rax
+; O0-NDD-ZU-NEXT: testw %ax, %ax # encoding: [0x66,0x85,0xc0]
+; O0-NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%v0 = and i64 %a, 562941363486720 ; 0xffff << 33
%v1 = icmp ne i64 %v0, 0
ret i1 %v1
@@ -1080,6 +1660,14 @@ define i1 @shifted_mask64_testl(i64 %a) {
; NDD-ZU-NEXT: testl %edi, %edi # encoding: [0x85,0xff]
; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: shifted_mask64_testl:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: shrq $7, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xc1,0xef,0x07]
+; O0-NDD-ZU-NEXT: # kill: def $eax killed $eax killed $rax
+; O0-NDD-ZU-NEXT: testl %eax, %eax # encoding: [0x85,0xc0]
+; O0-NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%v0 = and i64 %a, 549755813760 ; 0xffffffff << 7
%v1 = icmp eq i64 %v0, 0
ret i1 %v1
@@ -1115,6 +1703,17 @@ define i1 @shifted_mask64_extra_use_const(i64 %a) {
; NDD-ZU-NEXT: movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A]
; NDD-ZU-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: shifted_mask64_extra_use_const:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: movabsq $287104476244869120, %rcx # encoding: [0x48,0xb9,0x00,0x00,0x00,0x00,0x00,0x00,0xfc,0x03]
+; O0-NDD-ZU-NEXT: # imm = 0x3FC000000000000
+; O0-NDD-ZU-NEXT: andq %rcx, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x21,0xcf]
+; O0-NDD-ZU-NEXT: testq %rax, %rax # encoding: [0x48,0x85,0xc0]
+; O0-NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; O0-NDD-ZU-NEXT: movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A]
+; O0-NDD-ZU-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%v0 = and i64 %a, 287104476244869120 ; 0xff << 50
%v1 = icmp ne i64 %v0, 0
store i64 287104476244869120, ptr @d64
@@ -1151,6 +1750,16 @@ define i1 @shifted_mask64_extra_use_and(i64 %a) {
; NDD-ZU-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
; NDD-ZU-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: shifted_mask64_extra_use_and:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: movabsq $287104476244869120, %rax # encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0x00,0xfc,0x03]
+; O0-NDD-ZU-NEXT: # imm = 0x3FC000000000000
+; O0-NDD-ZU-NEXT: andq %rax, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x21,0xc7]
+; O0-NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; O0-NDD-ZU-NEXT: movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A]
+; O0-NDD-ZU-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%v0 = and i64 %a, 287104476244869120 ; 0xff << 50
%v1 = icmp ne i64 %v0, 0
store i64 %v0, ptr @d64
@@ -1178,6 +1787,14 @@ define i1 @shifted_mask32_testl_immediate(i64 %a) {
; NDD-ZU-NEXT: # imm = 0x3FC0000
; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: shifted_mask32_testl_immediate:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: movl %edi, %eax # encoding: [0x89,0xf8]
+; O0-NDD-ZU-NEXT: testl $66846720, %eax # encoding: [0xa9,0x00,0x00,0xfc,0x03]
+; O0-NDD-ZU-NEXT: # imm = 0x3FC0000
+; O0-NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%v0 = and i64 %a, 66846720 ; 0xff << 18
%v1 = icmp ne i64 %v0, 0
ret i1 %v1
@@ -1213,6 +1830,17 @@ define i1 @shifted_mask32_extra_use_const(i64 %a) {
; NDD-ZU-NEXT: # fixup A - offset: 3, value: d64-8, kind: reloc_riprel_4byte
; NDD-ZU-NEXT: # imm = 0x3FC0000
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: shifted_mask32_extra_use_const:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: movl %edi, %eax # encoding: [0x89,0xf8]
+; O0-NDD-ZU-NEXT: testl $66846720, %eax # encoding: [0xa9,0x00,0x00,0xfc,0x03]
+; O0-NDD-ZU-NEXT: # imm = 0x3FC0000
+; O0-NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; O0-NDD-ZU-NEXT: movq $66846720, d64(%rip) # encoding: [0x48,0xc7,0x05,A,A,A,A,0x00,0x00,0xfc,0x03]
+; O0-NDD-ZU-NEXT: # fixup A - offset: 3, value: d64-8, kind: reloc_riprel_4byte
+; O0-NDD-ZU-NEXT: # imm = 0x3FC0000
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%v0 = and i64 %a, 66846720 ; 0xff << 18
%v1 = icmp ne i64 %v0, 0
store i64 66846720, ptr @d64
@@ -1246,6 +1874,15 @@ define i1 @shifted_mask32_extra_use_and(i64 %a) {
; NDD-ZU-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
; NDD-ZU-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: shifted_mask32_extra_use_and:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: andq $66846720, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x81,0xe7,0x00,0x00,0xfc,0x03]
+; O0-NDD-ZU-NEXT: # imm = 0x3FC0000
+; O0-NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; O0-NDD-ZU-NEXT: movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A]
+; O0-NDD-ZU-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%v0 = and i64 %a, 66846720 ; 0xff << 50
%v1 = icmp ne i64 %v0, 0
store i64 %v0, ptr @d64
@@ -1277,6 +1914,16 @@ define { i64, i64 } @pr39968(i64, i64, i32) {
; NDD-ZU-NEXT: cmovneq %rdi, %rsi, %rdx # encoding: [0x62,0xf4,0xec,0x18,0x45,0xf7]
; NDD-ZU-NEXT: cmovneq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0x45,0xc7]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: pr39968:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: movb %dl, %cl # encoding: [0x88,0xd1]
+; O0-NDD-ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; O0-NDD-ZU-NEXT: testb $64, %cl # encoding: [0xf6,0xc1,0x40]
+; O0-NDD-ZU-NEXT: cmovneq %rdi, %rsi, %rdx # encoding: [0x62,0xf4,0xec,0x18,0x45,0xf7]
+; O0-NDD-ZU-NEXT: # kill: def $rax killed $eax
+; O0-NDD-ZU-NEXT: cmovneq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0x45,0xc7]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%4 = and i32 %2, 64
%5 = icmp ne i32 %4, 0
%6 = select i1 %5, i64 %0, i64 %1
@@ -1289,17 +1936,69 @@ define { i64, i64 } @pr39968(i64, i64, i32) {
; Make sure we use a 32-bit comparison without an extend based on the input
; being pre-sign extended by caller.
define i32 @pr42189(i16 signext %c) {
-; CHECK-LABEL: pr42189:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: cmpl $32767, %edi # encoding: [0x81,0xff,0xff,0x7f,0x00,0x00]
-; CHECK-NEXT: # imm = 0x7FFF
-; CHECK-NEXT: jne f at PLT # TAILCALL
-; CHECK-NEXT: # encoding: [0x75,A]
-; CHECK-NEXT: # fixup A - offset: 1, value: f at PLT-1, kind: FK_PCRel_1
-; CHECK-NEXT: # %bb.1: # %if.then
-; CHECK-NEXT: jmp g at PLT # TAILCALL
-; CHECK-NEXT: # encoding: [0xeb,A]
-; CHECK-NEXT: # fixup A - offset: 1, value: g at PLT-1, kind: FK_PCRel_1
+; NO-NDD-LABEL: pr42189:
+; NO-NDD: # %bb.0: # %entry
+; NO-NDD-NEXT: cmpl $32767, %edi # encoding: [0x81,0xff,0xff,0x7f,0x00,0x00]
+; NO-NDD-NEXT: # imm = 0x7FFF
+; NO-NDD-NEXT: jne f at PLT # TAILCALL
+; NO-NDD-NEXT: # encoding: [0x75,A]
+; NO-NDD-NEXT: # fixup A - offset: 1, value: f at PLT-1, kind: FK_PCRel_1
+; NO-NDD-NEXT: # %bb.1: # %if.then
+; NO-NDD-NEXT: jmp g at PLT # TAILCALL
+; NO-NDD-NEXT: # encoding: [0xeb,A]
+; NO-NDD-NEXT: # fixup A - offset: 1, value: g at PLT-1, kind: FK_PCRel_1
+;
+; NDD-LABEL: pr42189:
+; NDD: # %bb.0: # %entry
+; NDD-NEXT: cmpl $32767, %edi # encoding: [0x81,0xff,0xff,0x7f,0x00,0x00]
+; NDD-NEXT: # imm = 0x7FFF
+; NDD-NEXT: jne f at PLT # TAILCALL
+; NDD-NEXT: # encoding: [0x75,A]
+; NDD-NEXT: # fixup A - offset: 1, value: f at PLT-1, kind: FK_PCRel_1
+; NDD-NEXT: # %bb.1: # %if.then
+; NDD-NEXT: jmp g at PLT # TAILCALL
+; NDD-NEXT: # encoding: [0xeb,A]
+; NDD-NEXT: # fixup A - offset: 1, value: g at PLT-1, kind: FK_PCRel_1
+;
+; NDD-ZU-LABEL: pr42189:
+; NDD-ZU: # %bb.0: # %entry
+; NDD-ZU-NEXT: cmpl $32767, %edi # encoding: [0x81,0xff,0xff,0x7f,0x00,0x00]
+; NDD-ZU-NEXT: # imm = 0x7FFF
+; NDD-ZU-NEXT: jne f at PLT # TAILCALL
+; NDD-ZU-NEXT: # encoding: [0x75,A]
+; NDD-ZU-NEXT: # fixup A - offset: 1, value: f at PLT-1, kind: FK_PCRel_1
+; NDD-ZU-NEXT: # %bb.1: # %if.then
+; NDD-ZU-NEXT: jmp g at PLT # TAILCALL
+; NDD-ZU-NEXT: # encoding: [0xeb,A]
+; NDD-ZU-NEXT: # fixup A - offset: 1, value: g at PLT-1, kind: FK_PCRel_1
+;
+; O0-NDD-ZU-LABEL: pr42189:
+; O0-NDD-ZU: # %bb.0: # %entry
+; O0-NDD-ZU-NEXT: pushq %rax # encoding: [0x50]
+; O0-NDD-ZU-NEXT: .cfi_def_cfa_offset 16
+; O0-NDD-ZU-NEXT: movw %di, %ax # encoding: [0x66,0x89,0xf8]
+; O0-NDD-ZU-NEXT: cmpw $32767, %ax # encoding: [0x66,0x3d,0xff,0x7f]
+; O0-NDD-ZU-NEXT: # imm = 0x7FFF
+; O0-NDD-ZU-NEXT: jne .LBB45_2 # encoding: [0x75,A]
+; O0-NDD-ZU-NEXT: # fixup A - offset: 1, value: .LBB45_2-1, kind: FK_PCRel_1
+; O0-NDD-ZU-NEXT: # %bb.1: # %if.then
+; O0-NDD-ZU-NEXT: callq g at PLT # encoding: [0xe8,A,A,A,A]
+; O0-NDD-ZU-NEXT: # fixup A - offset: 1, value: g at PLT-4, kind: FK_PCRel_4
+; O0-NDD-ZU-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; O0-NDD-ZU-NEXT: # encoding: [0x89,0x44,0x24,0x04]
+; O0-NDD-ZU-NEXT: jmp .LBB45_3 # encoding: [0xeb,A]
+; O0-NDD-ZU-NEXT: # fixup A - offset: 1, value: .LBB45_3-1, kind: FK_PCRel_1
+; O0-NDD-ZU-NEXT: .LBB45_2: # %if.end
+; O0-NDD-ZU-NEXT: callq f at PLT # encoding: [0xe8,A,A,A,A]
+; O0-NDD-ZU-NEXT: # fixup A - offset: 1, value: f at PLT-4, kind: FK_PCRel_4
+; O0-NDD-ZU-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; O0-NDD-ZU-NEXT: # encoding: [0x89,0x44,0x24,0x04]
+; O0-NDD-ZU-NEXT: .LBB45_3: # %return
+; O0-NDD-ZU-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
+; O0-NDD-ZU-NEXT: # encoding: [0x8b,0x44,0x24,0x04]
+; O0-NDD-ZU-NEXT: popq %rcx # encoding: [0x59]
+; O0-NDD-ZU-NEXT: .cfi_def_cfa_offset 8
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
entry:
%cmp = icmp eq i16 %c, 32767
br i1 %cmp, label %if.then, label %if.end
@@ -1344,6 +2043,15 @@ define i1 @fold_test_and_with_chain(ptr %x, ptr %y, i32 %z) {
; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NDD-ZU-NEXT: movl %edx, (%rsi) # encoding: [0x89,0x16]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: fold_test_and_with_chain:
+; O0-NDD-ZU: # %bb.0:
+; O0-NDD-ZU-NEXT: movl (%rdi), %eax # encoding: [0x8b,0x07]
+; O0-NDD-ZU-NEXT: andl %edx, %eax # EVEX TO LEGACY Compression encoding: [0x21,0xd0]
+; O0-NDD-ZU-NEXT: testl %eax, %eax # encoding: [0x85,0xc0]
+; O0-NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; O0-NDD-ZU-NEXT: movl %edx, (%rsi) # encoding: [0x89,0x16]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
%a = load i32, ptr %x
%b = and i32 %z, %a
%c = icmp eq i32 %b, 0
diff --git a/llvm/test/CodeGen/X86/fast-isel-fcmp.ll b/llvm/test/CodeGen/X86/fast-isel-fcmp.ll
index b9ef3154cd1c3..7202de45d6d2f 100644
--- a/llvm/test/CodeGen/X86/fast-isel-fcmp.ll
+++ b/llvm/test/CodeGen/X86/fast-isel-fcmp.ll
@@ -3,6 +3,7 @@
; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=x86_64-apple-darwin10 | FileCheck %s --check-prefixes=FAST,FAST_NOAVX
; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=x86_64-apple-darwin10 -mattr=avx | FileCheck %s --check-prefixes=FAST,FAST_AVX
; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=x86_64-apple-darwin10 -mattr=avx512f | FileCheck %s --check-prefixes=FAST,FAST_AVX
+; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=x86_64-apple-darwin10 -mattr=zu | FileCheck %s --check-prefix=FAST_ZU
define zeroext i1 @fcmp_oeq(float %x, float %y) {
; SDAG-LABEL: fcmp_oeq:
@@ -30,6 +31,15 @@ define zeroext i1 @fcmp_oeq(float %x, float %y) {
; FAST_AVX-NEXT: andb %cl, %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_oeq:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: ucomiss %xmm1, %xmm0
+; FAST_ZU-NEXT: setzue %cl
+; FAST_ZU-NEXT: setzunp %al
+; FAST_ZU-NEXT: andb %cl, %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp oeq float %x, %y
ret i1 %1
}
@@ -54,6 +64,13 @@ define zeroext i1 @fcmp_ogt(float %x, float %y) {
; FAST_AVX-NEXT: seta %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_ogt:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: ucomiss %xmm1, %xmm0
+; FAST_ZU-NEXT: setzua %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp ogt float %x, %y
ret i1 %1
}
@@ -78,6 +95,13 @@ define zeroext i1 @fcmp_oge(float %x, float %y) {
; FAST_AVX-NEXT: setae %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_oge:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: ucomiss %xmm1, %xmm0
+; FAST_ZU-NEXT: setzuae %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp oge float %x, %y
ret i1 %1
}
@@ -102,6 +126,13 @@ define zeroext i1 @fcmp_olt(float %x, float %y) {
; FAST_AVX-NEXT: seta %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_olt:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: ucomiss %xmm0, %xmm1
+; FAST_ZU-NEXT: setzua %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp olt float %x, %y
ret i1 %1
}
@@ -126,6 +157,13 @@ define zeroext i1 @fcmp_ole(float %x, float %y) {
; FAST_AVX-NEXT: setae %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_ole:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: ucomiss %xmm0, %xmm1
+; FAST_ZU-NEXT: setzuae %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp ole float %x, %y
ret i1 %1
}
@@ -150,6 +188,13 @@ define zeroext i1 @fcmp_one(float %x, float %y) {
; FAST_AVX-NEXT: setne %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_one:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: ucomiss %xmm1, %xmm0
+; FAST_ZU-NEXT: setzune %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp one float %x, %y
ret i1 %1
}
@@ -174,6 +219,13 @@ define zeroext i1 @fcmp_ord(float %x, float %y) {
; FAST_AVX-NEXT: setnp %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_ord:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: ucomiss %xmm1, %xmm0
+; FAST_ZU-NEXT: setzunp %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp ord float %x, %y
ret i1 %1
}
@@ -198,6 +250,13 @@ define zeroext i1 @fcmp_uno(float %x, float %y) {
; FAST_AVX-NEXT: setp %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_uno:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: ucomiss %xmm1, %xmm0
+; FAST_ZU-NEXT: setzup %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp uno float %x, %y
ret i1 %1
}
@@ -222,6 +281,13 @@ define zeroext i1 @fcmp_ueq(float %x, float %y) {
; FAST_AVX-NEXT: sete %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_ueq:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: ucomiss %xmm1, %xmm0
+; FAST_ZU-NEXT: setzue %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp ueq float %x, %y
ret i1 %1
}
@@ -246,6 +312,13 @@ define zeroext i1 @fcmp_ugt(float %x, float %y) {
; FAST_AVX-NEXT: setb %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_ugt:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: ucomiss %xmm0, %xmm1
+; FAST_ZU-NEXT: setzub %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp ugt float %x, %y
ret i1 %1
}
@@ -270,6 +343,13 @@ define zeroext i1 @fcmp_uge(float %x, float %y) {
; FAST_AVX-NEXT: setbe %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_uge:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: ucomiss %xmm0, %xmm1
+; FAST_ZU-NEXT: setzube %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp uge float %x, %y
ret i1 %1
}
@@ -294,6 +374,13 @@ define zeroext i1 @fcmp_ult(float %x, float %y) {
; FAST_AVX-NEXT: setb %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_ult:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: ucomiss %xmm1, %xmm0
+; FAST_ZU-NEXT: setzub %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp ult float %x, %y
ret i1 %1
}
@@ -318,6 +405,13 @@ define zeroext i1 @fcmp_ule(float %x, float %y) {
; FAST_AVX-NEXT: setbe %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_ule:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: ucomiss %xmm1, %xmm0
+; FAST_ZU-NEXT: setzube %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp ule float %x, %y
ret i1 %1
}
@@ -348,6 +442,15 @@ define zeroext i1 @fcmp_une(float %x, float %y) {
; FAST_AVX-NEXT: orb %cl, %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_une:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: ucomiss %xmm1, %xmm0
+; FAST_ZU-NEXT: setzune %cl
+; FAST_ZU-NEXT: setzup %al
+; FAST_ZU-NEXT: orb %cl, %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp une float %x, %y
ret i1 %1
}
@@ -365,6 +468,13 @@ define zeroext i1 @icmp_eq(i32 %x, i32 %y) {
; FAST-NEXT: sete %al
; FAST-NEXT: andb $1, %al
; FAST-NEXT: retq
+;
+; FAST_ZU-LABEL: icmp_eq:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: cmpl %esi, %edi
+; FAST_ZU-NEXT: setzue %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = icmp eq i32 %x, %y
ret i1 %1
}
@@ -382,6 +492,13 @@ define zeroext i1 @icmp_ne(i32 %x, i32 %y) {
; FAST-NEXT: setne %al
; FAST-NEXT: andb $1, %al
; FAST-NEXT: retq
+;
+; FAST_ZU-LABEL: icmp_ne:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: cmpl %esi, %edi
+; FAST_ZU-NEXT: setzune %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = icmp ne i32 %x, %y
ret i1 %1
}
@@ -399,6 +516,13 @@ define zeroext i1 @icmp_ugt(i32 %x, i32 %y) {
; FAST-NEXT: seta %al
; FAST-NEXT: andb $1, %al
; FAST-NEXT: retq
+;
+; FAST_ZU-LABEL: icmp_ugt:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: cmpl %esi, %edi
+; FAST_ZU-NEXT: setzua %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = icmp ugt i32 %x, %y
ret i1 %1
}
@@ -416,6 +540,13 @@ define zeroext i1 @icmp_uge(i32 %x, i32 %y) {
; FAST-NEXT: setae %al
; FAST-NEXT: andb $1, %al
; FAST-NEXT: retq
+;
+; FAST_ZU-LABEL: icmp_uge:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: cmpl %esi, %edi
+; FAST_ZU-NEXT: setzuae %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = icmp uge i32 %x, %y
ret i1 %1
}
@@ -433,6 +564,13 @@ define zeroext i1 @icmp_ult(i32 %x, i32 %y) {
; FAST-NEXT: setb %al
; FAST-NEXT: andb $1, %al
; FAST-NEXT: retq
+;
+; FAST_ZU-LABEL: icmp_ult:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: cmpl %esi, %edi
+; FAST_ZU-NEXT: setzub %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = icmp ult i32 %x, %y
ret i1 %1
}
@@ -450,6 +588,13 @@ define zeroext i1 @icmp_ule(i32 %x, i32 %y) {
; FAST-NEXT: setbe %al
; FAST-NEXT: andb $1, %al
; FAST-NEXT: retq
+;
+; FAST_ZU-LABEL: icmp_ule:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: cmpl %esi, %edi
+; FAST_ZU-NEXT: setzube %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = icmp ule i32 %x, %y
ret i1 %1
}
@@ -467,6 +612,13 @@ define zeroext i1 @icmp_sgt(i32 %x, i32 %y) {
; FAST-NEXT: setg %al
; FAST-NEXT: andb $1, %al
; FAST-NEXT: retq
+;
+; FAST_ZU-LABEL: icmp_sgt:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: cmpl %esi, %edi
+; FAST_ZU-NEXT: setzug %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = icmp sgt i32 %x, %y
ret i1 %1
}
@@ -484,6 +636,13 @@ define zeroext i1 @icmp_sge(i32 %x, i32 %y) {
; FAST-NEXT: setge %al
; FAST-NEXT: andb $1, %al
; FAST-NEXT: retq
+;
+; FAST_ZU-LABEL: icmp_sge:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: cmpl %esi, %edi
+; FAST_ZU-NEXT: setzuge %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = icmp sge i32 %x, %y
ret i1 %1
}
@@ -501,6 +660,13 @@ define zeroext i1 @icmp_slt(i32 %x, i32 %y) {
; FAST-NEXT: setl %al
; FAST-NEXT: andb $1, %al
; FAST-NEXT: retq
+;
+; FAST_ZU-LABEL: icmp_slt:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: cmpl %esi, %edi
+; FAST_ZU-NEXT: setzul %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = icmp slt i32 %x, %y
ret i1 %1
}
@@ -518,6 +684,13 @@ define zeroext i1 @icmp_sle(i32 %x, i32 %y) {
; FAST-NEXT: setle %al
; FAST-NEXT: andb $1, %al
; FAST-NEXT: retq
+;
+; FAST_ZU-LABEL: icmp_sle:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: cmpl %esi, %edi
+; FAST_ZU-NEXT: setzule %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = icmp sle i32 %x, %y
ret i1 %1
}
@@ -543,6 +716,13 @@ define zeroext i1 @fcmp_oeq2(float %x) {
; FAST_AVX-NEXT: setnp %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_oeq2:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: ucomiss %xmm0, %xmm0
+; FAST_ZU-NEXT: setzunp %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp oeq float %x, %x
ret i1 %1
}
@@ -576,6 +756,16 @@ define zeroext i1 @fcmp_oeq3(float %x) {
; FAST_AVX-NEXT: andb %cl, %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_oeq3:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: xorps %xmm1, %xmm1
+; FAST_ZU-NEXT: ucomiss %xmm1, %xmm0
+; FAST_ZU-NEXT: setzue %cl
+; FAST_ZU-NEXT: setzunp %al
+; FAST_ZU-NEXT: andb %cl, %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp oeq float %x, 0.000000e+00
ret i1 %1
}
@@ -592,6 +782,13 @@ define zeroext i1 @fcmp_ogt2(float %x) {
; FAST-NEXT: andb $1, %al
; FAST-NEXT: ## kill: def $al killed $al killed $eax
; FAST-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_ogt2:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: xorl %eax, %eax
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: ## kill: def $al killed $al killed $eax
+; FAST_ZU-NEXT: retq
%1 = fcmp ogt float %x, %x
ret i1 %1
}
@@ -619,6 +816,14 @@ define zeroext i1 @fcmp_ogt3(float %x) {
; FAST_AVX-NEXT: seta %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_ogt3:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: xorps %xmm1, %xmm1
+; FAST_ZU-NEXT: ucomiss %xmm1, %xmm0
+; FAST_ZU-NEXT: setzua %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp ogt float %x, 0.000000e+00
ret i1 %1
}
@@ -643,6 +848,13 @@ define zeroext i1 @fcmp_oge2(float %x) {
; FAST_AVX-NEXT: setnp %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_oge2:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: ucomiss %xmm0, %xmm0
+; FAST_ZU-NEXT: setzunp %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp oge float %x, %x
ret i1 %1
}
@@ -670,6 +882,14 @@ define zeroext i1 @fcmp_oge3(float %x) {
; FAST_AVX-NEXT: setae %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_oge3:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: xorps %xmm1, %xmm1
+; FAST_ZU-NEXT: ucomiss %xmm1, %xmm0
+; FAST_ZU-NEXT: setzuae %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp oge float %x, 0.000000e+00
ret i1 %1
}
@@ -686,6 +906,13 @@ define zeroext i1 @fcmp_olt2(float %x) {
; FAST-NEXT: andb $1, %al
; FAST-NEXT: ## kill: def $al killed $al killed $eax
; FAST-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_olt2:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: xorl %eax, %eax
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: ## kill: def $al killed $al killed $eax
+; FAST_ZU-NEXT: retq
%1 = fcmp olt float %x, %x
ret i1 %1
}
@@ -713,6 +940,14 @@ define zeroext i1 @fcmp_olt3(float %x) {
; FAST_AVX-NEXT: seta %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_olt3:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: xorps %xmm1, %xmm1
+; FAST_ZU-NEXT: ucomiss %xmm0, %xmm1
+; FAST_ZU-NEXT: setzua %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp olt float %x, 0.000000e+00
ret i1 %1
}
@@ -737,6 +972,13 @@ define zeroext i1 @fcmp_ole2(float %x) {
; FAST_AVX-NEXT: setnp %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_ole2:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: ucomiss %xmm0, %xmm0
+; FAST_ZU-NEXT: setzunp %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp ole float %x, %x
ret i1 %1
}
@@ -764,6 +1006,14 @@ define zeroext i1 @fcmp_ole3(float %x) {
; FAST_AVX-NEXT: setae %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_ole3:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: xorps %xmm1, %xmm1
+; FAST_ZU-NEXT: ucomiss %xmm0, %xmm1
+; FAST_ZU-NEXT: setzuae %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp ole float %x, 0.000000e+00
ret i1 %1
}
@@ -780,6 +1030,13 @@ define zeroext i1 @fcmp_one2(float %x) {
; FAST-NEXT: andb $1, %al
; FAST-NEXT: ## kill: def $al killed $al killed $eax
; FAST-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_one2:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: xorl %eax, %eax
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: ## kill: def $al killed $al killed $eax
+; FAST_ZU-NEXT: retq
%1 = fcmp one float %x, %x
ret i1 %1
}
@@ -807,6 +1064,14 @@ define zeroext i1 @fcmp_one3(float %x) {
; FAST_AVX-NEXT: setne %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_one3:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: xorps %xmm1, %xmm1
+; FAST_ZU-NEXT: ucomiss %xmm1, %xmm0
+; FAST_ZU-NEXT: setzune %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp one float %x, 0.000000e+00
ret i1 %1
}
@@ -831,6 +1096,13 @@ define zeroext i1 @fcmp_ord2(float %x) {
; FAST_AVX-NEXT: setnp %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_ord2:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: ucomiss %xmm0, %xmm0
+; FAST_ZU-NEXT: setzunp %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp ord float %x, %x
ret i1 %1
}
@@ -855,6 +1127,13 @@ define zeroext i1 @fcmp_ord3(float %x) {
; FAST_AVX-NEXT: setnp %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_ord3:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: ucomiss %xmm0, %xmm0
+; FAST_ZU-NEXT: setzunp %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp ord float %x, 0.000000e+00
ret i1 %1
}
@@ -879,6 +1158,13 @@ define zeroext i1 @fcmp_uno2(float %x) {
; FAST_AVX-NEXT: setp %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_uno2:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: ucomiss %xmm0, %xmm0
+; FAST_ZU-NEXT: setzup %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp uno float %x, %x
ret i1 %1
}
@@ -903,6 +1189,13 @@ define zeroext i1 @fcmp_uno3(float %x) {
; FAST_AVX-NEXT: setp %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_uno3:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: ucomiss %xmm0, %xmm0
+; FAST_ZU-NEXT: setzup %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp uno float %x, 0.000000e+00
ret i1 %1
}
@@ -918,6 +1211,12 @@ define zeroext i1 @fcmp_ueq2(float %x) {
; FAST-NEXT: movb $1, %al
; FAST-NEXT: andb $1, %al
; FAST-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_ueq2:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: movb $1, %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp ueq float %x, %x
ret i1 %1
}
@@ -945,6 +1244,14 @@ define zeroext i1 @fcmp_ueq3(float %x) {
; FAST_AVX-NEXT: sete %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_ueq3:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: xorps %xmm1, %xmm1
+; FAST_ZU-NEXT: ucomiss %xmm1, %xmm0
+; FAST_ZU-NEXT: setzue %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp ueq float %x, 0.000000e+00
ret i1 %1
}
@@ -969,6 +1276,13 @@ define zeroext i1 @fcmp_ugt2(float %x) {
; FAST_AVX-NEXT: setp %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_ugt2:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: ucomiss %xmm0, %xmm0
+; FAST_ZU-NEXT: setzup %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp ugt float %x, %x
ret i1 %1
}
@@ -996,6 +1310,14 @@ define zeroext i1 @fcmp_ugt3(float %x) {
; FAST_AVX-NEXT: setb %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_ugt3:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: xorps %xmm1, %xmm1
+; FAST_ZU-NEXT: ucomiss %xmm0, %xmm1
+; FAST_ZU-NEXT: setzub %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp ugt float %x, 0.000000e+00
ret i1 %1
}
@@ -1011,6 +1333,12 @@ define zeroext i1 @fcmp_uge2(float %x) {
; FAST-NEXT: movb $1, %al
; FAST-NEXT: andb $1, %al
; FAST-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_uge2:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: movb $1, %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp uge float %x, %x
ret i1 %1
}
@@ -1038,6 +1366,14 @@ define zeroext i1 @fcmp_uge3(float %x) {
; FAST_AVX-NEXT: setbe %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_uge3:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: xorps %xmm1, %xmm1
+; FAST_ZU-NEXT: ucomiss %xmm0, %xmm1
+; FAST_ZU-NEXT: setzube %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp uge float %x, 0.000000e+00
ret i1 %1
}
@@ -1062,6 +1398,13 @@ define zeroext i1 @fcmp_ult2(float %x) {
; FAST_AVX-NEXT: setp %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_ult2:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: ucomiss %xmm0, %xmm0
+; FAST_ZU-NEXT: setzup %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp ult float %x, %x
ret i1 %1
}
@@ -1089,6 +1432,14 @@ define zeroext i1 @fcmp_ult3(float %x) {
; FAST_AVX-NEXT: setb %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_ult3:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: xorps %xmm1, %xmm1
+; FAST_ZU-NEXT: ucomiss %xmm1, %xmm0
+; FAST_ZU-NEXT: setzub %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp ult float %x, 0.000000e+00
ret i1 %1
}
@@ -1104,6 +1455,12 @@ define zeroext i1 @fcmp_ule2(float %x) {
; FAST-NEXT: movb $1, %al
; FAST-NEXT: andb $1, %al
; FAST-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_ule2:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: movb $1, %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp ule float %x, %x
ret i1 %1
}
@@ -1131,6 +1488,14 @@ define zeroext i1 @fcmp_ule3(float %x) {
; FAST_AVX-NEXT: setbe %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_ule3:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: xorps %xmm1, %xmm1
+; FAST_ZU-NEXT: ucomiss %xmm1, %xmm0
+; FAST_ZU-NEXT: setzube %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp ule float %x, 0.000000e+00
ret i1 %1
}
@@ -1155,6 +1520,13 @@ define zeroext i1 @fcmp_une2(float %x) {
; FAST_AVX-NEXT: setp %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_une2:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: ucomiss %xmm0, %xmm0
+; FAST_ZU-NEXT: setzup %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp une float %x, %x
ret i1 %1
}
@@ -1188,6 +1560,16 @@ define zeroext i1 @fcmp_une3(float %x) {
; FAST_AVX-NEXT: orb %cl, %al
; FAST_AVX-NEXT: andb $1, %al
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: fcmp_une3:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: xorps %xmm1, %xmm1
+; FAST_ZU-NEXT: ucomiss %xmm1, %xmm0
+; FAST_ZU-NEXT: setzune %cl
+; FAST_ZU-NEXT: setzup %al
+; FAST_ZU-NEXT: orb %cl, %al
+; FAST_ZU-NEXT: andb $1, %al
+; FAST_ZU-NEXT: retq
%1 = fcmp une float %x, 0.000000e+00
ret i1 %1
}
diff --git a/llvm/test/CodeGen/X86/fast-isel-select-cmov2.ll b/llvm/test/CodeGen/X86/fast-isel-select-cmov2.ll
index eb2bd08a2b14c..b58a5f72a5c4d 100644
--- a/llvm/test/CodeGen/X86/fast-isel-select-cmov2.ll
+++ b/llvm/test/CodeGen/X86/fast-isel-select-cmov2.ll
@@ -3,6 +3,7 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=CHECK --check-prefix=NOAVX --check-prefix=FAST
; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort=1 -mattr=avx | FileCheck %s --check-prefix=CHECK --check-prefix=FAST_AVX
; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort=1 -mattr=avx512f | FileCheck %s --check-prefix=CHECK --check-prefix=FAST_AVX
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort=1 -mattr=zu | FileCheck %s --check-prefix=CHECK --check-prefix=FAST_ZU
; Test all the cmp predicates that can feed an integer conditional move.
@@ -44,6 +45,16 @@ define i64 @select_fcmp_oeq_cmov(double %a, double %b, i64 %c, i64 %d) {
; FAST_AVX-NEXT: testb %cl, %dl
; FAST_AVX-NEXT: cmoveq %rsi, %rax
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: select_fcmp_oeq_cmov:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: movq %rdi, %rax
+; FAST_ZU-NEXT: ucomisd %xmm1, %xmm0
+; FAST_ZU-NEXT: setzunp %cl
+; FAST_ZU-NEXT: setzue %dl
+; FAST_ZU-NEXT: testb %cl, %dl
+; FAST_ZU-NEXT: cmoveq %rsi, %rax
+; FAST_ZU-NEXT: retq
%1 = fcmp oeq double %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
@@ -63,6 +74,13 @@ define i64 @select_fcmp_ogt_cmov(double %a, double %b, i64 %c, i64 %d) {
; FAST_AVX-NEXT: vucomisd %xmm1, %xmm0
; FAST_AVX-NEXT: cmovbeq %rsi, %rax
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: select_fcmp_ogt_cmov:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: movq %rdi, %rax
+; FAST_ZU-NEXT: ucomisd %xmm1, %xmm0
+; FAST_ZU-NEXT: cmovbeq %rsi, %rax
+; FAST_ZU-NEXT: retq
%1 = fcmp ogt double %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
@@ -82,6 +100,13 @@ define i64 @select_fcmp_oge_cmov(double %a, double %b, i64 %c, i64 %d) {
; FAST_AVX-NEXT: vucomisd %xmm1, %xmm0
; FAST_AVX-NEXT: cmovbq %rsi, %rax
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: select_fcmp_oge_cmov:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: movq %rdi, %rax
+; FAST_ZU-NEXT: ucomisd %xmm1, %xmm0
+; FAST_ZU-NEXT: cmovbq %rsi, %rax
+; FAST_ZU-NEXT: retq
%1 = fcmp oge double %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
@@ -101,6 +126,13 @@ define i64 @select_fcmp_olt_cmov(double %a, double %b, i64 %c, i64 %d) {
; FAST_AVX-NEXT: vucomisd %xmm0, %xmm1
; FAST_AVX-NEXT: cmovbeq %rsi, %rax
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: select_fcmp_olt_cmov:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: movq %rdi, %rax
+; FAST_ZU-NEXT: ucomisd %xmm0, %xmm1
+; FAST_ZU-NEXT: cmovbeq %rsi, %rax
+; FAST_ZU-NEXT: retq
%1 = fcmp olt double %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
@@ -120,6 +152,13 @@ define i64 @select_fcmp_ole_cmov(double %a, double %b, i64 %c, i64 %d) {
; FAST_AVX-NEXT: vucomisd %xmm0, %xmm1
; FAST_AVX-NEXT: cmovbq %rsi, %rax
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: select_fcmp_ole_cmov:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: movq %rdi, %rax
+; FAST_ZU-NEXT: ucomisd %xmm0, %xmm1
+; FAST_ZU-NEXT: cmovbq %rsi, %rax
+; FAST_ZU-NEXT: retq
%1 = fcmp ole double %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
@@ -139,6 +178,13 @@ define i64 @select_fcmp_one_cmov(double %a, double %b, i64 %c, i64 %d) {
; FAST_AVX-NEXT: vucomisd %xmm1, %xmm0
; FAST_AVX-NEXT: cmoveq %rsi, %rax
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: select_fcmp_one_cmov:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: movq %rdi, %rax
+; FAST_ZU-NEXT: ucomisd %xmm1, %xmm0
+; FAST_ZU-NEXT: cmoveq %rsi, %rax
+; FAST_ZU-NEXT: retq
%1 = fcmp one double %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
@@ -158,6 +204,13 @@ define i64 @select_fcmp_ord_cmov(double %a, double %b, i64 %c, i64 %d) {
; FAST_AVX-NEXT: vucomisd %xmm1, %xmm0
; FAST_AVX-NEXT: cmovpq %rsi, %rax
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: select_fcmp_ord_cmov:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: movq %rdi, %rax
+; FAST_ZU-NEXT: ucomisd %xmm1, %xmm0
+; FAST_ZU-NEXT: cmovpq %rsi, %rax
+; FAST_ZU-NEXT: retq
%1 = fcmp ord double %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
@@ -177,6 +230,13 @@ define i64 @select_fcmp_uno_cmov(double %a, double %b, i64 %c, i64 %d) {
; FAST_AVX-NEXT: vucomisd %xmm1, %xmm0
; FAST_AVX-NEXT: cmovnpq %rsi, %rax
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: select_fcmp_uno_cmov:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: movq %rdi, %rax
+; FAST_ZU-NEXT: ucomisd %xmm1, %xmm0
+; FAST_ZU-NEXT: cmovnpq %rsi, %rax
+; FAST_ZU-NEXT: retq
%1 = fcmp uno double %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
@@ -196,6 +256,13 @@ define i64 @select_fcmp_ueq_cmov(double %a, double %b, i64 %c, i64 %d) {
; FAST_AVX-NEXT: vucomisd %xmm1, %xmm0
; FAST_AVX-NEXT: cmovneq %rsi, %rax
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: select_fcmp_ueq_cmov:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: movq %rdi, %rax
+; FAST_ZU-NEXT: ucomisd %xmm1, %xmm0
+; FAST_ZU-NEXT: cmovneq %rsi, %rax
+; FAST_ZU-NEXT: retq
%1 = fcmp ueq double %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
@@ -215,6 +282,13 @@ define i64 @select_fcmp_ugt_cmov(double %a, double %b, i64 %c, i64 %d) {
; FAST_AVX-NEXT: vucomisd %xmm0, %xmm1
; FAST_AVX-NEXT: cmovaeq %rsi, %rax
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: select_fcmp_ugt_cmov:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: movq %rdi, %rax
+; FAST_ZU-NEXT: ucomisd %xmm0, %xmm1
+; FAST_ZU-NEXT: cmovaeq %rsi, %rax
+; FAST_ZU-NEXT: retq
%1 = fcmp ugt double %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
@@ -234,6 +308,13 @@ define i64 @select_fcmp_uge_cmov(double %a, double %b, i64 %c, i64 %d) {
; FAST_AVX-NEXT: vucomisd %xmm0, %xmm1
; FAST_AVX-NEXT: cmovaq %rsi, %rax
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: select_fcmp_uge_cmov:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: movq %rdi, %rax
+; FAST_ZU-NEXT: ucomisd %xmm0, %xmm1
+; FAST_ZU-NEXT: cmovaq %rsi, %rax
+; FAST_ZU-NEXT: retq
%1 = fcmp uge double %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
@@ -253,6 +334,13 @@ define i64 @select_fcmp_ult_cmov(double %a, double %b, i64 %c, i64 %d) {
; FAST_AVX-NEXT: vucomisd %xmm1, %xmm0
; FAST_AVX-NEXT: cmovaeq %rsi, %rax
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: select_fcmp_ult_cmov:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: movq %rdi, %rax
+; FAST_ZU-NEXT: ucomisd %xmm1, %xmm0
+; FAST_ZU-NEXT: cmovaeq %rsi, %rax
+; FAST_ZU-NEXT: retq
%1 = fcmp ult double %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
@@ -272,6 +360,13 @@ define i64 @select_fcmp_ule_cmov(double %a, double %b, i64 %c, i64 %d) {
; FAST_AVX-NEXT: vucomisd %xmm1, %xmm0
; FAST_AVX-NEXT: cmovaq %rsi, %rax
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: select_fcmp_ule_cmov:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: movq %rdi, %rax
+; FAST_ZU-NEXT: ucomisd %xmm1, %xmm0
+; FAST_ZU-NEXT: cmovaq %rsi, %rax
+; FAST_ZU-NEXT: retq
%1 = fcmp ule double %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
@@ -305,6 +400,16 @@ define i64 @select_fcmp_une_cmov(double %a, double %b, i64 %c, i64 %d) {
; FAST_AVX-NEXT: orb %cl, %dl
; FAST_AVX-NEXT: cmoveq %rsi, %rax
; FAST_AVX-NEXT: retq
+;
+; FAST_ZU-LABEL: select_fcmp_une_cmov:
+; FAST_ZU: ## %bb.0:
+; FAST_ZU-NEXT: movq %rdi, %rax
+; FAST_ZU-NEXT: ucomisd %xmm1, %xmm0
+; FAST_ZU-NEXT: setzup %cl
+; FAST_ZU-NEXT: setzune %dl
+; FAST_ZU-NEXT: orb %cl, %dl
+; FAST_ZU-NEXT: cmoveq %rsi, %rax
+; FAST_ZU-NEXT: retq
%1 = fcmp une double %a, %b
%2 = select i1 %1, i64 %c, i64 %d
ret i64 %2
diff --git a/llvm/test/CodeGen/X86/pr27591.ll b/llvm/test/CodeGen/X86/pr27591.ll
index c3c15e7bac959..02eab190a47c5 100644
--- a/llvm/test/CodeGen/X86/pr27591.ll
+++ b/llvm/test/CodeGen/X86/pr27591.ll
@@ -1,5 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -o - -O0 < %s | FileCheck %s
+; RUN: llc -mattr=zu -o - -O0 < %s | FileCheck %s -check-prefix=ZU
+
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
@@ -14,6 +16,17 @@ define void @test1(i32 %x) #0 {
; CHECK-NEXT: callq callee1 at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
+;
+; ZU-LABEL: test1:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: pushq %rax
+; ZU-NEXT: cmpl $0, %edi
+; ZU-NEXT: setzune %al
+; ZU-NEXT: movzbl %al, %edi
+; ZU-NEXT: andl $1, %edi
+; ZU-NEXT: callq callee1 at PLT
+; ZU-NEXT: popq %rax
+; ZU-NEXT: retq
entry:
%tobool = icmp ne i32 %x, 0
call void @callee1(i1 zeroext %tobool)
@@ -32,6 +45,18 @@ define void @test2(i32 %x) #0 {
; CHECK-NEXT: callq callee2 at PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
+;
+; ZU-LABEL: test2:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: pushq %rax
+; ZU-NEXT: cmpl $0, %edi
+; ZU-NEXT: setzune %al
+; ZU-NEXT: movzbl %al, %edi
+; ZU-NEXT: andl $1, %edi
+; ZU-NEXT: negl %edi
+; ZU-NEXT: callq callee2 at PLT
+; ZU-NEXT: popq %rax
+; ZU-NEXT: retq
entry:
%tobool = icmp ne i32 %x, 0
call void @callee2(i1 signext %tobool)
diff --git a/llvm/test/CodeGen/X86/pr32284.ll b/llvm/test/CodeGen/X86/pr32284.ll
index 8a726a469b61e..2bf524d0b75e1 100644
--- a/llvm/test/CodeGen/X86/pr32284.ll
+++ b/llvm/test/CodeGen/X86/pr32284.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 -mtriple=x86_64-unknown -mcpu=skx -o - %s | FileCheck %s --check-prefix=X64-O0
; RUN: llc -mtriple=x86_64-unknown -mcpu=skx -o - %s | FileCheck %s --check-prefix=X64
+; RUN: llc -O0 -mtriple=x86_64-unknown -mcpu=skx -mattr=zu -o - %s | FileCheck %s --check-prefix=X64-O0-ZU
+; RUN: llc -mtriple=x86_64-unknown -mcpu=skx -mattr=zu -o - %s | FileCheck %s --check-prefix=X64-ZU
; RUN: llc -O0 -mtriple=i686-unknown -mcpu=skx -o - %s | FileCheck %s --check-prefix=X86-O0
; RUN: llc -mtriple=i686-unknown -mcpu=skx -o - %s | FileCheck %s --check-prefix=X86
@@ -48,6 +50,45 @@ define void @foo() {
; X64-NEXT: movl %edx, -{{[0-9]+}}(%rsp)
; X64-NEXT: retq
;
+; X64-O0-ZU-LABEL: foo:
+; X64-O0-ZU: # %bb.0: # %entry
+; X64-O0-ZU-NEXT: movzbl c, %ecx
+; X64-O0-ZU-NEXT: xorl %eax, %eax
+; X64-O0-ZU-NEXT: subl %ecx, %eax
+; X64-O0-ZU-NEXT: movslq %eax, %rcx
+; X64-O0-ZU-NEXT: xorl %eax, %eax
+; X64-O0-ZU-NEXT: # kill: def $rax killed $eax
+; X64-O0-ZU-NEXT: subq %rcx, %rax
+; X64-O0-ZU-NEXT: # kill: def $al killed $al killed $rax
+; X64-O0-ZU-NEXT: cmpb $0, %al
+; X64-O0-ZU-NEXT: setzune %al
+; X64-O0-ZU-NEXT: andb $1, %al
+; X64-O0-ZU-NEXT: movb %al, -{{[0-9]+}}(%rsp)
+; X64-O0-ZU-NEXT: cmpb $0, c
+; X64-O0-ZU-NEXT: setzune %al
+; X64-O0-ZU-NEXT: xorb $-1, %al
+; X64-O0-ZU-NEXT: xorb $-1, %al
+; X64-O0-ZU-NEXT: andb $1, %al
+; X64-O0-ZU-NEXT: movzbl %al, %eax
+; X64-O0-ZU-NEXT: movzbl c, %ecx
+; X64-O0-ZU-NEXT: cmpl %ecx, %eax
+; X64-O0-ZU-NEXT: setzule %al
+; X64-O0-ZU-NEXT: andb $1, %al
+; X64-O0-ZU-NEXT: movzbl %al, %eax
+; X64-O0-ZU-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
+; X64-O0-ZU-NEXT: retq
+;
+; X64-ZU-LABEL: foo:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movzbl c(%rip), %eax
+; X64-ZU-NEXT: testl %eax, %eax
+; X64-ZU-NEXT: setzune %cl
+; X64-ZU-NEXT: setne -{{[0-9]+}}(%rsp)
+; X64-ZU-NEXT: cmpl %eax, %ecx
+; X64-ZU-NEXT: setzule %al
+; X64-ZU-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
+; X64-ZU-NEXT: retq
+;
; X86-O0-LABEL: foo:
; X86-O0: # %bb.0: # %entry
; X86-O0-NEXT: subl $8, %esp
@@ -175,6 +216,59 @@ define void @f1() {
; X64-NEXT: movq %rcx, _ZN8struct_210member_2_0E(%rip)
; X64-NEXT: retq
;
+; X64-O0-ZU-LABEL: f1:
+; X64-O0-ZU: # %bb.0: # %entry
+; X64-O0-ZU-NEXT: movslq var_5, %rax
+; X64-O0-ZU-NEXT: movabsq $8381627093, %rcx # imm = 0x1F3957AD5
+; X64-O0-ZU-NEXT: addq %rcx, %rax
+; X64-O0-ZU-NEXT: cmpq $0, %rax
+; X64-O0-ZU-NEXT: setzune %al
+; X64-O0-ZU-NEXT: andb $1, %al
+; X64-O0-ZU-NEXT: movb %al, -{{[0-9]+}}(%rsp)
+; X64-O0-ZU-NEXT: movl var_5, %eax
+; X64-O0-ZU-NEXT: xorl $-1, %eax
+; X64-O0-ZU-NEXT: cmpl $0, %eax
+; X64-O0-ZU-NEXT: setzune %al
+; X64-O0-ZU-NEXT: xorb $-1, %al
+; X64-O0-ZU-NEXT: andb $1, %al
+; X64-O0-ZU-NEXT: movzbl %al, %eax
+; X64-O0-ZU-NEXT: # kill: def $rax killed $eax
+; X64-O0-ZU-NEXT: movslq var_5, %rcx
+; X64-O0-ZU-NEXT: addq $7093, %rcx # imm = 0x1BB5
+; X64-O0-ZU-NEXT: cmpq %rcx, %rax
+; X64-O0-ZU-NEXT: setzug %al
+; X64-O0-ZU-NEXT: andb $1, %al
+; X64-O0-ZU-NEXT: movzbl %al, %eax
+; X64-O0-ZU-NEXT: # kill: def $rax killed $eax
+; X64-O0-ZU-NEXT: movq %rax, var_57
+; X64-O0-ZU-NEXT: movl var_5, %eax
+; X64-O0-ZU-NEXT: xorl $-1, %eax
+; X64-O0-ZU-NEXT: cmpl $0, %eax
+; X64-O0-ZU-NEXT: setzune %al
+; X64-O0-ZU-NEXT: xorb $-1, %al
+; X64-O0-ZU-NEXT: andb $1, %al
+; X64-O0-ZU-NEXT: movzbl %al, %eax
+; X64-O0-ZU-NEXT: # kill: def $rax killed $eax
+; X64-O0-ZU-NEXT: movq %rax, _ZN8struct_210member_2_0E
+; X64-O0-ZU-NEXT: retq
+;
+; X64-ZU-LABEL: f1:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movslq var_5(%rip), %rax
+; X64-ZU-NEXT: movabsq $-8381627093, %rcx # imm = 0xFFFFFFFE0C6A852B
+; X64-ZU-NEXT: cmpq %rcx, %rax
+; X64-ZU-NEXT: setne -{{[0-9]+}}(%rsp)
+; X64-ZU-NEXT: cmpq $-1, %rax
+; X64-ZU-NEXT: setzue %cl
+; X64-ZU-NEXT: cmpl $-1, %eax
+; X64-ZU-NEXT: setzue %dl
+; X64-ZU-NEXT: addq $7093, %rax # imm = 0x1BB5
+; X64-ZU-NEXT: cmpq %rax, %rdx
+; X64-ZU-NEXT: setzug %al
+; X64-ZU-NEXT: movq %rax, var_57(%rip)
+; X64-ZU-NEXT: movq %rcx, _ZN8struct_210member_2_0E(%rip)
+; X64-ZU-NEXT: retq
+;
; X86-O0-LABEL: f1:
; X86-O0: # %bb.0: # %entry
; X86-O0-NEXT: subl $1, %esp
@@ -328,6 +422,45 @@ define void @f2() {
; X64-NEXT: movw %dx, (%rax)
; X64-NEXT: retq
;
+; X64-O0-ZU-LABEL: f2:
+; X64-O0-ZU: # %bb.0: # %entry
+; X64-O0-ZU-NEXT: movzbl var_7, %eax
+; X64-O0-ZU-NEXT: cmpb $0, var_7
+; X64-O0-ZU-NEXT: setzune %cl
+; X64-O0-ZU-NEXT: xorb $-1, %cl
+; X64-O0-ZU-NEXT: andb $1, %cl
+; X64-O0-ZU-NEXT: movzbl %cl, %ecx
+; X64-O0-ZU-NEXT: xorl %ecx, %eax
+; X64-O0-ZU-NEXT: # kill: def $ax killed $ax killed $eax
+; X64-O0-ZU-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
+; X64-O0-ZU-NEXT: movzbl var_7, %eax
+; X64-O0-ZU-NEXT: # kill: def $ax killed $ax killed $eax
+; X64-O0-ZU-NEXT: cmpw $0, %ax
+; X64-O0-ZU-NEXT: setzune %al
+; X64-O0-ZU-NEXT: xorb $-1, %al
+; X64-O0-ZU-NEXT: andb $1, %al
+; X64-O0-ZU-NEXT: movzbl %al, %eax
+; X64-O0-ZU-NEXT: movzbl var_7, %ecx
+; X64-O0-ZU-NEXT: cmpl %ecx, %eax
+; X64-O0-ZU-NEXT: setzue %al
+; X64-O0-ZU-NEXT: andb $1, %al
+; X64-O0-ZU-NEXT: movzbl %al, %eax
+; X64-O0-ZU-NEXT: movw %ax, %cx
+; X64-O0-ZU-NEXT: # implicit-def: $rax
+; X64-O0-ZU-NEXT: movw %cx, (%rax)
+; X64-O0-ZU-NEXT: retq
+;
+; X64-ZU-LABEL: f2:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movzbl var_7(%rip), %eax
+; X64-ZU-NEXT: testl %eax, %eax
+; X64-ZU-NEXT: setzue %cl
+; X64-ZU-NEXT: xorl %eax, %ecx
+; X64-ZU-NEXT: movw %cx, -{{[0-9]+}}(%rsp)
+; X64-ZU-NEXT: setzue %al
+; X64-ZU-NEXT: movw %ax, (%rax)
+; X64-ZU-NEXT: retq
+;
; X86-O0-LABEL: f2:
; X86-O0: # %bb.0: # %entry
; X86-O0-NEXT: subl $2, %esp
@@ -458,6 +591,56 @@ define void @f3() #0 {
; X64-NEXT: movl %eax, var_46(%rip)
; X64-NEXT: retq
;
+; X64-O0-ZU-LABEL: f3:
+; X64-O0-ZU: # %bb.0: # %entry
+; X64-O0-ZU-NEXT: movl var_13, %eax
+; X64-O0-ZU-NEXT: xorl $-1, %eax
+; X64-O0-ZU-NEXT: movl %eax, %eax
+; X64-O0-ZU-NEXT: # kill: def $rax killed $eax
+; X64-O0-ZU-NEXT: cmpl $0, var_13
+; X64-O0-ZU-NEXT: setzune %cl
+; X64-O0-ZU-NEXT: xorb $-1, %cl
+; X64-O0-ZU-NEXT: andb $1, %cl
+; X64-O0-ZU-NEXT: movzbl %cl, %ecx
+; X64-O0-ZU-NEXT: # kill: def $rcx killed $ecx
+; X64-O0-ZU-NEXT: movl var_13, %edx
+; X64-O0-ZU-NEXT: xorl $-1, %edx
+; X64-O0-ZU-NEXT: xorl var_16, %edx
+; X64-O0-ZU-NEXT: movl %edx, %edx
+; X64-O0-ZU-NEXT: # kill: def $rdx killed $edx
+; X64-O0-ZU-NEXT: andq %rdx, %rcx
+; X64-O0-ZU-NEXT: orq %rcx, %rax
+; X64-O0-ZU-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
+; X64-O0-ZU-NEXT: movl var_13, %eax
+; X64-O0-ZU-NEXT: xorl $-1, %eax
+; X64-O0-ZU-NEXT: movl %eax, %eax
+; X64-O0-ZU-NEXT: # kill: def $rax killed $eax
+; X64-O0-ZU-NEXT: cmpl $0, var_13
+; X64-O0-ZU-NEXT: setzune %cl
+; X64-O0-ZU-NEXT: xorb $-1, %cl
+; X64-O0-ZU-NEXT: andb $1, %cl
+; X64-O0-ZU-NEXT: movzbl %cl, %ecx
+; X64-O0-ZU-NEXT: # kill: def $rcx killed $ecx
+; X64-O0-ZU-NEXT: andq $0, %rcx
+; X64-O0-ZU-NEXT: orq %rcx, %rax
+; X64-O0-ZU-NEXT: # kill: def $eax killed $eax killed $rax
+; X64-O0-ZU-NEXT: movl %eax, var_46
+; X64-O0-ZU-NEXT: retq
+;
+; X64-ZU-LABEL: f3:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movl var_13(%rip), %eax
+; X64-ZU-NEXT: testl %eax, %eax
+; X64-ZU-NEXT: notl %eax
+; X64-ZU-NEXT: setzue %cl
+; X64-ZU-NEXT: movl var_16(%rip), %edx
+; X64-ZU-NEXT: xorl %eax, %edx
+; X64-ZU-NEXT: andl %edx, %ecx
+; X64-ZU-NEXT: orl %eax, %ecx
+; X64-ZU-NEXT: movq %rcx, -{{[0-9]+}}(%rsp)
+; X64-ZU-NEXT: movl %eax, var_46(%rip)
+; X64-ZU-NEXT: retq
+;
; X86-O0-LABEL: f3:
; X86-O0: # %bb.0: # %entry
; X86-O0-NEXT: pushl %ebp
diff --git a/llvm/test/CodeGen/X86/pr54369.ll b/llvm/test/CodeGen/X86/pr54369.ll
index bebe8a0b2dc01..c6cfa49b14eb9 100644
--- a/llvm/test/CodeGen/X86/pr54369.ll
+++ b/llvm/test/CodeGen/X86/pr54369.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64-- -O0 < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64-- -O0 -mattr=+zu < %s | FileCheck %s -check-prefix=ZU
define i64 @adder(i64 %lhs, i64 %rhs) {
; CHECK-LABEL: adder:
@@ -12,6 +13,17 @@ define i64 @adder(i64 %lhs, i64 %rhs) {
; CHECK-NEXT: testb $1, %dl
; CHECK-NEXT: cmovneq %rcx, %rax
; CHECK-NEXT: retq
+;
+; ZU-LABEL: adder:
+; ZU: # %bb.0:
+; ZU-NEXT: addq %rsi, %rdi
+; ZU-NEXT: setzuo %dl
+; ZU-NEXT: xorl %eax, %eax
+; ZU-NEXT: # kill: def $rax killed $eax
+; ZU-NEXT: movl $148, %ecx
+; ZU-NEXT: testb $1, %dl
+; ZU-NEXT: cmovneq %rcx, %rax
+; ZU-NEXT: retq
%res = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %lhs, i64 %rhs)
%errorbit = extractvalue { i64, i1 } %res, 1
%errorval = select i1 %errorbit, i64 148, i64 0
@@ -31,6 +43,17 @@ define i64 @adder_constexpr(i64 %lhs, i64 %rhs) {
; CHECK-NEXT: testb $1, %dl
; CHECK-NEXT: cmovneq %rcx, %rax
; CHECK-NEXT: retq
+;
+; ZU-LABEL: adder_constexpr:
+; ZU: # %bb.0:
+; ZU-NEXT: addq %rsi, %rdi
+; ZU-NEXT: setzuo %dl
+; ZU-NEXT: movq a at GOTPCREL(%rip), %rax
+; ZU-NEXT: addq $5, %rax
+; ZU-NEXT: movl $148, %ecx
+; ZU-NEXT: testb $1, %dl
+; ZU-NEXT: cmovneq %rcx, %rax
+; ZU-NEXT: retq
%res = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %lhs, i64 %rhs)
%errorbit = extractvalue { i64, i1 } %res, 1
%errorval = select i1 %errorbit, i64 148, i64 add (i64 ptrtoint (ptr @a to i64), i64 5)
>From 85e4617fa7a726a88d08034e60e3b07563c08c32 Mon Sep 17 00:00:00 2001
From: Feng Zou <feng.zou at intel.com>
Date: Tue, 3 Jun 2025 09:20:25 +0800
Subject: [PATCH 3/6] Refine tests.
---
.../CodeGen/X86/apx/flags-copy-lowering.mir | 1455 +++++++-------
llvm/test/CodeGen/X86/cmp.ll | 380 +---
llvm/test/CodeGen/X86/is_fpclass.ll | 1732 +++++++++--------
3 files changed, 1651 insertions(+), 1916 deletions(-)
diff --git a/llvm/test/CodeGen/X86/apx/flags-copy-lowering.mir b/llvm/test/CodeGen/X86/apx/flags-copy-lowering.mir
index a7db26ae51942..39d9f26fd5ae8 100644
--- a/llvm/test/CodeGen/X86/apx/flags-copy-lowering.mir
+++ b/llvm/test/CodeGen/X86/apx/flags-copy-lowering.mir
@@ -1,9 +1,9 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=x86_64 -run-pass x86-flags-copy-lowering -mattr=+ndd -verify-machineinstrs -o - %s | FileCheck --check-prefixes=NDD %s
-# RUN: llc -mtriple=x86_64 -run-pass x86-flags-copy-lowering -mattr=+ndd,+nf -verify-machineinstrs -o - %s | FileCheck --check-prefixes=NDD-NF %s
-# RUN: llc -mtriple=x86_64 -run-pass x86-flags-copy-lowering -mattr=+ndd,+nf,+zu -verify-machineinstrs -o - %s | FileCheck --check-prefixes=NDD-NF-ZU %s
-# RUN: llc -O0 -mtriple=x86_64 -run-pass x86-flags-copy-lowering -mattr=+ndd,+nf,+zu -verify-machineinstrs -o - %s | FileCheck --check-prefixes=O0-NDD-NF-ZU %s
-# RUN: llc -mtriple=x86_64 -run-pass x86-flags-copy-lowering -mattr=+ndd,+nf -x86-enable-apx-for-relocation=true -verify-machineinstrs -o - %s | FileCheck --check-prefixes=NDD-NF %s
+# RUN: llc -mtriple=x86_64 -run-pass x86-flags-copy-lowering -mattr=+ndd -verify-machineinstrs -o - %s | FileCheck --check-prefixes=CHECK,NDD %s
+# RUN: llc -mtriple=x86_64 -run-pass x86-flags-copy-lowering -mattr=+ndd,+zu -verify-machineinstrs -o - %s | FileCheck --check-prefix=NDD-ZU %s
+# RUN: llc -O0 -mtriple=x86_64 -run-pass x86-flags-copy-lowering -mattr=+ndd,+zu -verify-machineinstrs -o - %s | FileCheck --check-prefix=O0-NDD-ZU %s
+# RUN: llc -mtriple=x86_64 -run-pass x86-flags-copy-lowering -mattr=+ndd,+nf -verify-machineinstrs -o - %s | FileCheck --check-prefixes=CHECK,NDD-NF %s
+# RUN: llc -mtriple=x86_64 -run-pass x86-flags-copy-lowering -mattr=+ndd,+nf -x86-enable-apx-for-relocation=true -verify-machineinstrs -o - %s | FileCheck --check-prefixes=CHECK,NDD-NF %s
# Lower various interesting copy patterns of EFLAGS without using LAHF/SAHF.
@@ -14,61 +14,47 @@ body: |
bb.0:
liveins: $rdi, $rsi
- ; NDD-LABEL: name: test_adc
- ; NDD: liveins: $rdi, $rsi
- ; NDD-NEXT: {{ $}}
- ; NDD-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; NDD-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; NDD-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
- ; NDD-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
- ; NDD-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; NDD-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETCCr]], 255, implicit-def $eflags
- ; NDD-NEXT: [[ADC64ri32_ND:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADD64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
- ; NDD-NEXT: [[ADC64ri32_ND1:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADC64ri32_ND]], 42, implicit-def $eflags, implicit $eflags
- ; NDD-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[ADC64ri32_ND1]]
- ; NDD-NEXT: RET 0
- ;
- ; NDD-NF-LABEL: name: test_adc
- ; NDD-NF: liveins: $rdi, $rsi
- ; NDD-NF-NEXT: {{ $}}
- ; NDD-NF-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; NDD-NF-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; NDD-NF-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
- ; NDD-NF-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
- ; NDD-NF-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; NDD-NF-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETCCr]], 255, implicit-def $eflags
- ; NDD-NF-NEXT: [[ADC64ri32_ND:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADD64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
- ; NDD-NF-NEXT: [[ADC64ri32_ND1:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADC64ri32_ND]], 42, implicit-def $eflags, implicit $eflags
- ; NDD-NF-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[ADC64ri32_ND1]]
- ; NDD-NF-NEXT: RET 0
+ ; CHECK-LABEL: name: test_adc
+ ; CHECK: liveins: $rdi, $rsi
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; CHECK-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
+ ; CHECK-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; CHECK-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETCCr]], 255, implicit-def $eflags
+ ; CHECK-NEXT: [[ADC64ri32_ND:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADD64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
+ ; CHECK-NEXT: [[ADC64ri32_ND1:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADC64ri32_ND]], 42, implicit-def $eflags, implicit $eflags
+ ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[ADC64ri32_ND1]]
+ ; CHECK-NEXT: RET 0
;
- ; NDD-NF-ZU-LABEL: name: test_adc
- ; NDD-NF-ZU: liveins: $rdi, $rsi
- ; NDD-NF-ZU-NEXT: {{ $}}
- ; NDD-NF-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; NDD-NF-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; NDD-NF-ZU-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
- ; NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
- ; NDD-NF-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; NDD-NF-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr]], 255, implicit-def $eflags
- ; NDD-NF-ZU-NEXT: [[ADC64ri32_ND:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADD64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
- ; NDD-NF-ZU-NEXT: [[ADC64ri32_ND1:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADC64ri32_ND]], 42, implicit-def $eflags, implicit $eflags
- ; NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[ADC64ri32_ND1]]
- ; NDD-NF-ZU-NEXT: RET 0
+ ; NDD-ZU-LABEL: name: test_adc
+ ; NDD-ZU: liveins: $rdi, $rsi
+ ; NDD-ZU-NEXT: {{ $}}
+ ; NDD-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; NDD-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; NDD-ZU-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; NDD-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; NDD-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr]], 255, implicit-def $eflags
+ ; NDD-ZU-NEXT: [[ADC64ri32_ND:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADD64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
+ ; NDD-ZU-NEXT: [[ADC64ri32_ND1:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADC64ri32_ND]], 42, implicit-def $eflags, implicit $eflags
+ ; NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[ADC64ri32_ND1]]
+ ; NDD-ZU-NEXT: RET 0
;
- ; O0-NDD-NF-ZU-LABEL: name: test_adc
- ; O0-NDD-NF-ZU: liveins: $rdi, $rsi
- ; O0-NDD-NF-ZU-NEXT: {{ $}}
- ; O0-NDD-NF-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; O0-NDD-NF-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; O0-NDD-NF-ZU-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
- ; O0-NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; O0-NDD-NF-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr]], 255, implicit-def $eflags
- ; O0-NDD-NF-ZU-NEXT: [[ADC64ri32_ND:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADD64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
- ; O0-NDD-NF-ZU-NEXT: [[ADC64ri32_ND1:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADC64ri32_ND]], 42, implicit-def $eflags, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[ADC64ri32_ND1]]
- ; O0-NDD-NF-ZU-NEXT: RET 0
+ ; O0-NDD-ZU-LABEL: name: test_adc
+ ; O0-NDD-ZU: liveins: $rdi, $rsi
+ ; O0-NDD-ZU-NEXT: {{ $}}
+ ; O0-NDD-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; O0-NDD-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; O0-NDD-ZU-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; O0-NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; O0-NDD-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; O0-NDD-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr]], 255, implicit-def $eflags
+ ; O0-NDD-ZU-NEXT: [[ADC64ri32_ND:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADD64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
+ ; O0-NDD-ZU-NEXT: [[ADC64ri32_ND1:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADC64ri32_ND]], 42, implicit-def $eflags, implicit $eflags
+ ; O0-NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[ADC64ri32_ND1]]
+ ; O0-NDD-ZU-NEXT: RET 0
%0:gr64 = COPY $rdi
%1:gr64 = COPY $rsi
%2:gr64 = ADD64rr_ND %0, %1, implicit-def $eflags
@@ -90,61 +76,47 @@ body: |
bb.0:
liveins: $rdi, $rsi
- ; NDD-LABEL: name: test_sbb
- ; NDD: liveins: $rdi, $rsi
- ; NDD-NEXT: {{ $}}
- ; NDD-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; NDD-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; NDD-NEXT: [[SUB64rr_ND:%[0-9]+]]:gr64 = SUB64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
- ; NDD-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
- ; NDD-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; NDD-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETCCr]], 255, implicit-def $eflags
- ; NDD-NEXT: [[SBB64ri32_ND:%[0-9]+]]:gr64 = SBB64ri32_ND [[SUB64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
- ; NDD-NEXT: [[SBB64ri32_ND1:%[0-9]+]]:gr64 = SBB64ri32_ND [[SBB64ri32_ND]], 42, implicit-def dead $eflags, implicit killed $eflags
- ; NDD-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[SBB64ri32_ND1]]
- ; NDD-NEXT: RET 0
+ ; CHECK-LABEL: name: test_sbb
+ ; CHECK: liveins: $rdi, $rsi
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; CHECK-NEXT: [[SUB64rr_ND:%[0-9]+]]:gr64 = SUB64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
+ ; CHECK-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; CHECK-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETCCr]], 255, implicit-def $eflags
+ ; CHECK-NEXT: [[SBB64ri32_ND:%[0-9]+]]:gr64 = SBB64ri32_ND [[SUB64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
+ ; CHECK-NEXT: [[SBB64ri32_ND1:%[0-9]+]]:gr64 = SBB64ri32_ND [[SBB64ri32_ND]], 42, implicit-def dead $eflags, implicit killed $eflags
+ ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[SBB64ri32_ND1]]
+ ; CHECK-NEXT: RET 0
;
- ; NDD-NF-LABEL: name: test_sbb
- ; NDD-NF: liveins: $rdi, $rsi
- ; NDD-NF-NEXT: {{ $}}
- ; NDD-NF-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; NDD-NF-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; NDD-NF-NEXT: [[SUB64rr_ND:%[0-9]+]]:gr64 = SUB64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
- ; NDD-NF-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
- ; NDD-NF-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; NDD-NF-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETCCr]], 255, implicit-def $eflags
- ; NDD-NF-NEXT: [[SBB64ri32_ND:%[0-9]+]]:gr64 = SBB64ri32_ND [[SUB64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
- ; NDD-NF-NEXT: [[SBB64ri32_ND1:%[0-9]+]]:gr64 = SBB64ri32_ND [[SBB64ri32_ND]], 42, implicit-def dead $eflags, implicit killed $eflags
- ; NDD-NF-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[SBB64ri32_ND1]]
- ; NDD-NF-NEXT: RET 0
+ ; NDD-ZU-LABEL: name: test_sbb
+ ; NDD-ZU: liveins: $rdi, $rsi
+ ; NDD-ZU-NEXT: {{ $}}
+ ; NDD-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; NDD-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; NDD-ZU-NEXT: [[SUB64rr_ND:%[0-9]+]]:gr64 = SUB64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; NDD-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; NDD-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr]], 255, implicit-def $eflags
+ ; NDD-ZU-NEXT: [[SBB64ri32_ND:%[0-9]+]]:gr64 = SBB64ri32_ND [[SUB64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
+ ; NDD-ZU-NEXT: [[SBB64ri32_ND1:%[0-9]+]]:gr64 = SBB64ri32_ND [[SBB64ri32_ND]], 42, implicit-def dead $eflags, implicit killed $eflags
+ ; NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[SBB64ri32_ND1]]
+ ; NDD-ZU-NEXT: RET 0
;
- ; NDD-NF-ZU-LABEL: name: test_sbb
- ; NDD-NF-ZU: liveins: $rdi, $rsi
- ; NDD-NF-ZU-NEXT: {{ $}}
- ; NDD-NF-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; NDD-NF-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; NDD-NF-ZU-NEXT: [[SUB64rr_ND:%[0-9]+]]:gr64 = SUB64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
- ; NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
- ; NDD-NF-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; NDD-NF-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr]], 255, implicit-def $eflags
- ; NDD-NF-ZU-NEXT: [[SBB64ri32_ND:%[0-9]+]]:gr64 = SBB64ri32_ND [[SUB64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
- ; NDD-NF-ZU-NEXT: [[SBB64ri32_ND1:%[0-9]+]]:gr64 = SBB64ri32_ND [[SBB64ri32_ND]], 42, implicit-def dead $eflags, implicit killed $eflags
- ; NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[SBB64ri32_ND1]]
- ; NDD-NF-ZU-NEXT: RET 0
- ;
- ; O0-NDD-NF-ZU-LABEL: name: test_sbb
- ; O0-NDD-NF-ZU: liveins: $rdi, $rsi
- ; O0-NDD-NF-ZU-NEXT: {{ $}}
- ; O0-NDD-NF-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; O0-NDD-NF-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; O0-NDD-NF-ZU-NEXT: [[SUB64rr_ND:%[0-9]+]]:gr64 = SUB64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
- ; O0-NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; O0-NDD-NF-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr]], 255, implicit-def $eflags
- ; O0-NDD-NF-ZU-NEXT: [[SBB64ri32_ND:%[0-9]+]]:gr64 = SBB64ri32_ND [[SUB64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
- ; O0-NDD-NF-ZU-NEXT: [[SBB64ri32_ND1:%[0-9]+]]:gr64 = SBB64ri32_ND [[SBB64ri32_ND]], 42, implicit-def dead $eflags, implicit killed $eflags
- ; O0-NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[SBB64ri32_ND1]]
- ; O0-NDD-NF-ZU-NEXT: RET 0
+ ; O0-NDD-ZU-LABEL: name: test_sbb
+ ; O0-NDD-ZU: liveins: $rdi, $rsi
+ ; O0-NDD-ZU-NEXT: {{ $}}
+ ; O0-NDD-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; O0-NDD-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; O0-NDD-ZU-NEXT: [[SUB64rr_ND:%[0-9]+]]:gr64 = SUB64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; O0-NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; O0-NDD-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; O0-NDD-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr]], 255, implicit-def $eflags
+ ; O0-NDD-ZU-NEXT: [[SBB64ri32_ND:%[0-9]+]]:gr64 = SBB64ri32_ND [[SUB64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
+ ; O0-NDD-ZU-NEXT: [[SBB64ri32_ND1:%[0-9]+]]:gr64 = SBB64ri32_ND [[SBB64ri32_ND]], 42, implicit-def dead $eflags, implicit killed $eflags
+ ; O0-NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[SBB64ri32_ND1]]
+ ; O0-NDD-ZU-NEXT: RET 0
%0:gr64 = COPY $rdi
%1:gr64 = COPY $rsi
%2:gr64 = SUB64rr_ND %0, %1, implicit-def $eflags
@@ -166,61 +138,47 @@ body: |
bb.0:
liveins: $rdi, $rsi
- ; NDD-LABEL: name: test_rcl
- ; NDD: liveins: $rdi, $rsi
- ; NDD-NEXT: {{ $}}
- ; NDD-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; NDD-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; NDD-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
- ; NDD-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
- ; NDD-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; NDD-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETCCr]], 255, implicit-def $eflags
- ; NDD-NEXT: [[RCL64r1_ND:%[0-9]+]]:gr64 = RCL64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
- ; NDD-NEXT: [[RCL64r1_ND1:%[0-9]+]]:gr64 = RCL64r1_ND [[RCL64r1_ND]], implicit-def $eflags, implicit $eflags
- ; NDD-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCL64r1_ND1]]
- ; NDD-NEXT: RET 0
- ;
- ; NDD-NF-LABEL: name: test_rcl
- ; NDD-NF: liveins: $rdi, $rsi
- ; NDD-NF-NEXT: {{ $}}
- ; NDD-NF-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; NDD-NF-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; NDD-NF-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
- ; NDD-NF-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
- ; NDD-NF-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; NDD-NF-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETCCr]], 255, implicit-def $eflags
- ; NDD-NF-NEXT: [[RCL64r1_ND:%[0-9]+]]:gr64 = RCL64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
- ; NDD-NF-NEXT: [[RCL64r1_ND1:%[0-9]+]]:gr64 = RCL64r1_ND [[RCL64r1_ND]], implicit-def $eflags, implicit $eflags
- ; NDD-NF-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCL64r1_ND1]]
- ; NDD-NF-NEXT: RET 0
+ ; CHECK-LABEL: name: test_rcl
+ ; CHECK: liveins: $rdi, $rsi
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; CHECK-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
+ ; CHECK-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; CHECK-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETCCr]], 255, implicit-def $eflags
+ ; CHECK-NEXT: [[RCL64r1_ND:%[0-9]+]]:gr64 = RCL64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
+ ; CHECK-NEXT: [[RCL64r1_ND1:%[0-9]+]]:gr64 = RCL64r1_ND [[RCL64r1_ND]], implicit-def $eflags, implicit $eflags
+ ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCL64r1_ND1]]
+ ; CHECK-NEXT: RET 0
;
- ; NDD-NF-ZU-LABEL: name: test_rcl
- ; NDD-NF-ZU: liveins: $rdi, $rsi
- ; NDD-NF-ZU-NEXT: {{ $}}
- ; NDD-NF-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; NDD-NF-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; NDD-NF-ZU-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
- ; NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
- ; NDD-NF-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; NDD-NF-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr]], 255, implicit-def $eflags
- ; NDD-NF-ZU-NEXT: [[RCL64r1_ND:%[0-9]+]]:gr64 = RCL64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
- ; NDD-NF-ZU-NEXT: [[RCL64r1_ND1:%[0-9]+]]:gr64 = RCL64r1_ND [[RCL64r1_ND]], implicit-def $eflags, implicit $eflags
- ; NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCL64r1_ND1]]
- ; NDD-NF-ZU-NEXT: RET 0
+ ; NDD-ZU-LABEL: name: test_rcl
+ ; NDD-ZU: liveins: $rdi, $rsi
+ ; NDD-ZU-NEXT: {{ $}}
+ ; NDD-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; NDD-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; NDD-ZU-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; NDD-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; NDD-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr]], 255, implicit-def $eflags
+ ; NDD-ZU-NEXT: [[RCL64r1_ND:%[0-9]+]]:gr64 = RCL64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
+ ; NDD-ZU-NEXT: [[RCL64r1_ND1:%[0-9]+]]:gr64 = RCL64r1_ND [[RCL64r1_ND]], implicit-def $eflags, implicit $eflags
+ ; NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCL64r1_ND1]]
+ ; NDD-ZU-NEXT: RET 0
;
- ; O0-NDD-NF-ZU-LABEL: name: test_rcl
- ; O0-NDD-NF-ZU: liveins: $rdi, $rsi
- ; O0-NDD-NF-ZU-NEXT: {{ $}}
- ; O0-NDD-NF-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; O0-NDD-NF-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; O0-NDD-NF-ZU-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
- ; O0-NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; O0-NDD-NF-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr]], 255, implicit-def $eflags
- ; O0-NDD-NF-ZU-NEXT: [[RCL64r1_ND:%[0-9]+]]:gr64 = RCL64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
- ; O0-NDD-NF-ZU-NEXT: [[RCL64r1_ND1:%[0-9]+]]:gr64 = RCL64r1_ND [[RCL64r1_ND]], implicit-def $eflags, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCL64r1_ND1]]
- ; O0-NDD-NF-ZU-NEXT: RET 0
+ ; O0-NDD-ZU-LABEL: name: test_rcl
+ ; O0-NDD-ZU: liveins: $rdi, $rsi
+ ; O0-NDD-ZU-NEXT: {{ $}}
+ ; O0-NDD-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; O0-NDD-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; O0-NDD-ZU-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; O0-NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; O0-NDD-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; O0-NDD-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr]], 255, implicit-def $eflags
+ ; O0-NDD-ZU-NEXT: [[RCL64r1_ND:%[0-9]+]]:gr64 = RCL64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
+ ; O0-NDD-ZU-NEXT: [[RCL64r1_ND1:%[0-9]+]]:gr64 = RCL64r1_ND [[RCL64r1_ND]], implicit-def $eflags, implicit $eflags
+ ; O0-NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCL64r1_ND1]]
+ ; O0-NDD-ZU-NEXT: RET 0
%0:gr64 = COPY $rdi
%1:gr64 = COPY $rsi
%2:gr64 = ADD64rr_ND %0, %1, implicit-def $eflags
@@ -242,61 +200,47 @@ body: |
bb.0:
liveins: $rdi, $rsi
- ; NDD-LABEL: name: test_rcr
- ; NDD: liveins: $rdi, $rsi
- ; NDD-NEXT: {{ $}}
- ; NDD-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; NDD-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; NDD-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
- ; NDD-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
- ; NDD-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; NDD-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETCCr]], 255, implicit-def $eflags
- ; NDD-NEXT: [[RCR64r1_ND:%[0-9]+]]:gr64 = RCR64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
- ; NDD-NEXT: [[RCR64r1_ND1:%[0-9]+]]:gr64 = RCR64r1_ND [[RCR64r1_ND]], implicit-def $eflags, implicit $eflags
- ; NDD-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCR64r1_ND1]]
- ; NDD-NEXT: RET 0
- ;
- ; NDD-NF-LABEL: name: test_rcr
- ; NDD-NF: liveins: $rdi, $rsi
- ; NDD-NF-NEXT: {{ $}}
- ; NDD-NF-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; NDD-NF-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; NDD-NF-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
- ; NDD-NF-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
- ; NDD-NF-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; NDD-NF-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETCCr]], 255, implicit-def $eflags
- ; NDD-NF-NEXT: [[RCR64r1_ND:%[0-9]+]]:gr64 = RCR64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
- ; NDD-NF-NEXT: [[RCR64r1_ND1:%[0-9]+]]:gr64 = RCR64r1_ND [[RCR64r1_ND]], implicit-def $eflags, implicit $eflags
- ; NDD-NF-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCR64r1_ND1]]
- ; NDD-NF-NEXT: RET 0
+ ; CHECK-LABEL: name: test_rcr
+ ; CHECK: liveins: $rdi, $rsi
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; CHECK-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
+ ; CHECK-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; CHECK-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETCCr]], 255, implicit-def $eflags
+ ; CHECK-NEXT: [[RCR64r1_ND:%[0-9]+]]:gr64 = RCR64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
+ ; CHECK-NEXT: [[RCR64r1_ND1:%[0-9]+]]:gr64 = RCR64r1_ND [[RCR64r1_ND]], implicit-def $eflags, implicit $eflags
+ ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCR64r1_ND1]]
+ ; CHECK-NEXT: RET 0
;
- ; NDD-NF-ZU-LABEL: name: test_rcr
- ; NDD-NF-ZU: liveins: $rdi, $rsi
- ; NDD-NF-ZU-NEXT: {{ $}}
- ; NDD-NF-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; NDD-NF-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; NDD-NF-ZU-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
- ; NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
- ; NDD-NF-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; NDD-NF-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr]], 255, implicit-def $eflags
- ; NDD-NF-ZU-NEXT: [[RCR64r1_ND:%[0-9]+]]:gr64 = RCR64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
- ; NDD-NF-ZU-NEXT: [[RCR64r1_ND1:%[0-9]+]]:gr64 = RCR64r1_ND [[RCR64r1_ND]], implicit-def $eflags, implicit $eflags
- ; NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCR64r1_ND1]]
- ; NDD-NF-ZU-NEXT: RET 0
+ ; NDD-ZU-LABEL: name: test_rcr
+ ; NDD-ZU: liveins: $rdi, $rsi
+ ; NDD-ZU-NEXT: {{ $}}
+ ; NDD-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; NDD-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; NDD-ZU-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; NDD-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; NDD-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr]], 255, implicit-def $eflags
+ ; NDD-ZU-NEXT: [[RCR64r1_ND:%[0-9]+]]:gr64 = RCR64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
+ ; NDD-ZU-NEXT: [[RCR64r1_ND1:%[0-9]+]]:gr64 = RCR64r1_ND [[RCR64r1_ND]], implicit-def $eflags, implicit $eflags
+ ; NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCR64r1_ND1]]
+ ; NDD-ZU-NEXT: RET 0
;
- ; O0-NDD-NF-ZU-LABEL: name: test_rcr
- ; O0-NDD-NF-ZU: liveins: $rdi, $rsi
- ; O0-NDD-NF-ZU-NEXT: {{ $}}
- ; O0-NDD-NF-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; O0-NDD-NF-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; O0-NDD-NF-ZU-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
- ; O0-NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; O0-NDD-NF-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr]], 255, implicit-def $eflags
- ; O0-NDD-NF-ZU-NEXT: [[RCR64r1_ND:%[0-9]+]]:gr64 = RCR64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
- ; O0-NDD-NF-ZU-NEXT: [[RCR64r1_ND1:%[0-9]+]]:gr64 = RCR64r1_ND [[RCR64r1_ND]], implicit-def $eflags, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCR64r1_ND1]]
- ; O0-NDD-NF-ZU-NEXT: RET 0
+ ; O0-NDD-ZU-LABEL: name: test_rcr
+ ; O0-NDD-ZU: liveins: $rdi, $rsi
+ ; O0-NDD-ZU-NEXT: {{ $}}
+ ; O0-NDD-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; O0-NDD-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; O0-NDD-ZU-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; O0-NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; O0-NDD-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; O0-NDD-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr]], 255, implicit-def $eflags
+ ; O0-NDD-ZU-NEXT: [[RCR64r1_ND:%[0-9]+]]:gr64 = RCR64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
+ ; O0-NDD-ZU-NEXT: [[RCR64r1_ND1:%[0-9]+]]:gr64 = RCR64r1_ND [[RCR64r1_ND]], implicit-def $eflags, implicit $eflags
+ ; O0-NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCR64r1_ND1]]
+ ; O0-NDD-ZU-NEXT: RET 0
%0:gr64 = COPY $rdi
%1:gr64 = COPY $rsi
%2:gr64 = ADD64rr_ND %0, %1, implicit-def $eflags
@@ -318,101 +262,77 @@ body: |
bb.0:
liveins: $rdi, $rsi
- ; NDD-LABEL: name: test_cmov
- ; NDD: liveins: $rdi, $rsi
- ; NDD-NEXT: {{ $}}
- ; NDD-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; NDD-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; NDD-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
- ; NDD-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
- ; NDD-NEXT: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
- ; NDD-NEXT: [[SETCCr2:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
- ; NDD-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; NDD-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
- ; NDD-NEXT: [[CMOV64rr_ND:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
- ; NDD-NEXT: TEST8rr [[SETCCr1]], [[SETCCr1]], implicit-def $eflags
- ; NDD-NEXT: [[CMOV64rr_ND1:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
- ; NDD-NEXT: TEST8rr [[SETCCr2]], [[SETCCr2]], implicit-def $eflags
- ; NDD-NEXT: [[CMOV64rr_ND2:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
- ; NDD-NEXT: TEST8rr [[SETCCr2]], [[SETCCr2]], implicit-def $eflags
- ; NDD-NEXT: [[CMOV64rr_ND3:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
- ; NDD-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND]]
- ; NDD-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND1]]
- ; NDD-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND2]]
- ; NDD-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND3]]
- ; NDD-NEXT: RET 0
- ;
- ; NDD-NF-LABEL: name: test_cmov
- ; NDD-NF: liveins: $rdi, $rsi
- ; NDD-NF-NEXT: {{ $}}
- ; NDD-NF-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; NDD-NF-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; NDD-NF-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
- ; NDD-NF-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
- ; NDD-NF-NEXT: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
- ; NDD-NF-NEXT: [[SETCCr2:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
- ; NDD-NF-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; NDD-NF-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
- ; NDD-NF-NEXT: [[CMOV64rr_ND:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
- ; NDD-NF-NEXT: TEST8rr [[SETCCr1]], [[SETCCr1]], implicit-def $eflags
- ; NDD-NF-NEXT: [[CMOV64rr_ND1:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
- ; NDD-NF-NEXT: TEST8rr [[SETCCr2]], [[SETCCr2]], implicit-def $eflags
- ; NDD-NF-NEXT: [[CMOV64rr_ND2:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
- ; NDD-NF-NEXT: TEST8rr [[SETCCr2]], [[SETCCr2]], implicit-def $eflags
- ; NDD-NF-NEXT: [[CMOV64rr_ND3:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
- ; NDD-NF-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND]]
- ; NDD-NF-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND1]]
- ; NDD-NF-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND2]]
- ; NDD-NF-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND3]]
- ; NDD-NF-NEXT: RET 0
+ ; CHECK-LABEL: name: test_cmov
+ ; CHECK: liveins: $rdi, $rsi
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; CHECK-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
+ ; CHECK-NEXT: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
+ ; CHECK-NEXT: [[SETCCr2:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
+ ; CHECK-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; CHECK-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
+ ; CHECK-NEXT: [[CMOV64rr_ND:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; CHECK-NEXT: TEST8rr [[SETCCr1]], [[SETCCr1]], implicit-def $eflags
+ ; CHECK-NEXT: [[CMOV64rr_ND1:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; CHECK-NEXT: TEST8rr [[SETCCr2]], [[SETCCr2]], implicit-def $eflags
+ ; CHECK-NEXT: [[CMOV64rr_ND2:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; CHECK-NEXT: TEST8rr [[SETCCr2]], [[SETCCr2]], implicit-def $eflags
+ ; CHECK-NEXT: [[CMOV64rr_ND3:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
+ ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND]]
+ ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND1]]
+ ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND2]]
+ ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND3]]
+ ; CHECK-NEXT: RET 0
;
- ; NDD-NF-ZU-LABEL: name: test_cmov
- ; NDD-NF-ZU: liveins: $rdi, $rsi
- ; NDD-NF-ZU-NEXT: {{ $}}
- ; NDD-NF-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; NDD-NF-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; NDD-NF-ZU-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
- ; NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
- ; NDD-NF-ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
- ; NDD-NF-ZU-NEXT: [[SETZUCCr2:%[0-9]+]]:gr8 = SETZUCCr 4, implicit $eflags
- ; NDD-NF-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; NDD-NF-ZU-NEXT: [[CMOV64rr_ND:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
- ; NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr1]], [[SETZUCCr1]], implicit-def $eflags
- ; NDD-NF-ZU-NEXT: [[CMOV64rr_ND1:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
- ; NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
- ; NDD-NF-ZU-NEXT: [[CMOV64rr_ND2:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
- ; NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
- ; NDD-NF-ZU-NEXT: [[CMOV64rr_ND3:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
- ; NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND]]
- ; NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND1]]
- ; NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND2]]
- ; NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND3]]
- ; NDD-NF-ZU-NEXT: RET 0
+ ; NDD-ZU-LABEL: name: test_cmov
+ ; NDD-ZU: liveins: $rdi, $rsi
+ ; NDD-ZU-NEXT: {{ $}}
+ ; NDD-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; NDD-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; NDD-ZU-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
+ ; NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; NDD-ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; NDD-ZU-NEXT: [[SETZUCCr2:%[0-9]+]]:gr8 = SETZUCCr 4, implicit $eflags
+ ; NDD-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; NDD-ZU-NEXT: [[CMOV64rr_ND:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr1]], [[SETZUCCr1]], implicit-def $eflags
+ ; NDD-ZU-NEXT: [[CMOV64rr_ND1:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
+ ; NDD-ZU-NEXT: [[CMOV64rr_ND2:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
+ ; NDD-ZU-NEXT: [[CMOV64rr_ND3:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
+ ; NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND]]
+ ; NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND1]]
+ ; NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND2]]
+ ; NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND3]]
+ ; NDD-ZU-NEXT: RET 0
;
- ; O0-NDD-NF-ZU-LABEL: name: test_cmov
- ; O0-NDD-NF-ZU: liveins: $rdi, $rsi
- ; O0-NDD-NF-ZU-NEXT: {{ $}}
- ; O0-NDD-NF-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; O0-NDD-NF-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; O0-NDD-NF-ZU-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
- ; O0-NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: [[SETZUCCr2:%[0-9]+]]:gr8 = SETZUCCr 4, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; O0-NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; O0-NDD-NF-ZU-NEXT: [[CMOV64rr_ND:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
- ; O0-NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr1]], [[SETZUCCr1]], implicit-def $eflags
- ; O0-NDD-NF-ZU-NEXT: [[CMOV64rr_ND1:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
- ; O0-NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
- ; O0-NDD-NF-ZU-NEXT: [[CMOV64rr_ND2:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
- ; O0-NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
- ; O0-NDD-NF-ZU-NEXT: [[CMOV64rr_ND3:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
- ; O0-NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND]]
- ; O0-NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND1]]
- ; O0-NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND2]]
- ; O0-NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND3]]
- ; O0-NDD-NF-ZU-NEXT: RET 0
+ ; O0-NDD-ZU-LABEL: name: test_cmov
+ ; O0-NDD-ZU: liveins: $rdi, $rsi
+ ; O0-NDD-ZU-NEXT: {{ $}}
+ ; O0-NDD-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; O0-NDD-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; O0-NDD-ZU-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
+ ; O0-NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; O0-NDD-ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; O0-NDD-ZU-NEXT: [[SETZUCCr2:%[0-9]+]]:gr8 = SETZUCCr 4, implicit $eflags
+ ; O0-NDD-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; O0-NDD-ZU-NEXT: [[CMOV64rr_ND:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr1]], [[SETZUCCr1]], implicit-def $eflags
+ ; O0-NDD-ZU-NEXT: [[CMOV64rr_ND1:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
+ ; O0-NDD-ZU-NEXT: [[CMOV64rr_ND2:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
+ ; O0-NDD-ZU-NEXT: [[CMOV64rr_ND3:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
+ ; O0-NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND]]
+ ; O0-NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND1]]
+ ; O0-NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND2]]
+ ; O0-NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND3]]
+ ; O0-NDD-ZU-NEXT: RET 0
%0:gr64 = COPY $rdi
%1:gr64 = COPY $rsi
CMP64rr %0, %1, implicit-def $eflags
@@ -438,101 +358,77 @@ body: |
bb.0:
liveins: $rdi, $rsi
- ; NDD-LABEL: name: test_cfcmov
- ; NDD: liveins: $rdi, $rsi
- ; NDD-NEXT: {{ $}}
- ; NDD-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; NDD-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; NDD-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
- ; NDD-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
- ; NDD-NEXT: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
- ; NDD-NEXT: [[SETCCr2:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
- ; NDD-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; NDD-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
- ; NDD-NEXT: [[CFCMOV64rr:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
- ; NDD-NEXT: TEST8rr [[SETCCr1]], [[SETCCr1]], implicit-def $eflags
- ; NDD-NEXT: [[CFCMOV64rr1:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
- ; NDD-NEXT: TEST8rr [[SETCCr2]], [[SETCCr2]], implicit-def $eflags
- ; NDD-NEXT: [[CFCMOV64rr_ND:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
- ; NDD-NEXT: TEST8rr [[SETCCr2]], [[SETCCr2]], implicit-def $eflags
- ; NDD-NEXT: [[CFCMOV64rr_ND1:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
- ; NDD-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr]]
- ; NDD-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr1]]
- ; NDD-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND]]
- ; NDD-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND1]]
- ; NDD-NEXT: RET 0
- ;
- ; NDD-NF-LABEL: name: test_cfcmov
- ; NDD-NF: liveins: $rdi, $rsi
- ; NDD-NF-NEXT: {{ $}}
- ; NDD-NF-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; NDD-NF-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; NDD-NF-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
- ; NDD-NF-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
- ; NDD-NF-NEXT: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
- ; NDD-NF-NEXT: [[SETCCr2:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
- ; NDD-NF-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; NDD-NF-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
- ; NDD-NF-NEXT: [[CFCMOV64rr:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
- ; NDD-NF-NEXT: TEST8rr [[SETCCr1]], [[SETCCr1]], implicit-def $eflags
- ; NDD-NF-NEXT: [[CFCMOV64rr1:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
- ; NDD-NF-NEXT: TEST8rr [[SETCCr2]], [[SETCCr2]], implicit-def $eflags
- ; NDD-NF-NEXT: [[CFCMOV64rr_ND:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
- ; NDD-NF-NEXT: TEST8rr [[SETCCr2]], [[SETCCr2]], implicit-def $eflags
- ; NDD-NF-NEXT: [[CFCMOV64rr_ND1:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
- ; NDD-NF-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr]]
- ; NDD-NF-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr1]]
- ; NDD-NF-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND]]
- ; NDD-NF-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND1]]
- ; NDD-NF-NEXT: RET 0
+ ; CHECK-LABEL: name: test_cfcmov
+ ; CHECK: liveins: $rdi, $rsi
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; CHECK-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
+ ; CHECK-NEXT: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
+ ; CHECK-NEXT: [[SETCCr2:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
+ ; CHECK-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; CHECK-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
+ ; CHECK-NEXT: [[CFCMOV64rr:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
+ ; CHECK-NEXT: TEST8rr [[SETCCr1]], [[SETCCr1]], implicit-def $eflags
+ ; CHECK-NEXT: [[CFCMOV64rr1:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
+ ; CHECK-NEXT: TEST8rr [[SETCCr2]], [[SETCCr2]], implicit-def $eflags
+ ; CHECK-NEXT: [[CFCMOV64rr_ND:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; CHECK-NEXT: TEST8rr [[SETCCr2]], [[SETCCr2]], implicit-def $eflags
+ ; CHECK-NEXT: [[CFCMOV64rr_ND1:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
+ ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr]]
+ ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr1]]
+ ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND]]
+ ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND1]]
+ ; CHECK-NEXT: RET 0
;
- ; NDD-NF-ZU-LABEL: name: test_cfcmov
- ; NDD-NF-ZU: liveins: $rdi, $rsi
- ; NDD-NF-ZU-NEXT: {{ $}}
- ; NDD-NF-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; NDD-NF-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; NDD-NF-ZU-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
- ; NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
- ; NDD-NF-ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
- ; NDD-NF-ZU-NEXT: [[SETZUCCr2:%[0-9]+]]:gr8 = SETZUCCr 4, implicit $eflags
- ; NDD-NF-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; NDD-NF-ZU-NEXT: [[CFCMOV64rr:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
- ; NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr1]], [[SETZUCCr1]], implicit-def $eflags
- ; NDD-NF-ZU-NEXT: [[CFCMOV64rr1:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
- ; NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
- ; NDD-NF-ZU-NEXT: [[CFCMOV64rr_ND:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
- ; NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
- ; NDD-NF-ZU-NEXT: [[CFCMOV64rr_ND1:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
- ; NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr]]
- ; NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr1]]
- ; NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND]]
- ; NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND1]]
- ; NDD-NF-ZU-NEXT: RET 0
+ ; NDD-ZU-LABEL: name: test_cfcmov
+ ; NDD-ZU: liveins: $rdi, $rsi
+ ; NDD-ZU-NEXT: {{ $}}
+ ; NDD-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; NDD-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; NDD-ZU-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
+ ; NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; NDD-ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; NDD-ZU-NEXT: [[SETZUCCr2:%[0-9]+]]:gr8 = SETZUCCr 4, implicit $eflags
+ ; NDD-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; NDD-ZU-NEXT: [[CFCMOV64rr:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
+ ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr1]], [[SETZUCCr1]], implicit-def $eflags
+ ; NDD-ZU-NEXT: [[CFCMOV64rr1:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
+ ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
+ ; NDD-ZU-NEXT: [[CFCMOV64rr_ND:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
+ ; NDD-ZU-NEXT: [[CFCMOV64rr_ND1:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
+ ; NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr]]
+ ; NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr1]]
+ ; NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND]]
+ ; NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND1]]
+ ; NDD-ZU-NEXT: RET 0
;
- ; O0-NDD-NF-ZU-LABEL: name: test_cfcmov
- ; O0-NDD-NF-ZU: liveins: $rdi, $rsi
- ; O0-NDD-NF-ZU-NEXT: {{ $}}
- ; O0-NDD-NF-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; O0-NDD-NF-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; O0-NDD-NF-ZU-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
- ; O0-NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: [[SETZUCCr2:%[0-9]+]]:gr8 = SETZUCCr 4, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; O0-NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; O0-NDD-NF-ZU-NEXT: [[CFCMOV64rr:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
- ; O0-NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr1]], [[SETZUCCr1]], implicit-def $eflags
- ; O0-NDD-NF-ZU-NEXT: [[CFCMOV64rr1:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
- ; O0-NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
- ; O0-NDD-NF-ZU-NEXT: [[CFCMOV64rr_ND:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
- ; O0-NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
- ; O0-NDD-NF-ZU-NEXT: [[CFCMOV64rr_ND1:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
- ; O0-NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr]]
- ; O0-NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr1]]
- ; O0-NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND]]
- ; O0-NDD-NF-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND1]]
- ; O0-NDD-NF-ZU-NEXT: RET 0
+ ; O0-NDD-ZU-LABEL: name: test_cfcmov
+ ; O0-NDD-ZU: liveins: $rdi, $rsi
+ ; O0-NDD-ZU-NEXT: {{ $}}
+ ; O0-NDD-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; O0-NDD-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; O0-NDD-ZU-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
+ ; O0-NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; O0-NDD-ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; O0-NDD-ZU-NEXT: [[SETZUCCr2:%[0-9]+]]:gr8 = SETZUCCr 4, implicit $eflags
+ ; O0-NDD-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; O0-NDD-ZU-NEXT: [[CFCMOV64rr:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
+ ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr1]], [[SETZUCCr1]], implicit-def $eflags
+ ; O0-NDD-ZU-NEXT: [[CFCMOV64rr1:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
+ ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
+ ; O0-NDD-ZU-NEXT: [[CFCMOV64rr_ND:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
+ ; O0-NDD-ZU-NEXT: [[CFCMOV64rr_ND1:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
+ ; O0-NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr]]
+ ; O0-NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr1]]
+ ; O0-NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND]]
+ ; O0-NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND1]]
+ ; O0-NDD-ZU-NEXT: RET 0
%0:gr64 = COPY $rdi
%1:gr64 = COPY $rsi
CMP64rr %0, %1, implicit-def $eflags
@@ -568,6 +464,26 @@ body: |
; NDD-NEXT: CCMP32rr [[ADD32rr]], [[ADD32rr]], 0, 5, implicit-def $eflags, implicit killed $eflags
; NDD-NEXT: RET 0, $al
;
+ ; NDD-ZU-LABEL: name: test_ccmp
+ ; NDD-ZU: liveins: $edi
+ ; NDD-ZU-NEXT: {{ $}}
+ ; NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 1, implicit $eflags
+ ; NDD-ZU-NEXT: [[ADD32rr:%[0-9]+]]:gr32 = ADD32rr $edi, $edi, implicit-def dead $eflags
+ ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; NDD-ZU-NEXT: CCMP32rr [[ADD32rr]], [[ADD32rr]], 0, 5, implicit-def $eflags, implicit killed $eflags
+ ; NDD-ZU-NEXT: RET 0, $al
+ ;
+ ; O0-NDD-ZU-LABEL: name: test_ccmp
+ ; O0-NDD-ZU: liveins: $edi
+ ; O0-NDD-ZU-NEXT: {{ $}}
+ ; O0-NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; O0-NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 1, implicit $eflags
+ ; O0-NDD-ZU-NEXT: [[ADD32rr:%[0-9]+]]:gr32 = ADD32rr $edi, $edi, implicit-def dead $eflags
+ ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; O0-NDD-ZU-NEXT: CCMP32rr [[ADD32rr]], [[ADD32rr]], 0, 5, implicit-def $eflags, implicit killed $eflags
+ ; O0-NDD-ZU-NEXT: RET 0, $al
+ ;
; NDD-NF-LABEL: name: test_ccmp
; NDD-NF: liveins: $edi
; NDD-NF-NEXT: {{ $}}
@@ -575,22 +491,6 @@ body: |
; NDD-NF-NEXT: [[ADD32rr_NF:%[0-9]+]]:gr32 = ADD32rr_NF $edi, $edi
; NDD-NF-NEXT: CCMP32rr [[ADD32rr_NF]], [[ADD32rr_NF]], 0, 1, implicit-def $eflags, implicit $eflags
; NDD-NF-NEXT: RET 0, $al
- ;
- ; NDD-NF-ZU-LABEL: name: test_ccmp
- ; NDD-NF-ZU: liveins: $edi
- ; NDD-NF-ZU-NEXT: {{ $}}
- ; NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; NDD-NF-ZU-NEXT: [[ADD32rr_NF:%[0-9]+]]:gr32 = ADD32rr_NF $edi, $edi
- ; NDD-NF-ZU-NEXT: CCMP32rr [[ADD32rr_NF]], [[ADD32rr_NF]], 0, 1, implicit-def $eflags, implicit $eflags
- ; NDD-NF-ZU-NEXT: RET 0, $al
- ;
- ; O0-NDD-NF-ZU-LABEL: name: test_ccmp
- ; O0-NDD-NF-ZU: liveins: $edi
- ; O0-NDD-NF-ZU-NEXT: {{ $}}
- ; O0-NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; O0-NDD-NF-ZU-NEXT: [[ADD32rr_NF:%[0-9]+]]:gr32 = ADD32rr_NF $edi, $edi
- ; O0-NDD-NF-ZU-NEXT: CCMP32rr [[ADD32rr_NF]], [[ADD32rr_NF]], 0, 1, implicit-def $eflags, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: RET 0, $al
MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
%1:gr64 = COPY $eflags
%2:gr32 = ADD32rr $edi, $edi, implicit-def dead $eflags
@@ -615,6 +515,26 @@ body: |
; NDD-NEXT: CTEST32rr [[ADD32rr]], [[ADD32rr]], 0, 5, implicit-def $eflags, implicit killed $eflags
; NDD-NEXT: RET 0, $al
;
+ ; NDD-ZU-LABEL: name: test_ctest
+ ; NDD-ZU: liveins: $edi
+ ; NDD-ZU-NEXT: {{ $}}
+ ; NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 1, implicit $eflags
+ ; NDD-ZU-NEXT: [[ADD32rr:%[0-9]+]]:gr32 = ADD32rr $edi, $edi, implicit-def dead $eflags
+ ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; NDD-ZU-NEXT: CTEST32rr [[ADD32rr]], [[ADD32rr]], 0, 5, implicit-def $eflags, implicit killed $eflags
+ ; NDD-ZU-NEXT: RET 0, $al
+ ;
+ ; O0-NDD-ZU-LABEL: name: test_ctest
+ ; O0-NDD-ZU: liveins: $edi
+ ; O0-NDD-ZU-NEXT: {{ $}}
+ ; O0-NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; O0-NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 1, implicit $eflags
+ ; O0-NDD-ZU-NEXT: [[ADD32rr:%[0-9]+]]:gr32 = ADD32rr $edi, $edi, implicit-def dead $eflags
+ ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; O0-NDD-ZU-NEXT: CTEST32rr [[ADD32rr]], [[ADD32rr]], 0, 5, implicit-def $eflags, implicit killed $eflags
+ ; O0-NDD-ZU-NEXT: RET 0, $al
+ ;
; NDD-NF-LABEL: name: test_ctest
; NDD-NF: liveins: $edi
; NDD-NF-NEXT: {{ $}}
@@ -622,22 +542,6 @@ body: |
; NDD-NF-NEXT: [[ADD32rr_NF:%[0-9]+]]:gr32 = ADD32rr_NF $edi, $edi
; NDD-NF-NEXT: CTEST32rr [[ADD32rr_NF]], [[ADD32rr_NF]], 0, 1, implicit-def $eflags, implicit $eflags
; NDD-NF-NEXT: RET 0, $al
- ;
- ; NDD-NF-ZU-LABEL: name: test_ctest
- ; NDD-NF-ZU: liveins: $edi
- ; NDD-NF-ZU-NEXT: {{ $}}
- ; NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; NDD-NF-ZU-NEXT: [[ADD32rr_NF:%[0-9]+]]:gr32 = ADD32rr_NF $edi, $edi
- ; NDD-NF-ZU-NEXT: CTEST32rr [[ADD32rr_NF]], [[ADD32rr_NF]], 0, 1, implicit-def $eflags, implicit $eflags
- ; NDD-NF-ZU-NEXT: RET 0, $al
- ;
- ; O0-NDD-NF-ZU-LABEL: name: test_ctest
- ; O0-NDD-NF-ZU: liveins: $edi
- ; O0-NDD-NF-ZU-NEXT: {{ $}}
- ; O0-NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; O0-NDD-NF-ZU-NEXT: [[ADD32rr_NF:%[0-9]+]]:gr32 = ADD32rr_NF $edi, $edi
- ; O0-NDD-NF-ZU-NEXT: CTEST32rr [[ADD32rr_NF]], [[ADD32rr_NF]], 0, 1, implicit-def $eflags, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: RET 0, $al
MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
%1:gr64 = COPY $eflags
%2:gr32 = ADD32rr $edi, $edi, implicit-def dead $eflags
@@ -662,6 +566,26 @@ body: |
; NDD-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND]], 5, implicit killed $eflags
; NDD-NEXT: RET 0, $al
;
+ ; NDD-ZU-LABEL: name: test_evitable_clobber
+ ; NDD-ZU: liveins: $edi
+ ; NDD-ZU-NEXT: {{ $}}
+ ; NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; NDD-ZU-NEXT: [[ADD32rr_ND:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
+ ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND]], 5, implicit killed $eflags
+ ; NDD-ZU-NEXT: RET 0, $al
+ ;
+ ; O0-NDD-ZU-LABEL: name: test_evitable_clobber
+ ; O0-NDD-ZU: liveins: $edi
+ ; O0-NDD-ZU-NEXT: {{ $}}
+ ; O0-NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; O0-NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; O0-NDD-ZU-NEXT: [[ADD32rr_ND:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
+ ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; O0-NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND]], 5, implicit killed $eflags
+ ; O0-NDD-ZU-NEXT: RET 0, $al
+ ;
; NDD-NF-LABEL: name: test_evitable_clobber
; NDD-NF: liveins: $edi
; NDD-NF-NEXT: {{ $}}
@@ -669,22 +593,6 @@ body: |
; NDD-NF-NEXT: [[ADD32rr_NF_ND:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $edi
; NDD-NF-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND]], 7, implicit $eflags
; NDD-NF-NEXT: RET 0, $al
- ;
- ; NDD-NF-ZU-LABEL: name: test_evitable_clobber
- ; NDD-NF-ZU: liveins: $edi
- ; NDD-NF-ZU-NEXT: {{ $}}
- ; NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; NDD-NF-ZU-NEXT: [[ADD32rr_NF_ND:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $edi
- ; NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND]], 7, implicit $eflags
- ; NDD-NF-ZU-NEXT: RET 0, $al
- ;
- ; O0-NDD-NF-ZU-LABEL: name: test_evitable_clobber
- ; O0-NDD-NF-ZU: liveins: $edi
- ; O0-NDD-NF-ZU-NEXT: {{ $}}
- ; O0-NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; O0-NDD-NF-ZU-NEXT: [[ADD32rr_NF_ND:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $edi
- ; O0-NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND]], 7, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: RET 0, $al
MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
%1:gr64 = COPY $eflags
%2:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
@@ -699,45 +607,35 @@ body: |
bb.0:
liveins: $edi
- ; NDD-LABEL: name: test_inevitable_clobber
- ; NDD: liveins: $edi
- ; NDD-NEXT: {{ $}}
- ; NDD-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; NDD-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
- ; NDD-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
- ; NDD-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
- ; NDD-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
- ; NDD-NEXT: RET 0, $al
- ;
- ; NDD-NF-LABEL: name: test_inevitable_clobber
- ; NDD-NF: liveins: $edi
- ; NDD-NF-NEXT: {{ $}}
- ; NDD-NF-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; NDD-NF-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
- ; NDD-NF-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
- ; NDD-NF-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
- ; NDD-NF-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
- ; NDD-NF-NEXT: RET 0, $al
+ ; CHECK-LABEL: name: test_inevitable_clobber
+ ; CHECK: liveins: $edi
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
+ ; CHECK-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
+ ; CHECK-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
+ ; CHECK-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
+ ; CHECK-NEXT: RET 0, $al
;
- ; NDD-NF-ZU-LABEL: name: test_inevitable_clobber
- ; NDD-NF-ZU: liveins: $edi
- ; NDD-NF-ZU-NEXT: {{ $}}
- ; NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
- ; NDD-NF-ZU-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
- ; NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
- ; NDD-NF-ZU-NEXT: RET 0, $al
+ ; NDD-ZU-LABEL: name: test_inevitable_clobber
+ ; NDD-ZU: liveins: $edi
+ ; NDD-ZU-NEXT: {{ $}}
+ ; NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; NDD-ZU-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
+ ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
+ ; NDD-ZU-NEXT: RET 0, $al
;
- ; O0-NDD-NF-ZU-LABEL: name: test_inevitable_clobber
- ; O0-NDD-NF-ZU: liveins: $edi
- ; O0-NDD-NF-ZU-NEXT: {{ $}}
- ; O0-NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; O0-NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; O0-NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
- ; O0-NDD-NF-ZU-NEXT: RET 0, $al
+ ; O0-NDD-ZU-LABEL: name: test_inevitable_clobber
+ ; O0-NDD-ZU: liveins: $edi
+ ; O0-NDD-ZU-NEXT: {{ $}}
+ ; O0-NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; O0-NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; O0-NDD-ZU-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
+ ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; O0-NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
+ ; O0-NDD-ZU-NEXT: RET 0, $al
MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
%1:gr64 = COPY $eflags
%2:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
@@ -765,6 +663,34 @@ body: |
; NDD-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND1]], 5, implicit killed $eflags
; NDD-NEXT: RET 0, $al
;
+ ; NDD-ZU-LABEL: name: test_evitable_clobber_multiple_uses
+ ; NDD-ZU: liveins: $edi
+ ; NDD-ZU-NEXT: {{ $}}
+ ; NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; NDD-ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 9, implicit $eflags
+ ; NDD-ZU-NEXT: [[ADD32rr_ND:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
+ ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND]], 5, implicit killed $eflags
+ ; NDD-ZU-NEXT: [[ADD32rr_ND1:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $eax, implicit-def dead $eflags
+ ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr1]], [[SETZUCCr1]], implicit-def $eflags
+ ; NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND1]], 5, implicit killed $eflags
+ ; NDD-ZU-NEXT: RET 0, $al
+ ;
+ ; O0-NDD-ZU-LABEL: name: test_evitable_clobber_multiple_uses
+ ; O0-NDD-ZU: liveins: $edi
+ ; O0-NDD-ZU-NEXT: {{ $}}
+ ; O0-NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; O0-NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; O0-NDD-ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 9, implicit $eflags
+ ; O0-NDD-ZU-NEXT: [[ADD32rr_ND:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
+ ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; O0-NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND]], 5, implicit killed $eflags
+ ; O0-NDD-ZU-NEXT: [[ADD32rr_ND1:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $eax, implicit-def dead $eflags
+ ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr1]], [[SETZUCCr1]], implicit-def $eflags
+ ; O0-NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND1]], 5, implicit killed $eflags
+ ; O0-NDD-ZU-NEXT: RET 0, $al
+ ;
; NDD-NF-LABEL: name: test_evitable_clobber_multiple_uses
; NDD-NF: liveins: $edi
; NDD-NF-NEXT: {{ $}}
@@ -774,26 +700,6 @@ body: |
; NDD-NF-NEXT: [[ADD32rr_NF_ND1:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $eax
; NDD-NF-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND1]], 9, implicit $eflags
; NDD-NF-NEXT: RET 0, $al
- ;
- ; NDD-NF-ZU-LABEL: name: test_evitable_clobber_multiple_uses
- ; NDD-NF-ZU: liveins: $edi
- ; NDD-NF-ZU-NEXT: {{ $}}
- ; NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; NDD-NF-ZU-NEXT: [[ADD32rr_NF_ND:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $edi
- ; NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND]], 7, implicit $eflags
- ; NDD-NF-ZU-NEXT: [[ADD32rr_NF_ND1:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $eax
- ; NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND1]], 9, implicit $eflags
- ; NDD-NF-ZU-NEXT: RET 0, $al
- ;
- ; O0-NDD-NF-ZU-LABEL: name: test_evitable_clobber_multiple_uses
- ; O0-NDD-NF-ZU: liveins: $edi
- ; O0-NDD-NF-ZU-NEXT: {{ $}}
- ; O0-NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; O0-NDD-NF-ZU-NEXT: [[ADD32rr_NF_ND:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $edi
- ; O0-NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND]], 7, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: [[ADD32rr_NF_ND1:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $eax
- ; O0-NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND1]], 9, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: RET 0, $al
MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
%1:gr64 = COPY $eflags
%2:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
@@ -826,6 +732,36 @@ body: |
; NDD-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND]], 5, implicit killed $eflags
; NDD-NEXT: RET 0, $al
;
+ ; NDD-ZU-LABEL: name: test_mixed_clobber
+ ; NDD-ZU: liveins: $edi
+ ; NDD-ZU-NEXT: {{ $}}
+ ; NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; NDD-ZU-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
+ ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
+ ; NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; NDD-ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 1, implicit $eflags
+ ; NDD-ZU-NEXT: [[ADD32rr_ND:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
+ ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr1]], [[SETZUCCr1]], implicit-def $eflags
+ ; NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND]], 5, implicit killed $eflags
+ ; NDD-ZU-NEXT: RET 0, $al
+ ;
+ ; O0-NDD-ZU-LABEL: name: test_mixed_clobber
+ ; O0-NDD-ZU: liveins: $edi
+ ; O0-NDD-ZU-NEXT: {{ $}}
+ ; O0-NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; O0-NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; O0-NDD-ZU-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
+ ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; O0-NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
+ ; O0-NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; O0-NDD-ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 1, implicit $eflags
+ ; O0-NDD-ZU-NEXT: [[ADD32rr_ND:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
+ ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr1]], [[SETZUCCr1]], implicit-def $eflags
+ ; O0-NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND]], 5, implicit killed $eflags
+ ; O0-NDD-ZU-NEXT: RET 0, $al
+ ;
; NDD-NF-LABEL: name: test_mixed_clobber
; NDD-NF: liveins: $edi
; NDD-NF-NEXT: {{ $}}
@@ -838,32 +774,6 @@ body: |
; NDD-NF-NEXT: [[ADD32rr_NF_ND:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $edi
; NDD-NF-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND]], 1, implicit $eflags
; NDD-NF-NEXT: RET 0, $al
- ;
- ; NDD-NF-ZU-LABEL: name: test_mixed_clobber
- ; NDD-NF-ZU: liveins: $edi
- ; NDD-NF-ZU-NEXT: {{ $}}
- ; NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
- ; NDD-NF-ZU-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
- ; NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
- ; NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; NDD-NF-ZU-NEXT: [[ADD32rr_NF_ND:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $edi
- ; NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND]], 1, implicit $eflags
- ; NDD-NF-ZU-NEXT: RET 0, $al
- ;
- ; O0-NDD-NF-ZU-LABEL: name: test_mixed_clobber
- ; O0-NDD-NF-ZU: liveins: $edi
- ; O0-NDD-NF-ZU-NEXT: {{ $}}
- ; O0-NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; O0-NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; O0-NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
- ; O0-NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; O0-NDD-NF-ZU-NEXT: [[ADD32rr_NF_ND:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $edi
- ; O0-NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND]], 1, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: RET 0, $al
MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
%1:gr64 = COPY $eflags
%2:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
@@ -898,6 +808,44 @@ body: |
; NDD-NEXT: $eax = ADC32rr_ND $eax, $edi, implicit-def dead $eflags, implicit killed $eflags
; NDD-NEXT: RET 0, $al
;
+ ; NDD-ZU-LABEL: name: test_evitable_clobber_crossbb
+ ; NDD-ZU: bb.0:
+ ; NDD-ZU-NEXT: successors: %bb.1(0x80000000)
+ ; NDD-ZU-NEXT: liveins: $edi
+ ; NDD-ZU-NEXT: {{ $}}
+ ; NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; NDD-ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; NDD-ZU-NEXT: [[ADD32rr_ND:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
+ ; NDD-ZU-NEXT: JCC_1 %bb.1, 4, implicit $eflags
+ ; NDD-ZU-NEXT: RET 0, $al
+ ; NDD-ZU-NEXT: {{ $}}
+ ; NDD-ZU-NEXT: bb.1:
+ ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND]], 5, implicit killed $eflags
+ ; NDD-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr1]], 255, implicit-def $eflags
+ ; NDD-ZU-NEXT: $eax = ADC32rr_ND $eax, $edi, implicit-def dead $eflags, implicit killed $eflags
+ ; NDD-ZU-NEXT: RET 0, $al
+ ;
+ ; O0-NDD-ZU-LABEL: name: test_evitable_clobber_crossbb
+ ; O0-NDD-ZU: bb.0:
+ ; O0-NDD-ZU-NEXT: successors: %bb.1(0x80000000)
+ ; O0-NDD-ZU-NEXT: liveins: $edi
+ ; O0-NDD-ZU-NEXT: {{ $}}
+ ; O0-NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; O0-NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; O0-NDD-ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; O0-NDD-ZU-NEXT: [[ADD32rr_ND:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
+ ; O0-NDD-ZU-NEXT: JCC_1 %bb.1, 4, implicit $eflags
+ ; O0-NDD-ZU-NEXT: RET 0, $al
+ ; O0-NDD-ZU-NEXT: {{ $}}
+ ; O0-NDD-ZU-NEXT: bb.1:
+ ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; O0-NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND]], 5, implicit killed $eflags
+ ; O0-NDD-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr1]], 255, implicit-def $eflags
+ ; O0-NDD-ZU-NEXT: $eax = ADC32rr_ND $eax, $edi, implicit-def dead $eflags, implicit killed $eflags
+ ; O0-NDD-ZU-NEXT: RET 0, $al
+ ;
; NDD-NF-LABEL: name: test_evitable_clobber_crossbb
; NDD-NF: bb.0:
; NDD-NF-NEXT: successors: %bb.1(0x80000000)
@@ -914,40 +862,7 @@ body: |
; NDD-NF-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND]], 7, implicit $eflags
; NDD-NF-NEXT: $eax = ADC32rr_ND $eax, $edi, implicit-def dead $eflags, implicit $eflags
; NDD-NF-NEXT: RET 0, $al
- ;
- ; NDD-NF-ZU-LABEL: name: test_evitable_clobber_crossbb
- ; NDD-NF-ZU: bb.0:
- ; NDD-NF-ZU-NEXT: successors: %bb.1(0x80000000)
- ; NDD-NF-ZU-NEXT: liveins: $edi
- ; NDD-NF-ZU-NEXT: {{ $}}
- ; NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; NDD-NF-ZU-NEXT: [[ADD32rr_NF_ND:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $edi
- ; NDD-NF-ZU-NEXT: JCC_1 %bb.1, 4, implicit $eflags
- ; NDD-NF-ZU-NEXT: RET 0, $al
- ; NDD-NF-ZU-NEXT: {{ $}}
- ; NDD-NF-ZU-NEXT: bb.1:
- ; NDD-NF-ZU-NEXT: liveins: $eflags
- ; NDD-NF-ZU-NEXT: {{ $}}
- ; NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND]], 7, implicit $eflags
- ; NDD-NF-ZU-NEXT: $eax = ADC32rr_ND $eax, $edi, implicit-def dead $eflags, implicit $eflags
- ; NDD-NF-ZU-NEXT: RET 0, $al
- ;
- ; O0-NDD-NF-ZU-LABEL: name: test_evitable_clobber_crossbb
- ; O0-NDD-NF-ZU: bb.0:
- ; O0-NDD-NF-ZU-NEXT: successors: %bb.1(0x80000000)
- ; O0-NDD-NF-ZU-NEXT: liveins: $edi
- ; O0-NDD-NF-ZU-NEXT: {{ $}}
- ; O0-NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; O0-NDD-NF-ZU-NEXT: [[ADD32rr_NF_ND:%[0-9]+]]:gr32 = ADD32rr_NF_ND $edi, $edi
- ; O0-NDD-NF-ZU-NEXT: JCC_1 %bb.1, 4, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: RET 0, $al
- ; O0-NDD-NF-ZU-NEXT: {{ $}}
- ; O0-NDD-NF-ZU-NEXT: bb.1:
- ; O0-NDD-NF-ZU-NEXT: liveins: $eflags
- ; O0-NDD-NF-ZU-NEXT: {{ $}}
- ; O0-NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_NF_ND]], 7, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: $eax = ADC32rr_ND $eax, $edi, implicit-def dead $eflags, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: RET 0, $al
+
bb.0:
liveins: $edi
@@ -966,69 +881,54 @@ body: |
---
name: test_inevitable_clobber_crossbb
body: |
- ; NDD-LABEL: name: test_inevitable_clobber_crossbb
- ; NDD: bb.0:
- ; NDD-NEXT: successors: %bb.1(0x80000000)
- ; NDD-NEXT: liveins: $edi
- ; NDD-NEXT: {{ $}}
- ; NDD-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; NDD-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
- ; NDD-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
- ; NDD-NEXT: JCC_1 %bb.1, 4, implicit $eflags
- ; NDD-NEXT: RET 0, $al
- ; NDD-NEXT: {{ $}}
- ; NDD-NEXT: bb.1:
- ; NDD-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
- ; NDD-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
- ; NDD-NEXT: RET 0, $al
- ;
- ; NDD-NF-LABEL: name: test_inevitable_clobber_crossbb
- ; NDD-NF: bb.0:
- ; NDD-NF-NEXT: successors: %bb.1(0x80000000)
- ; NDD-NF-NEXT: liveins: $edi
- ; NDD-NF-NEXT: {{ $}}
- ; NDD-NF-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; NDD-NF-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
- ; NDD-NF-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
- ; NDD-NF-NEXT: JCC_1 %bb.1, 4, implicit $eflags
- ; NDD-NF-NEXT: RET 0, $al
- ; NDD-NF-NEXT: {{ $}}
- ; NDD-NF-NEXT: bb.1:
- ; NDD-NF-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
- ; NDD-NF-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
- ; NDD-NF-NEXT: RET 0, $al
+ ; CHECK-LABEL: name: test_inevitable_clobber_crossbb
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $edi
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
+ ; CHECK-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
+ ; CHECK-NEXT: JCC_1 %bb.1, 4, implicit $eflags
+ ; CHECK-NEXT: RET 0, $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
+ ; CHECK-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
+ ; CHECK-NEXT: RET 0, $al
;
- ; NDD-NF-ZU-LABEL: name: test_inevitable_clobber_crossbb
- ; NDD-NF-ZU: bb.0:
- ; NDD-NF-ZU-NEXT: successors: %bb.1(0x80000000)
- ; NDD-NF-ZU-NEXT: liveins: $edi
- ; NDD-NF-ZU-NEXT: {{ $}}
- ; NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
- ; NDD-NF-ZU-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
- ; NDD-NF-ZU-NEXT: JCC_1 %bb.1, 4, implicit $eflags
- ; NDD-NF-ZU-NEXT: RET 0, $al
- ; NDD-NF-ZU-NEXT: {{ $}}
- ; NDD-NF-ZU-NEXT: bb.1:
- ; NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
- ; NDD-NF-ZU-NEXT: RET 0, $al
+ ; NDD-ZU-LABEL: name: test_inevitable_clobber_crossbb
+ ; NDD-ZU: bb.0:
+ ; NDD-ZU-NEXT: successors: %bb.1(0x80000000)
+ ; NDD-ZU-NEXT: liveins: $edi
+ ; NDD-ZU-NEXT: {{ $}}
+ ; NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; NDD-ZU-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
+ ; NDD-ZU-NEXT: JCC_1 %bb.1, 4, implicit $eflags
+ ; NDD-ZU-NEXT: RET 0, $al
+ ; NDD-ZU-NEXT: {{ $}}
+ ; NDD-ZU-NEXT: bb.1:
+ ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
+ ; NDD-ZU-NEXT: RET 0, $al
;
- ; O0-NDD-NF-ZU-LABEL: name: test_inevitable_clobber_crossbb
- ; O0-NDD-NF-ZU: bb.0:
- ; O0-NDD-NF-ZU-NEXT: successors: %bb.1(0x80000000)
- ; O0-NDD-NF-ZU-NEXT: liveins: $edi
- ; O0-NDD-NF-ZU-NEXT: {{ $}}
- ; O0-NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; O0-NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: JCC_1 %bb.1, 4, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: RET 0, $al
- ; O0-NDD-NF-ZU-NEXT: {{ $}}
- ; O0-NDD-NF-ZU-NEXT: bb.1:
- ; O0-NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; O0-NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
- ; O0-NDD-NF-ZU-NEXT: RET 0, $al
+ ; O0-NDD-ZU-LABEL: name: test_inevitable_clobber_crossbb
+ ; O0-NDD-ZU: bb.0:
+ ; O0-NDD-ZU-NEXT: successors: %bb.1(0x80000000)
+ ; O0-NDD-ZU-NEXT: liveins: $edi
+ ; O0-NDD-ZU-NEXT: {{ $}}
+ ; O0-NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; O0-NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; O0-NDD-ZU-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
+ ; O0-NDD-ZU-NEXT: JCC_1 %bb.1, 4, implicit $eflags
+ ; O0-NDD-ZU-NEXT: RET 0, $al
+ ; O0-NDD-ZU-NEXT: {{ $}}
+ ; O0-NDD-ZU-NEXT: bb.1:
+ ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; O0-NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
+ ; O0-NDD-ZU-NEXT: RET 0, $al
+
bb.0:
liveins: $edi
@@ -1073,6 +973,60 @@ body: |
; NDD-NEXT: $eax = CMOV32rr_ND $edi, [[SUB32rr_ND]], 5, implicit killed $eflags
; NDD-NEXT: RET 0, $al
;
+ ; NDD-ZU-LABEL: name: test_evitable_clobber_crossbb_complex
+ ; NDD-ZU: bb.0:
+ ; NDD-ZU-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; NDD-ZU-NEXT: liveins: $edi
+ ; NDD-ZU-NEXT: {{ $}}
+ ; NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; NDD-ZU-NEXT: [[SUB32rr_ND:%[0-9]+]]:gr32 = SUB32rr_ND $edi, $edi, implicit-def dead $eflags
+ ; NDD-ZU-NEXT: JCC_1 %bb.2, 4, implicit $eflags
+ ; NDD-ZU-NEXT: {{ $}}
+ ; NDD-ZU-NEXT: bb.1:
+ ; NDD-ZU-NEXT: successors: %bb.3(0x80000000)
+ ; NDD-ZU-NEXT: {{ $}}
+ ; NDD-ZU-NEXT: $eax = IMUL32rr_ND $eax, $edi, implicit-def dead $eflags
+ ; NDD-ZU-NEXT: JMP_1 %bb.3
+ ; NDD-ZU-NEXT: {{ $}}
+ ; NDD-ZU-NEXT: bb.2:
+ ; NDD-ZU-NEXT: successors: %bb.3(0x80000000)
+ ; NDD-ZU-NEXT: {{ $}}
+ ; NDD-ZU-NEXT: $eax = IMUL32rr $eax, $esi, implicit-def dead $eflags
+ ; NDD-ZU-NEXT: JMP_1 %bb.3
+ ; NDD-ZU-NEXT: {{ $}}
+ ; NDD-ZU-NEXT: bb.3:
+ ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[SUB32rr_ND]], 5, implicit killed $eflags
+ ; NDD-ZU-NEXT: RET 0, $al
+ ;
+ ; O0-NDD-ZU-LABEL: name: test_evitable_clobber_crossbb_complex
+ ; O0-NDD-ZU: bb.0:
+ ; O0-NDD-ZU-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; O0-NDD-ZU-NEXT: liveins: $edi
+ ; O0-NDD-ZU-NEXT: {{ $}}
+ ; O0-NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; O0-NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; O0-NDD-ZU-NEXT: [[SUB32rr_ND:%[0-9]+]]:gr32 = SUB32rr_ND $edi, $edi, implicit-def dead $eflags
+ ; O0-NDD-ZU-NEXT: JCC_1 %bb.2, 4, implicit $eflags
+ ; O0-NDD-ZU-NEXT: {{ $}}
+ ; O0-NDD-ZU-NEXT: bb.1:
+ ; O0-NDD-ZU-NEXT: successors: %bb.3(0x80000000)
+ ; O0-NDD-ZU-NEXT: {{ $}}
+ ; O0-NDD-ZU-NEXT: $eax = IMUL32rr_ND $eax, $edi, implicit-def dead $eflags
+ ; O0-NDD-ZU-NEXT: JMP_1 %bb.3
+ ; O0-NDD-ZU-NEXT: {{ $}}
+ ; O0-NDD-ZU-NEXT: bb.2:
+ ; O0-NDD-ZU-NEXT: successors: %bb.3(0x80000000)
+ ; O0-NDD-ZU-NEXT: {{ $}}
+ ; O0-NDD-ZU-NEXT: $eax = IMUL32rr $eax, $esi, implicit-def dead $eflags
+ ; O0-NDD-ZU-NEXT: JMP_1 %bb.3
+ ; O0-NDD-ZU-NEXT: {{ $}}
+ ; O0-NDD-ZU-NEXT: bb.3:
+ ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; O0-NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[SUB32rr_ND]], 5, implicit killed $eflags
+ ; O0-NDD-ZU-NEXT: RET 0, $al
+ ;
; NDD-NF-LABEL: name: test_evitable_clobber_crossbb_complex
; NDD-NF: bb.0:
; NDD-NF-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
@@ -1101,64 +1055,7 @@ body: |
; NDD-NF-NEXT: {{ $}}
; NDD-NF-NEXT: $eax = CMOV32rr_ND $edi, [[SUB32rr_NF_ND]], 7, implicit $eflags
; NDD-NF-NEXT: RET 0, $al
- ;
- ; NDD-NF-ZU-LABEL: name: test_evitable_clobber_crossbb_complex
- ; NDD-NF-ZU: bb.0:
- ; NDD-NF-ZU-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; NDD-NF-ZU-NEXT: liveins: $edi
- ; NDD-NF-ZU-NEXT: {{ $}}
- ; NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; NDD-NF-ZU-NEXT: [[SUB32rr_NF_ND:%[0-9]+]]:gr32 = SUB32rr_NF_ND $edi, $edi
- ; NDD-NF-ZU-NEXT: JCC_1 %bb.2, 4, implicit $eflags
- ; NDD-NF-ZU-NEXT: {{ $}}
- ; NDD-NF-ZU-NEXT: bb.1:
- ; NDD-NF-ZU-NEXT: successors: %bb.3(0x80000000)
- ; NDD-NF-ZU-NEXT: liveins: $eflags
- ; NDD-NF-ZU-NEXT: {{ $}}
- ; NDD-NF-ZU-NEXT: $eax = IMUL32rr_NF_ND $eax, $edi
- ; NDD-NF-ZU-NEXT: JMP_1 %bb.3
- ; NDD-NF-ZU-NEXT: {{ $}}
- ; NDD-NF-ZU-NEXT: bb.2:
- ; NDD-NF-ZU-NEXT: successors: %bb.3(0x80000000)
- ; NDD-NF-ZU-NEXT: liveins: $eflags
- ; NDD-NF-ZU-NEXT: {{ $}}
- ; NDD-NF-ZU-NEXT: $eax = IMUL32rr_NF $eax, $esi
- ; NDD-NF-ZU-NEXT: JMP_1 %bb.3
- ; NDD-NF-ZU-NEXT: {{ $}}
- ; NDD-NF-ZU-NEXT: bb.3:
- ; NDD-NF-ZU-NEXT: liveins: $eflags
- ; NDD-NF-ZU-NEXT: {{ $}}
- ; NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[SUB32rr_NF_ND]], 7, implicit $eflags
- ; NDD-NF-ZU-NEXT: RET 0, $al
- ;
- ; O0-NDD-NF-ZU-LABEL: name: test_evitable_clobber_crossbb_complex
- ; O0-NDD-NF-ZU: bb.0:
- ; O0-NDD-NF-ZU-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; O0-NDD-NF-ZU-NEXT: liveins: $edi
- ; O0-NDD-NF-ZU-NEXT: {{ $}}
- ; O0-NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; O0-NDD-NF-ZU-NEXT: [[SUB32rr_NF_ND:%[0-9]+]]:gr32 = SUB32rr_NF_ND $edi, $edi
- ; O0-NDD-NF-ZU-NEXT: JCC_1 %bb.2, 4, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: {{ $}}
- ; O0-NDD-NF-ZU-NEXT: bb.1:
- ; O0-NDD-NF-ZU-NEXT: successors: %bb.3(0x80000000)
- ; O0-NDD-NF-ZU-NEXT: liveins: $eflags
- ; O0-NDD-NF-ZU-NEXT: {{ $}}
- ; O0-NDD-NF-ZU-NEXT: $eax = IMUL32rr_NF_ND $eax, $edi
- ; O0-NDD-NF-ZU-NEXT: JMP_1 %bb.3
- ; O0-NDD-NF-ZU-NEXT: {{ $}}
- ; O0-NDD-NF-ZU-NEXT: bb.2:
- ; O0-NDD-NF-ZU-NEXT: successors: %bb.3(0x80000000)
- ; O0-NDD-NF-ZU-NEXT: liveins: $eflags
- ; O0-NDD-NF-ZU-NEXT: {{ $}}
- ; O0-NDD-NF-ZU-NEXT: $eax = IMUL32rr_NF $eax, $esi
- ; O0-NDD-NF-ZU-NEXT: JMP_1 %bb.3
- ; O0-NDD-NF-ZU-NEXT: {{ $}}
- ; O0-NDD-NF-ZU-NEXT: bb.3:
- ; O0-NDD-NF-ZU-NEXT: liveins: $eflags
- ; O0-NDD-NF-ZU-NEXT: {{ $}}
- ; O0-NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[SUB32rr_NF_ND]], 7, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: RET 0, $al
+
bb.0:
liveins: $edi
@@ -1183,113 +1080,87 @@ body: |
---
name: test_inevitable_clobber_crossbb_complex
body: |
- ; NDD-LABEL: name: test_inevitable_clobber_crossbb_complex
- ; NDD: bb.0:
- ; NDD-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; NDD-NEXT: liveins: $edi
- ; NDD-NEXT: {{ $}}
- ; NDD-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; NDD-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
- ; NDD-NEXT: [[SUB32rr_ND:%[0-9]+]]:gr32 = SUB32rr_ND $edi, $edi, implicit-def dead $eflags
- ; NDD-NEXT: JCC_1 %bb.2, 4, implicit $eflags
- ; NDD-NEXT: {{ $}}
- ; NDD-NEXT: bb.1:
- ; NDD-NEXT: successors: %bb.3(0x80000000)
- ; NDD-NEXT: {{ $}}
- ; NDD-NEXT: $eax = IMUL32rr_ND $eax, $edi, implicit-def dead $eflags
- ; NDD-NEXT: JMP_1 %bb.3
- ; NDD-NEXT: {{ $}}
- ; NDD-NEXT: bb.2:
- ; NDD-NEXT: successors: %bb.3(0x80000000)
- ; NDD-NEXT: {{ $}}
- ; NDD-NEXT: $eax = SBB32rr $eax, $esi, implicit-def dead $eflags, implicit $eflags
- ; NDD-NEXT: JMP_1 %bb.3
- ; NDD-NEXT: {{ $}}
- ; NDD-NEXT: bb.3:
- ; NDD-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
- ; NDD-NEXT: $eax = CMOV32rr_ND $edi, [[SUB32rr_ND]], 5, implicit killed $eflags
- ; NDD-NEXT: RET 0, $al
- ;
- ; NDD-NF-LABEL: name: test_inevitable_clobber_crossbb_complex
- ; NDD-NF: bb.0:
- ; NDD-NF-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; NDD-NF-NEXT: liveins: $edi
- ; NDD-NF-NEXT: {{ $}}
- ; NDD-NF-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; NDD-NF-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
- ; NDD-NF-NEXT: [[SUB32rr_ND:%[0-9]+]]:gr32 = SUB32rr_ND $edi, $edi, implicit-def dead $eflags
- ; NDD-NF-NEXT: JCC_1 %bb.2, 4, implicit $eflags
- ; NDD-NF-NEXT: {{ $}}
- ; NDD-NF-NEXT: bb.1:
- ; NDD-NF-NEXT: successors: %bb.3(0x80000000)
- ; NDD-NF-NEXT: {{ $}}
- ; NDD-NF-NEXT: $eax = IMUL32rr_ND $eax, $edi, implicit-def dead $eflags
- ; NDD-NF-NEXT: JMP_1 %bb.3
- ; NDD-NF-NEXT: {{ $}}
- ; NDD-NF-NEXT: bb.2:
- ; NDD-NF-NEXT: successors: %bb.3(0x80000000)
- ; NDD-NF-NEXT: {{ $}}
- ; NDD-NF-NEXT: $eax = SBB32rr $eax, $esi, implicit-def dead $eflags, implicit $eflags
- ; NDD-NF-NEXT: JMP_1 %bb.3
- ; NDD-NF-NEXT: {{ $}}
- ; NDD-NF-NEXT: bb.3:
- ; NDD-NF-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
- ; NDD-NF-NEXT: $eax = CMOV32rr_ND $edi, [[SUB32rr_ND]], 5, implicit killed $eflags
- ; NDD-NF-NEXT: RET 0, $al
+ ; CHECK-LABEL: name: test_inevitable_clobber_crossbb_complex
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: liveins: $edi
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
+ ; CHECK-NEXT: [[SUB32rr_ND:%[0-9]+]]:gr32 = SUB32rr_ND $edi, $edi, implicit-def dead $eflags
+ ; CHECK-NEXT: JCC_1 %bb.2, 4, implicit $eflags
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $eax = IMUL32rr_ND $eax, $edi, implicit-def dead $eflags
+ ; CHECK-NEXT: JMP_1 %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $eax = SBB32rr $eax, $esi, implicit-def dead $eflags, implicit $eflags
+ ; CHECK-NEXT: JMP_1 %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3:
+ ; CHECK-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
+ ; CHECK-NEXT: $eax = CMOV32rr_ND $edi, [[SUB32rr_ND]], 5, implicit killed $eflags
+ ; CHECK-NEXT: RET 0, $al
;
- ; NDD-NF-ZU-LABEL: name: test_inevitable_clobber_crossbb_complex
- ; NDD-NF-ZU: bb.0:
- ; NDD-NF-ZU-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; NDD-NF-ZU-NEXT: liveins: $edi
- ; NDD-NF-ZU-NEXT: {{ $}}
- ; NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
- ; NDD-NF-ZU-NEXT: [[SUB32rr_ND:%[0-9]+]]:gr32 = SUB32rr_ND $edi, $edi, implicit-def dead $eflags
- ; NDD-NF-ZU-NEXT: JCC_1 %bb.2, 4, implicit $eflags
- ; NDD-NF-ZU-NEXT: {{ $}}
- ; NDD-NF-ZU-NEXT: bb.1:
- ; NDD-NF-ZU-NEXT: successors: %bb.3(0x80000000)
- ; NDD-NF-ZU-NEXT: {{ $}}
- ; NDD-NF-ZU-NEXT: $eax = IMUL32rr_ND $eax, $edi, implicit-def dead $eflags
- ; NDD-NF-ZU-NEXT: JMP_1 %bb.3
- ; NDD-NF-ZU-NEXT: {{ $}}
- ; NDD-NF-ZU-NEXT: bb.2:
- ; NDD-NF-ZU-NEXT: successors: %bb.3(0x80000000)
- ; NDD-NF-ZU-NEXT: {{ $}}
- ; NDD-NF-ZU-NEXT: $eax = SBB32rr $eax, $esi, implicit-def dead $eflags, implicit $eflags
- ; NDD-NF-ZU-NEXT: JMP_1 %bb.3
- ; NDD-NF-ZU-NEXT: {{ $}}
- ; NDD-NF-ZU-NEXT: bb.3:
- ; NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[SUB32rr_ND]], 5, implicit killed $eflags
- ; NDD-NF-ZU-NEXT: RET 0, $al
+ ; NDD-ZU-LABEL: name: test_inevitable_clobber_crossbb_complex
+ ; NDD-ZU: bb.0:
+ ; NDD-ZU-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; NDD-ZU-NEXT: liveins: $edi
+ ; NDD-ZU-NEXT: {{ $}}
+ ; NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; NDD-ZU-NEXT: [[SUB32rr_ND:%[0-9]+]]:gr32 = SUB32rr_ND $edi, $edi, implicit-def dead $eflags
+ ; NDD-ZU-NEXT: JCC_1 %bb.2, 4, implicit $eflags
+ ; NDD-ZU-NEXT: {{ $}}
+ ; NDD-ZU-NEXT: bb.1:
+ ; NDD-ZU-NEXT: successors: %bb.3(0x80000000)
+ ; NDD-ZU-NEXT: {{ $}}
+ ; NDD-ZU-NEXT: $eax = IMUL32rr_ND $eax, $edi, implicit-def dead $eflags
+ ; NDD-ZU-NEXT: JMP_1 %bb.3
+ ; NDD-ZU-NEXT: {{ $}}
+ ; NDD-ZU-NEXT: bb.2:
+ ; NDD-ZU-NEXT: successors: %bb.3(0x80000000)
+ ; NDD-ZU-NEXT: {{ $}}
+ ; NDD-ZU-NEXT: $eax = SBB32rr $eax, $esi, implicit-def dead $eflags, implicit $eflags
+ ; NDD-ZU-NEXT: JMP_1 %bb.3
+ ; NDD-ZU-NEXT: {{ $}}
+ ; NDD-ZU-NEXT: bb.3:
+ ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[SUB32rr_ND]], 5, implicit killed $eflags
+ ; NDD-ZU-NEXT: RET 0, $al
;
- ; O0-NDD-NF-ZU-LABEL: name: test_inevitable_clobber_crossbb_complex
- ; O0-NDD-NF-ZU: bb.0:
- ; O0-NDD-NF-ZU-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; O0-NDD-NF-ZU-NEXT: liveins: $edi
- ; O0-NDD-NF-ZU-NEXT: {{ $}}
- ; O0-NDD-NF-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; O0-NDD-NF-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: [[SUB32rr_ND:%[0-9]+]]:gr32 = SUB32rr_ND $edi, $edi, implicit-def dead $eflags
- ; O0-NDD-NF-ZU-NEXT: JCC_1 %bb.2, 4, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: {{ $}}
- ; O0-NDD-NF-ZU-NEXT: bb.1:
- ; O0-NDD-NF-ZU-NEXT: successors: %bb.3(0x80000000)
- ; O0-NDD-NF-ZU-NEXT: {{ $}}
- ; O0-NDD-NF-ZU-NEXT: $eax = IMUL32rr_ND $eax, $edi, implicit-def dead $eflags
- ; O0-NDD-NF-ZU-NEXT: JMP_1 %bb.3
- ; O0-NDD-NF-ZU-NEXT: {{ $}}
- ; O0-NDD-NF-ZU-NEXT: bb.2:
- ; O0-NDD-NF-ZU-NEXT: successors: %bb.3(0x80000000)
- ; O0-NDD-NF-ZU-NEXT: {{ $}}
- ; O0-NDD-NF-ZU-NEXT: $eax = SBB32rr $eax, $esi, implicit-def dead $eflags, implicit $eflags
- ; O0-NDD-NF-ZU-NEXT: JMP_1 %bb.3
- ; O0-NDD-NF-ZU-NEXT: {{ $}}
- ; O0-NDD-NF-ZU-NEXT: bb.3:
- ; O0-NDD-NF-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; O0-NDD-NF-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[SUB32rr_ND]], 5, implicit killed $eflags
- ; O0-NDD-NF-ZU-NEXT: RET 0, $al
+ ; O0-NDD-ZU-LABEL: name: test_inevitable_clobber_crossbb_complex
+ ; O0-NDD-ZU: bb.0:
+ ; O0-NDD-ZU-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; O0-NDD-ZU-NEXT: liveins: $edi
+ ; O0-NDD-ZU-NEXT: {{ $}}
+ ; O0-NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; O0-NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; O0-NDD-ZU-NEXT: [[SUB32rr_ND:%[0-9]+]]:gr32 = SUB32rr_ND $edi, $edi, implicit-def dead $eflags
+ ; O0-NDD-ZU-NEXT: JCC_1 %bb.2, 4, implicit $eflags
+ ; O0-NDD-ZU-NEXT: {{ $}}
+ ; O0-NDD-ZU-NEXT: bb.1:
+ ; O0-NDD-ZU-NEXT: successors: %bb.3(0x80000000)
+ ; O0-NDD-ZU-NEXT: {{ $}}
+ ; O0-NDD-ZU-NEXT: $eax = IMUL32rr_ND $eax, $edi, implicit-def dead $eflags
+ ; O0-NDD-ZU-NEXT: JMP_1 %bb.3
+ ; O0-NDD-ZU-NEXT: {{ $}}
+ ; O0-NDD-ZU-NEXT: bb.2:
+ ; O0-NDD-ZU-NEXT: successors: %bb.3(0x80000000)
+ ; O0-NDD-ZU-NEXT: {{ $}}
+ ; O0-NDD-ZU-NEXT: $eax = SBB32rr $eax, $esi, implicit-def dead $eflags, implicit $eflags
+ ; O0-NDD-ZU-NEXT: JMP_1 %bb.3
+ ; O0-NDD-ZU-NEXT: {{ $}}
+ ; O0-NDD-ZU-NEXT: bb.3:
+ ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; O0-NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[SUB32rr_ND]], 5, implicit killed $eflags
+ ; O0-NDD-ZU-NEXT: RET 0, $al
+
bb.0:
liveins: $edi
diff --git a/llvm/test/CodeGen/X86/cmp.ll b/llvm/test/CodeGen/X86/cmp.ll
index 64dd19ca42c50..4c0292ccc70ac 100644
--- a/llvm/test/CodeGen/X86/cmp.ll
+++ b/llvm/test/CodeGen/X86/cmp.ll
@@ -2,7 +2,7 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,NO-NDD
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ndd -show-mc-encoding | FileCheck --check-prefixes=CHECK,NDD %s
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ndd,+zu -show-mc-encoding | FileCheck --check-prefixes=CHECK,NDD-ZU %s
-; RUN: llc -O0 < %s -mtriple=x86_64-unknown-unknown -mattr=+ndd,+zu -show-mc-encoding | FileCheck --check-prefixes=CHECK,O0-NDD-ZU %s
+; RUN: llc -O0 < %s -mtriple=x86_64-unknown-unknown -mattr=+ndd,+zu -show-mc-encoding | FileCheck --check-prefix=O0-NDD-ZU %s
@d = dso_local global i8 0, align 1
@d64 = dso_local global i64 0
@@ -19,6 +19,18 @@ define i32 @test1(i32 %X, ptr %y) nounwind {
; CHECK-NEXT: .LBB0_2: # %ReturnBlock
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; CHECK-NEXT: retq # encoding: [0xc3]
+;
+; O0-NDD-ZU-LABEL: test1:
+; O0-NDD-ZU: # %bb.0: # %entry
+; O0-NDD-ZU-NEXT: cmpl $0, (%rsi) # encoding: [0x83,0x3e,0x00]
+; O0-NDD-ZU-NEXT: je .LBB0_2 # encoding: [0x74,A]
+; O0-NDD-ZU-NEXT: # fixup A - offset: 1, value: .LBB0_2-1, kind: FK_PCRel_1
+; O0-NDD-ZU-NEXT: # %bb.1: # %cond_true
+; O0-NDD-ZU-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; O0-NDD-ZU-NEXT: .LBB0_2: # %ReturnBlock
+; O0-NDD-ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
entry:
%tmp = load i32, ptr %y
%tmp.upgrd.1 = icmp eq i32 %tmp, 0
@@ -32,44 +44,18 @@ ReturnBlock:
}
define i32 @test2(i32 %X, ptr %y) nounwind {
-; NO-NDD-LABEL: test2:
-; NO-NDD: # %bb.0: # %entry
-; NO-NDD-NEXT: testl $536870911, (%rsi) # encoding: [0xf7,0x06,0xff,0xff,0xff,0x1f]
-; NO-NDD-NEXT: # imm = 0x1FFFFFFF
-; NO-NDD-NEXT: je .LBB1_2 # encoding: [0x74,A]
-; NO-NDD-NEXT: # fixup A - offset: 1, value: .LBB1_2-1, kind: FK_PCRel_1
-; NO-NDD-NEXT: # %bb.1: # %cond_true
-; NO-NDD-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
-; NO-NDD-NEXT: retq # encoding: [0xc3]
-; NO-NDD-NEXT: .LBB1_2: # %ReturnBlock
-; NO-NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; NO-NDD-NEXT: retq # encoding: [0xc3]
-;
-; NDD-LABEL: test2:
-; NDD: # %bb.0: # %entry
-; NDD-NEXT: testl $536870911, (%rsi) # encoding: [0xf7,0x06,0xff,0xff,0xff,0x1f]
-; NDD-NEXT: # imm = 0x1FFFFFFF
-; NDD-NEXT: je .LBB1_2 # encoding: [0x74,A]
-; NDD-NEXT: # fixup A - offset: 1, value: .LBB1_2-1, kind: FK_PCRel_1
-; NDD-NEXT: # %bb.1: # %cond_true
-; NDD-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
-; NDD-NEXT: retq # encoding: [0xc3]
-; NDD-NEXT: .LBB1_2: # %ReturnBlock
-; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; NDD-NEXT: retq # encoding: [0xc3]
-;
-; NDD-ZU-LABEL: test2:
-; NDD-ZU: # %bb.0: # %entry
-; NDD-ZU-NEXT: testl $536870911, (%rsi) # encoding: [0xf7,0x06,0xff,0xff,0xff,0x1f]
-; NDD-ZU-NEXT: # imm = 0x1FFFFFFF
-; NDD-ZU-NEXT: je .LBB1_2 # encoding: [0x74,A]
-; NDD-ZU-NEXT: # fixup A - offset: 1, value: .LBB1_2-1, kind: FK_PCRel_1
-; NDD-ZU-NEXT: # %bb.1: # %cond_true
-; NDD-ZU-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-; NDD-ZU-NEXT: .LBB1_2: # %ReturnBlock
-; NDD-ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
+; CHECK-LABEL: test2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: testl $536870911, (%rsi) # encoding: [0xf7,0x06,0xff,0xff,0xff,0x1f]
+; CHECK-NEXT: # imm = 0x1FFFFFFF
+; CHECK-NEXT: je .LBB1_2 # encoding: [0x74,A]
+; CHECK-NEXT: # fixup A - offset: 1, value: .LBB1_2-1, kind: FK_PCRel_1
+; CHECK-NEXT: # %bb.1: # %cond_true
+; CHECK-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
+; CHECK-NEXT: retq # encoding: [0xc3]
+; CHECK-NEXT: .LBB1_2: # %ReturnBlock
+; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; CHECK-NEXT: retq # encoding: [0xc3]
;
; O0-NDD-ZU-LABEL: test2:
; O0-NDD-ZU: # %bb.0: # %entry
@@ -97,41 +83,17 @@ ReturnBlock:
}
define i8 @test2b(i8 %X, ptr %y) nounwind {
-; NO-NDD-LABEL: test2b:
-; NO-NDD: # %bb.0: # %entry
-; NO-NDD-NEXT: testb $31, (%rsi) # encoding: [0xf6,0x06,0x1f]
-; NO-NDD-NEXT: je .LBB2_2 # encoding: [0x74,A]
-; NO-NDD-NEXT: # fixup A - offset: 1, value: .LBB2_2-1, kind: FK_PCRel_1
-; NO-NDD-NEXT: # %bb.1: # %cond_true
-; NO-NDD-NEXT: movb $1, %al # encoding: [0xb0,0x01]
-; NO-NDD-NEXT: retq # encoding: [0xc3]
-; NO-NDD-NEXT: .LBB2_2: # %ReturnBlock
-; NO-NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; NO-NDD-NEXT: retq # encoding: [0xc3]
-;
-; NDD-LABEL: test2b:
-; NDD: # %bb.0: # %entry
-; NDD-NEXT: testb $31, (%rsi) # encoding: [0xf6,0x06,0x1f]
-; NDD-NEXT: je .LBB2_2 # encoding: [0x74,A]
-; NDD-NEXT: # fixup A - offset: 1, value: .LBB2_2-1, kind: FK_PCRel_1
-; NDD-NEXT: # %bb.1: # %cond_true
-; NDD-NEXT: movb $1, %al # encoding: [0xb0,0x01]
-; NDD-NEXT: retq # encoding: [0xc3]
-; NDD-NEXT: .LBB2_2: # %ReturnBlock
-; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; NDD-NEXT: retq # encoding: [0xc3]
-;
-; NDD-ZU-LABEL: test2b:
-; NDD-ZU: # %bb.0: # %entry
-; NDD-ZU-NEXT: testb $31, (%rsi) # encoding: [0xf6,0x06,0x1f]
-; NDD-ZU-NEXT: je .LBB2_2 # encoding: [0x74,A]
-; NDD-ZU-NEXT: # fixup A - offset: 1, value: .LBB2_2-1, kind: FK_PCRel_1
-; NDD-ZU-NEXT: # %bb.1: # %cond_true
-; NDD-ZU-NEXT: movb $1, %al # encoding: [0xb0,0x01]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-; NDD-ZU-NEXT: .LBB2_2: # %ReturnBlock
-; NDD-ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
+; CHECK-LABEL: test2b:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: testb $31, (%rsi) # encoding: [0xf6,0x06,0x1f]
+; CHECK-NEXT: je .LBB2_2 # encoding: [0x74,A]
+; CHECK-NEXT: # fixup A - offset: 1, value: .LBB2_2-1, kind: FK_PCRel_1
+; CHECK-NEXT: # %bb.1: # %cond_true
+; CHECK-NEXT: movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT: retq # encoding: [0xc3]
+; CHECK-NEXT: .LBB2_2: # %ReturnBlock
+; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; CHECK-NEXT: retq # encoding: [0xc3]
;
; O0-NDD-ZU-LABEL: test2b:
; O0-NDD-ZU: # %bb.0: # %entry
@@ -229,65 +191,25 @@ define i64 @test4(i64 %x) nounwind {
}
define i32 @test5(double %A) nounwind {
-; NO-NDD-LABEL: test5:
-; NO-NDD: # %bb.0: # %entry
-; NO-NDD-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # encoding: [0x66,0x0f,0x2e,0x05,A,A,A,A]
-; NO-NDD-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; NO-NDD-NEXT: ja .LBB5_3 # encoding: [0x77,A]
-; NO-NDD-NEXT: # fixup A - offset: 1, value: .LBB5_3-1, kind: FK_PCRel_1
-; NO-NDD-NEXT: # %bb.1: # %entry
-; NO-NDD-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # encoding: [0x66,0x0f,0x2e,0x05,A,A,A,A]
-; NO-NDD-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; NO-NDD-NEXT: jb .LBB5_3 # encoding: [0x72,A]
-; NO-NDD-NEXT: # fixup A - offset: 1, value: .LBB5_3-1, kind: FK_PCRel_1
-; NO-NDD-NEXT: # %bb.2: # %bb12
-; NO-NDD-NEXT: movl $32, %eax # encoding: [0xb8,0x20,0x00,0x00,0x00]
-; NO-NDD-NEXT: retq # encoding: [0xc3]
-; NO-NDD-NEXT: .LBB5_3: # %bb8
-; NO-NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; NO-NDD-NEXT: jmp foo at PLT # TAILCALL
-; NO-NDD-NEXT: # encoding: [0xeb,A]
-; NO-NDD-NEXT: # fixup A - offset: 1, value: foo at PLT-1, kind: FK_PCRel_1
-;
-; NDD-LABEL: test5:
-; NDD: # %bb.0: # %entry
-; NDD-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # encoding: [0x66,0x0f,0x2e,0x05,A,A,A,A]
-; NDD-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; NDD-NEXT: ja .LBB5_3 # encoding: [0x77,A]
-; NDD-NEXT: # fixup A - offset: 1, value: .LBB5_3-1, kind: FK_PCRel_1
-; NDD-NEXT: # %bb.1: # %entry
-; NDD-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # encoding: [0x66,0x0f,0x2e,0x05,A,A,A,A]
-; NDD-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; NDD-NEXT: jb .LBB5_3 # encoding: [0x72,A]
-; NDD-NEXT: # fixup A - offset: 1, value: .LBB5_3-1, kind: FK_PCRel_1
-; NDD-NEXT: # %bb.2: # %bb12
-; NDD-NEXT: movl $32, %eax # encoding: [0xb8,0x20,0x00,0x00,0x00]
-; NDD-NEXT: retq # encoding: [0xc3]
-; NDD-NEXT: .LBB5_3: # %bb8
-; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; NDD-NEXT: jmp foo at PLT # TAILCALL
-; NDD-NEXT: # encoding: [0xeb,A]
-; NDD-NEXT: # fixup A - offset: 1, value: foo at PLT-1, kind: FK_PCRel_1
-;
-; NDD-ZU-LABEL: test5:
-; NDD-ZU: # %bb.0: # %entry
-; NDD-ZU-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # encoding: [0x66,0x0f,0x2e,0x05,A,A,A,A]
-; NDD-ZU-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; NDD-ZU-NEXT: ja .LBB5_3 # encoding: [0x77,A]
-; NDD-ZU-NEXT: # fixup A - offset: 1, value: .LBB5_3-1, kind: FK_PCRel_1
-; NDD-ZU-NEXT: # %bb.1: # %entry
-; NDD-ZU-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # encoding: [0x66,0x0f,0x2e,0x05,A,A,A,A]
-; NDD-ZU-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; NDD-ZU-NEXT: jb .LBB5_3 # encoding: [0x72,A]
-; NDD-ZU-NEXT: # fixup A - offset: 1, value: .LBB5_3-1, kind: FK_PCRel_1
-; NDD-ZU-NEXT: # %bb.2: # %bb12
-; NDD-ZU-NEXT: movl $32, %eax # encoding: [0xb8,0x20,0x00,0x00,0x00]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-; NDD-ZU-NEXT: .LBB5_3: # %bb8
-; NDD-ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; NDD-ZU-NEXT: jmp foo at PLT # TAILCALL
-; NDD-ZU-NEXT: # encoding: [0xeb,A]
-; NDD-ZU-NEXT: # fixup A - offset: 1, value: foo at PLT-1, kind: FK_PCRel_1
+; CHECK-LABEL: test5:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # encoding: [0x66,0x0f,0x2e,0x05,A,A,A,A]
+; CHECK-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; CHECK-NEXT: ja .LBB5_3 # encoding: [0x77,A]
+; CHECK-NEXT: # fixup A - offset: 1, value: .LBB5_3-1, kind: FK_PCRel_1
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # encoding: [0x66,0x0f,0x2e,0x05,A,A,A,A]
+; CHECK-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; CHECK-NEXT: jb .LBB5_3 # encoding: [0x72,A]
+; CHECK-NEXT: # fixup A - offset: 1, value: .LBB5_3-1, kind: FK_PCRel_1
+; CHECK-NEXT: # %bb.2: # %bb12
+; CHECK-NEXT: movl $32, %eax # encoding: [0xb8,0x20,0x00,0x00,0x00]
+; CHECK-NEXT: retq # encoding: [0xc3]
+; CHECK-NEXT: .LBB5_3: # %bb8
+; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; CHECK-NEXT: jmp foo at PLT # TAILCALL
+; CHECK-NEXT: # encoding: [0xeb,A]
+; CHECK-NEXT: # fixup A - offset: 1, value: foo at PLT-1, kind: FK_PCRel_1
;
; O0-NDD-ZU-LABEL: test5:
; O0-NDD-ZU: # %bb.0: # %entry
@@ -333,41 +255,17 @@ bb12:
declare i32 @foo(...)
define i32 @test6() nounwind align 2 {
-; NO-NDD-LABEL: test6:
-; NO-NDD: # %bb.0: # %entry
-; NO-NDD-NEXT: cmpq $0, -{{[0-9]+}}(%rsp) # encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00]
-; NO-NDD-NEXT: je .LBB6_1 # encoding: [0x74,A]
-; NO-NDD-NEXT: # fixup A - offset: 1, value: .LBB6_1-1, kind: FK_PCRel_1
-; NO-NDD-NEXT: # %bb.2: # %F
-; NO-NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; NO-NDD-NEXT: retq # encoding: [0xc3]
-; NO-NDD-NEXT: .LBB6_1: # %T
-; NO-NDD-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
-; NO-NDD-NEXT: retq # encoding: [0xc3]
-;
-; NDD-LABEL: test6:
-; NDD: # %bb.0: # %entry
-; NDD-NEXT: cmpq $0, -{{[0-9]+}}(%rsp) # encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00]
-; NDD-NEXT: je .LBB6_1 # encoding: [0x74,A]
-; NDD-NEXT: # fixup A - offset: 1, value: .LBB6_1-1, kind: FK_PCRel_1
-; NDD-NEXT: # %bb.2: # %F
-; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; NDD-NEXT: retq # encoding: [0xc3]
-; NDD-NEXT: .LBB6_1: # %T
-; NDD-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
-; NDD-NEXT: retq # encoding: [0xc3]
-;
-; NDD-ZU-LABEL: test6:
-; NDD-ZU: # %bb.0: # %entry
-; NDD-ZU-NEXT: cmpq $0, -{{[0-9]+}}(%rsp) # encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00]
-; NDD-ZU-NEXT: je .LBB6_1 # encoding: [0x74,A]
-; NDD-ZU-NEXT: # fixup A - offset: 1, value: .LBB6_1-1, kind: FK_PCRel_1
-; NDD-ZU-NEXT: # %bb.2: # %F
-; NDD-ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-; NDD-ZU-NEXT: .LBB6_1: # %T
-; NDD-ZU-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
+; CHECK-LABEL: test6:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpq $0, -{{[0-9]+}}(%rsp) # encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00]
+; CHECK-NEXT: je .LBB6_1 # encoding: [0x74,A]
+; CHECK-NEXT: # fixup A - offset: 1, value: .LBB6_1-1, kind: FK_PCRel_1
+; CHECK-NEXT: # %bb.2: # %F
+; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; CHECK-NEXT: retq # encoding: [0xc3]
+; CHECK-NEXT: .LBB6_1: # %T
+; CHECK-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
+; CHECK-NEXT: retq # encoding: [0xc3]
;
; O0-NDD-ZU-LABEL: test6:
; O0-NDD-ZU: # %bb.0: # %entry
@@ -581,68 +479,26 @@ define i32 @test11(i64 %l) nounwind {
}
define i32 @test12() ssp uwtable {
-; NO-NDD-LABEL: test12:
-; NO-NDD: # %bb.0: # %entry
-; NO-NDD-NEXT: pushq %rax # encoding: [0x50]
-; NO-NDD-NEXT: .cfi_def_cfa_offset 16
-; NO-NDD-NEXT: callq test12b at PLT # encoding: [0xe8,A,A,A,A]
-; NO-NDD-NEXT: # fixup A - offset: 1, value: test12b at PLT-4, kind: FK_PCRel_4
-; NO-NDD-NEXT: testb %al, %al # encoding: [0x84,0xc0]
-; NO-NDD-NEXT: je .LBB12_2 # encoding: [0x74,A]
-; NO-NDD-NEXT: # fixup A - offset: 1, value: .LBB12_2-1, kind: FK_PCRel_1
-; NO-NDD-NEXT: # %bb.1: # %T
-; NO-NDD-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
-; NO-NDD-NEXT: popq %rcx # encoding: [0x59]
-; NO-NDD-NEXT: .cfi_def_cfa_offset 8
-; NO-NDD-NEXT: retq # encoding: [0xc3]
-; NO-NDD-NEXT: .LBB12_2: # %F
-; NO-NDD-NEXT: .cfi_def_cfa_offset 16
-; NO-NDD-NEXT: movl $2, %eax # encoding: [0xb8,0x02,0x00,0x00,0x00]
-; NO-NDD-NEXT: popq %rcx # encoding: [0x59]
-; NO-NDD-NEXT: .cfi_def_cfa_offset 8
-; NO-NDD-NEXT: retq # encoding: [0xc3]
-;
-; NDD-LABEL: test12:
-; NDD: # %bb.0: # %entry
-; NDD-NEXT: pushq %rax # encoding: [0x50]
-; NDD-NEXT: .cfi_def_cfa_offset 16
-; NDD-NEXT: callq test12b at PLT # encoding: [0xe8,A,A,A,A]
-; NDD-NEXT: # fixup A - offset: 1, value: test12b at PLT-4, kind: FK_PCRel_4
-; NDD-NEXT: testb %al, %al # encoding: [0x84,0xc0]
-; NDD-NEXT: je .LBB12_2 # encoding: [0x74,A]
-; NDD-NEXT: # fixup A - offset: 1, value: .LBB12_2-1, kind: FK_PCRel_1
-; NDD-NEXT: # %bb.1: # %T
-; NDD-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
-; NDD-NEXT: popq %rcx # encoding: [0x59]
-; NDD-NEXT: .cfi_def_cfa_offset 8
-; NDD-NEXT: retq # encoding: [0xc3]
-; NDD-NEXT: .LBB12_2: # %F
-; NDD-NEXT: .cfi_def_cfa_offset 16
-; NDD-NEXT: movl $2, %eax # encoding: [0xb8,0x02,0x00,0x00,0x00]
-; NDD-NEXT: popq %rcx # encoding: [0x59]
-; NDD-NEXT: .cfi_def_cfa_offset 8
-; NDD-NEXT: retq # encoding: [0xc3]
-;
-; NDD-ZU-LABEL: test12:
-; NDD-ZU: # %bb.0: # %entry
-; NDD-ZU-NEXT: pushq %rax # encoding: [0x50]
-; NDD-ZU-NEXT: .cfi_def_cfa_offset 16
-; NDD-ZU-NEXT: callq test12b at PLT # encoding: [0xe8,A,A,A,A]
-; NDD-ZU-NEXT: # fixup A - offset: 1, value: test12b at PLT-4, kind: FK_PCRel_4
-; NDD-ZU-NEXT: testb %al, %al # encoding: [0x84,0xc0]
-; NDD-ZU-NEXT: je .LBB12_2 # encoding: [0x74,A]
-; NDD-ZU-NEXT: # fixup A - offset: 1, value: .LBB12_2-1, kind: FK_PCRel_1
-; NDD-ZU-NEXT: # %bb.1: # %T
-; NDD-ZU-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
-; NDD-ZU-NEXT: popq %rcx # encoding: [0x59]
-; NDD-ZU-NEXT: .cfi_def_cfa_offset 8
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-; NDD-ZU-NEXT: .LBB12_2: # %F
-; NDD-ZU-NEXT: .cfi_def_cfa_offset 16
-; NDD-ZU-NEXT: movl $2, %eax # encoding: [0xb8,0x02,0x00,0x00,0x00]
-; NDD-ZU-NEXT: popq %rcx # encoding: [0x59]
-; NDD-ZU-NEXT: .cfi_def_cfa_offset 8
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
+; CHECK-LABEL: test12:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: pushq %rax # encoding: [0x50]
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: callq test12b at PLT # encoding: [0xe8,A,A,A,A]
+; CHECK-NEXT: # fixup A - offset: 1, value: test12b at PLT-4, kind: FK_PCRel_4
+; CHECK-NEXT: testb %al, %al # encoding: [0x84,0xc0]
+; CHECK-NEXT: je .LBB12_2 # encoding: [0x74,A]
+; CHECK-NEXT: # fixup A - offset: 1, value: .LBB12_2-1, kind: FK_PCRel_1
+; CHECK-NEXT: # %bb.1: # %T
+; CHECK-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
+; CHECK-NEXT: popq %rcx # encoding: [0x59]
+; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: retq # encoding: [0xc3]
+; CHECK-NEXT: .LBB12_2: # %F
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: movl $2, %eax # encoding: [0xb8,0x02,0x00,0x00,0x00]
+; CHECK-NEXT: popq %rcx # encoding: [0x59]
+; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: retq # encoding: [0xc3]
;
; O0-NDD-ZU-LABEL: test12:
; O0-NDD-ZU: # %bb.0: # %entry
@@ -998,20 +854,10 @@ define void @test20(i32 %bf.load, i8 %x1, ptr %b_addr) {
}
define i32 @highmask_i64_simplify(i64 %val) {
-; NO-NDD-LABEL: highmask_i64_simplify:
-; NO-NDD: # %bb.0:
-; NO-NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; NO-NDD-NEXT: retq # encoding: [0xc3]
-;
-; NDD-LABEL: highmask_i64_simplify:
-; NDD: # %bb.0:
-; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; NDD-NEXT: retq # encoding: [0xc3]
-;
-; NDD-ZU-LABEL: highmask_i64_simplify:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
+; CHECK-LABEL: highmask_i64_simplify:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; CHECK-NEXT: retq # encoding: [0xc3]
;
; O0-NDD-ZU-LABEL: highmask_i64_simplify:
; O0-NDD-ZU: # %bb.0:
@@ -1936,41 +1782,17 @@ define { i64, i64 } @pr39968(i64, i64, i32) {
; Make sure we use a 32-bit comparison without an extend based on the input
; being pre-sign extended by caller.
define i32 @pr42189(i16 signext %c) {
-; NO-NDD-LABEL: pr42189:
-; NO-NDD: # %bb.0: # %entry
-; NO-NDD-NEXT: cmpl $32767, %edi # encoding: [0x81,0xff,0xff,0x7f,0x00,0x00]
-; NO-NDD-NEXT: # imm = 0x7FFF
-; NO-NDD-NEXT: jne f at PLT # TAILCALL
-; NO-NDD-NEXT: # encoding: [0x75,A]
-; NO-NDD-NEXT: # fixup A - offset: 1, value: f at PLT-1, kind: FK_PCRel_1
-; NO-NDD-NEXT: # %bb.1: # %if.then
-; NO-NDD-NEXT: jmp g at PLT # TAILCALL
-; NO-NDD-NEXT: # encoding: [0xeb,A]
-; NO-NDD-NEXT: # fixup A - offset: 1, value: g at PLT-1, kind: FK_PCRel_1
-;
-; NDD-LABEL: pr42189:
-; NDD: # %bb.0: # %entry
-; NDD-NEXT: cmpl $32767, %edi # encoding: [0x81,0xff,0xff,0x7f,0x00,0x00]
-; NDD-NEXT: # imm = 0x7FFF
-; NDD-NEXT: jne f at PLT # TAILCALL
-; NDD-NEXT: # encoding: [0x75,A]
-; NDD-NEXT: # fixup A - offset: 1, value: f at PLT-1, kind: FK_PCRel_1
-; NDD-NEXT: # %bb.1: # %if.then
-; NDD-NEXT: jmp g at PLT # TAILCALL
-; NDD-NEXT: # encoding: [0xeb,A]
-; NDD-NEXT: # fixup A - offset: 1, value: g at PLT-1, kind: FK_PCRel_1
-;
-; NDD-ZU-LABEL: pr42189:
-; NDD-ZU: # %bb.0: # %entry
-; NDD-ZU-NEXT: cmpl $32767, %edi # encoding: [0x81,0xff,0xff,0x7f,0x00,0x00]
-; NDD-ZU-NEXT: # imm = 0x7FFF
-; NDD-ZU-NEXT: jne f at PLT # TAILCALL
-; NDD-ZU-NEXT: # encoding: [0x75,A]
-; NDD-ZU-NEXT: # fixup A - offset: 1, value: f at PLT-1, kind: FK_PCRel_1
-; NDD-ZU-NEXT: # %bb.1: # %if.then
-; NDD-ZU-NEXT: jmp g at PLT # TAILCALL
-; NDD-ZU-NEXT: # encoding: [0xeb,A]
-; NDD-ZU-NEXT: # fixup A - offset: 1, value: g at PLT-1, kind: FK_PCRel_1
+; CHECK-LABEL: pr42189:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpl $32767, %edi # encoding: [0x81,0xff,0xff,0x7f,0x00,0x00]
+; CHECK-NEXT: # imm = 0x7FFF
+; CHECK-NEXT: jne f at PLT # TAILCALL
+; CHECK-NEXT: # encoding: [0x75,A]
+; CHECK-NEXT: # fixup A - offset: 1, value: f at PLT-1, kind: FK_PCRel_1
+; CHECK-NEXT: # %bb.1: # %if.then
+; CHECK-NEXT: jmp g at PLT # TAILCALL
+; CHECK-NEXT: # encoding: [0xeb,A]
+; CHECK-NEXT: # fixup A - offset: 1, value: g at PLT-1, kind: FK_PCRel_1
;
; O0-NDD-ZU-LABEL: pr42189:
; O0-NDD-ZU: # %bb.0: # %entry
diff --git a/llvm/test/CodeGen/X86/is_fpclass.ll b/llvm/test/CodeGen/X86/is_fpclass.ll
index 174a0da9af86d..75506d37dea93 100644
--- a/llvm/test/CodeGen/X86/is_fpclass.ll
+++ b/llvm/test/CodeGen/X86/is_fpclass.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-linux | FileCheck %s -check-prefixes=X86
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefixes=X64,X64-GENERIC
-; RUN: llc < %s -mtriple=x86_64-linux -mattr=+ndd | FileCheck %s -check-prefixes=X64,X64-NDD
+; RUN: llc < %s -mtriple=x86_64-linux -mattr=+ndd | FileCheck %s -check-prefix=X64-NDD
define i1 @isnan_f(float %x) {
; X86-LABEL: isnan_f:
@@ -14,11 +14,11 @@ define i1 @isnan_f(float %x) {
; X86-NEXT: setp %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: isnan_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: ucomiss %xmm0, %xmm0
-; X64-GENERIC-NEXT: setp %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: isnan_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: ucomiss %xmm0, %xmm0
+; X64-NEXT: setp %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: isnan_f:
; X64-NDD: # %bb.0: # %entry
@@ -41,11 +41,11 @@ define i1 @isnot_nan_f(float %x) {
; X86-NEXT: setnp %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: isnot_nan_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: ucomiss %xmm0, %xmm0
-; X64-GENERIC-NEXT: setnp %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: isnot_nan_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: ucomiss %xmm0, %xmm0
+; X64-NEXT: setnp %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: isnot_nan_f:
; X64-NDD: # %bb.0: # %entry
@@ -69,16 +69,16 @@ define i1 @issignaling_f(float %x) {
; X86-NEXT: andb %cl, %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: issignaling_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-GENERIC-NEXT: setl %cl
-; X64-GENERIC-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-GENERIC-NEXT: setge %al
-; X64-GENERIC-NEXT: andb %cl, %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: issignaling_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-NEXT: setl %cl
+; X64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-NEXT: setge %al
+; X64-NEXT: andb %cl, %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: issignaling_f:
; X64-NDD: # %bb.0: # %entry
@@ -107,16 +107,16 @@ define i1 @not_issignaling_f(float %x) {
; X86-NEXT: orb %cl, %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_issignaling_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-GENERIC-NEXT: setge %cl
-; X64-GENERIC-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-GENERIC-NEXT: setl %al
-; X64-GENERIC-NEXT: orb %cl, %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_issignaling_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-NEXT: setge %cl
+; X64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-NEXT: setl %al
+; X64-NEXT: orb %cl, %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_issignaling_f:
; X64-NDD: # %bb.0: # %entry
@@ -142,13 +142,13 @@ define i1 @isquiet_f(float %x) {
; X86-NEXT: setge %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: isquiet_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-GENERIC-NEXT: setge %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: isquiet_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-NEXT: setge %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: isquiet_f:
; X64-NDD: # %bb.0: # %entry
@@ -171,13 +171,13 @@ define i1 @not_isquiet_f(float %x) {
; X86-NEXT: setl %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_isquiet_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-GENERIC-NEXT: setl %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_isquiet_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-NEXT: setl %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_isquiet_f:
; X64-NDD: # %bb.0: # %entry
@@ -200,13 +200,13 @@ define i1 @isinf_f(float %x) {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: isinf_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: sete %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: isinf_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: sete %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: isinf_f:
; X64-NDD: # %bb.0: # %entry
@@ -229,13 +229,13 @@ define i1 @not_isinf_f(float %x) {
; X86-NEXT: setne %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_isinf_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: setne %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_isinf_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: setne %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_isinf_f:
; X64-NDD: # %bb.0: # %entry
@@ -256,12 +256,12 @@ define i1 @is_plus_inf_f(float %x) {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: is_plus_inf_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: sete %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: is_plus_inf_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: sete %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: is_plus_inf_f:
; X64-NDD: # %bb.0: # %entry
@@ -281,12 +281,12 @@ define i1 @is_minus_inf_f(float %x) {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: is_minus_inf_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
-; X64-GENERIC-NEXT: sete %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: is_minus_inf_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
+; X64-NEXT: sete %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: is_minus_inf_f:
; X64-NDD: # %bb.0: # %entry
@@ -306,12 +306,12 @@ define i1 @not_is_minus_inf_f(float %x) {
; X86-NEXT: setne %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_is_minus_inf_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
-; X64-GENERIC-NEXT: setne %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_is_minus_inf_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
+; X64-NEXT: setne %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_is_minus_inf_f:
; X64-NDD: # %bb.0: # %entry
@@ -333,13 +333,13 @@ define i1 @isfinite_f(float %x) {
; X86-NEXT: setl %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: isfinite_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: setl %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: isfinite_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: setl %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: isfinite_f:
; X64-NDD: # %bb.0: # %entry
@@ -362,13 +362,13 @@ define i1 @not_isfinite_f(float %x) {
; X86-NEXT: setge %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_isfinite_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: setge %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_isfinite_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: setge %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_isfinite_f:
; X64-NDD: # %bb.0: # %entry
@@ -389,12 +389,12 @@ define i1 @is_plus_finite_f(float %x) {
; X86-NEXT: setb %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: is_plus_finite_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: setb %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: is_plus_finite_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: setb %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: is_plus_finite_f:
; X64-NDD: # %bb.0: # %entry
@@ -414,12 +414,12 @@ define i1 @not_is_plus_finite_f(float %x) {
; X86-NEXT: setae %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_is_plus_finite_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: setae %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_is_plus_finite_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: setae %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_is_plus_finite_f:
; X64-NDD: # %bb.0: # %entry
@@ -444,16 +444,16 @@ define i1 @is_minus_finite_f(float %x) {
; X86-NEXT: andb %cl, %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: is_minus_finite_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: testl %eax, %eax
-; X64-GENERIC-NEXT: sets %cl
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: setl %al
-; X64-GENERIC-NEXT: andb %cl, %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: is_minus_finite_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: testl %eax, %eax
+; X64-NEXT: sets %cl
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: setl %al
+; X64-NEXT: andb %cl, %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: is_minus_finite_f:
; X64-NDD: # %bb.0: # %entry
@@ -482,16 +482,16 @@ define i1 @not_is_minus_finite_f(float %x) {
; X86-NEXT: orb %cl, %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_is_minus_finite_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: testl %eax, %eax
-; X64-GENERIC-NEXT: setns %cl
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: setge %al
-; X64-GENERIC-NEXT: orb %cl, %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_is_minus_finite_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: testl %eax, %eax
+; X64-NEXT: setns %cl
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: setge %al
+; X64-NEXT: orb %cl, %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_is_minus_finite_f:
; X64-NDD: # %bb.0: # %entry
@@ -518,14 +518,14 @@ define i1 @isnormal_f(float %x) #1 {
; X86-NEXT: setb %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: isnormal_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: addl $-8388608, %eax # imm = 0xFF800000
-; X64-GENERIC-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; X64-GENERIC-NEXT: setb %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: isnormal_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: addl $-8388608, %eax # imm = 0xFF800000
+; X64-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
+; X64-NEXT: setb %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: isnormal_f:
; X64-NDD: # %bb.0: # %entry
@@ -550,14 +550,14 @@ define i1 @not_isnormal_f(float %x) #1 {
; X86-NEXT: setae %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_isnormal_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: addl $-8388608, %eax # imm = 0xFF800000
-; X64-GENERIC-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; X64-GENERIC-NEXT: setae %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_isnormal_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: addl $-8388608, %eax # imm = 0xFF800000
+; X64-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
+; X64-NEXT: setae %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_isnormal_f:
; X64-NDD: # %bb.0: # %entry
@@ -585,17 +585,17 @@ define i1 @is_plus_normal_f(float %x) {
; X86-NEXT: andb %cl, %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: is_plus_normal_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: testl %eax, %eax
-; X64-GENERIC-NEXT: setns %cl
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: addl $-8388608, %eax # imm = 0xFF800000
-; X64-GENERIC-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; X64-GENERIC-NEXT: setb %al
-; X64-GENERIC-NEXT: andb %cl, %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: is_plus_normal_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: testl %eax, %eax
+; X64-NEXT: setns %cl
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: addl $-8388608, %eax # imm = 0xFF800000
+; X64-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
+; X64-NEXT: setb %al
+; X64-NEXT: andb %cl, %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: is_plus_normal_f:
; X64-NDD: # %bb.0: # %entry
@@ -623,14 +623,14 @@ define i1 @issubnormal_f(float %x) {
; X86-NEXT: setb %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: issubnormal_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: decl %eax
-; X64-GENERIC-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
-; X64-GENERIC-NEXT: setb %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: issubnormal_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: decl %eax
+; X64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-NEXT: setb %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: issubnormal_f:
; X64-NDD: # %bb.0: # %entry
@@ -655,14 +655,14 @@ define i1 @issubnormal_f_daz(float %x) #0 {
; X86-NEXT: setb %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: issubnormal_f_daz:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: decl %eax
-; X64-GENERIC-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
-; X64-GENERIC-NEXT: setb %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: issubnormal_f_daz:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: decl %eax
+; X64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-NEXT: setb %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: issubnormal_f_daz:
; X64-NDD: # %bb.0: # %entry
@@ -687,14 +687,14 @@ define i1 @issubnormal_f_maybe_daz(float %x) #1 {
; X86-NEXT: setb %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: issubnormal_f_maybe_daz:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: decl %eax
-; X64-GENERIC-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
-; X64-GENERIC-NEXT: setb %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: issubnormal_f_maybe_daz:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: decl %eax
+; X64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-NEXT: setb %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: issubnormal_f_maybe_daz:
; X64-NDD: # %bb.0: # %entry
@@ -719,14 +719,14 @@ define i1 @not_issubnormal_f(float %x) {
; X86-NEXT: setae %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_issubnormal_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: decl %eax
-; X64-GENERIC-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
-; X64-GENERIC-NEXT: setae %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_issubnormal_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: decl %eax
+; X64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-NEXT: setae %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_issubnormal_f:
; X64-NDD: # %bb.0: # %entry
@@ -751,14 +751,14 @@ define i1 @not_issubnormal_f_daz(float %x) #0 {
; X86-NEXT: setae %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_issubnormal_f_daz:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: decl %eax
-; X64-GENERIC-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
-; X64-GENERIC-NEXT: setae %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_issubnormal_f_daz:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: decl %eax
+; X64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-NEXT: setae %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_issubnormal_f_daz:
; X64-NDD: # %bb.0: # %entry
@@ -783,14 +783,14 @@ define i1 @not_issubnormal_f_maybe_daz(float %x) #1 {
; X86-NEXT: setae %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_issubnormal_f_maybe_daz:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: decl %eax
-; X64-GENERIC-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
-; X64-GENERIC-NEXT: setae %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_issubnormal_f_maybe_daz:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: decl %eax
+; X64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-NEXT: setae %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_issubnormal_f_maybe_daz:
; X64-NDD: # %bb.0: # %entry
@@ -814,13 +814,13 @@ define i1 @is_plus_subnormal_f(float %x) {
; X86-NEXT: setb %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: is_plus_subnormal_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: decl %eax
-; X64-GENERIC-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
-; X64-GENERIC-NEXT: setb %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: is_plus_subnormal_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: decl %eax
+; X64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-NEXT: setb %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: is_plus_subnormal_f:
; X64-NDD: # %bb.0: # %entry
@@ -843,13 +843,13 @@ define i1 @not_is_plus_subnormal_f(float %x) {
; X86-NEXT: setae %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_is_plus_subnormal_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: decl %eax
-; X64-GENERIC-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
-; X64-GENERIC-NEXT: setae %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_is_plus_subnormal_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: decl %eax
+; X64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-NEXT: setae %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_is_plus_subnormal_f:
; X64-NDD: # %bb.0: # %entry
@@ -876,17 +876,17 @@ define i1 @is_minus_subnormal_f(float %x) {
; X86-NEXT: andb %cl, %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: is_minus_subnormal_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: testl %eax, %eax
-; X64-GENERIC-NEXT: sets %cl
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: decl %eax
-; X64-GENERIC-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
-; X64-GENERIC-NEXT: setb %al
-; X64-GENERIC-NEXT: andb %cl, %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: is_minus_subnormal_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: testl %eax, %eax
+; X64-NEXT: sets %cl
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: decl %eax
+; X64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-NEXT: setb %al
+; X64-NEXT: andb %cl, %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: is_minus_subnormal_f:
; X64-NDD: # %bb.0: # %entry
@@ -917,17 +917,17 @@ define i1 @not_is_minus_subnormal_f(float %x) {
; X86-NEXT: orb %cl, %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_is_minus_subnormal_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: testl %eax, %eax
-; X64-GENERIC-NEXT: setns %cl
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: decl %eax
-; X64-GENERIC-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
-; X64-GENERIC-NEXT: setae %al
-; X64-GENERIC-NEXT: orb %cl, %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_is_minus_subnormal_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: testl %eax, %eax
+; X64-NEXT: setns %cl
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: decl %eax
+; X64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-NEXT: setae %al
+; X64-NEXT: orb %cl, %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_is_minus_subnormal_f:
; X64-NDD: # %bb.0: # %entry
@@ -952,12 +952,12 @@ define i1 @iszero_f(float %x) {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: iszero_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: sete %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: iszero_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: sete %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: iszero_f:
; X64-NDD: # %bb.0: # %entry
@@ -977,12 +977,12 @@ define i1 @iszero_f_daz(float %x) #0 {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: iszero_f_daz:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: sete %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: iszero_f_daz:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: sete %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: iszero_f_daz:
; X64-NDD: # %bb.0: # %entry
@@ -1002,12 +1002,12 @@ define i1 @iszero_f_maybe_daz(float %x) #1 {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: iszero_f_maybe_daz:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: sete %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: iszero_f_maybe_daz:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: sete %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: iszero_f_maybe_daz:
; X64-NDD: # %bb.0: # %entry
@@ -1027,12 +1027,12 @@ define i1 @not_iszero_f(float %x) {
; X86-NEXT: setne %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_iszero_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: setne %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_iszero_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: setne %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_iszero_f:
; X64-NDD: # %bb.0: # %entry
@@ -1052,12 +1052,12 @@ define i1 @not_iszero_f_daz(float %x) #0 {
; X86-NEXT: setne %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_iszero_f_daz:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: setne %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_iszero_f_daz:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: setne %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_iszero_f_daz:
; X64-NDD: # %bb.0: # %entry
@@ -1077,12 +1077,12 @@ define i1 @not_iszero_f_maybe_daz(float %x) #1 {
; X86-NEXT: setne %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_iszero_f_maybe_daz:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: setne %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_iszero_f_maybe_daz:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: setne %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_iszero_f_maybe_daz:
; X64-NDD: # %bb.0: # %entry
@@ -1102,12 +1102,12 @@ define i1 @issubnormal_or_zero_f(float %x) {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: issubnormal_or_zero_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: testl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: sete %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: issubnormal_or_zero_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: sete %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: issubnormal_or_zero_f:
; X64-NDD: # %bb.0: # %entry
@@ -1127,12 +1127,12 @@ define i1 @issubnormal_or_zero_f_daz(float %x) #0 {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: issubnormal_or_zero_f_daz:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: testl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: sete %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: issubnormal_or_zero_f_daz:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: sete %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: issubnormal_or_zero_f_daz:
; X64-NDD: # %bb.0: # %entry
@@ -1152,12 +1152,12 @@ define i1 @issubnormal_or_zero_f_maybe_daz(float %x) #1 {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: issubnormal_or_zero_f_maybe_daz:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: testl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: sete %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: issubnormal_or_zero_f_maybe_daz:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: sete %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: issubnormal_or_zero_f_maybe_daz:
; X64-NDD: # %bb.0: # %entry
@@ -1177,12 +1177,12 @@ define i1 @not_issubnormal_or_zero_f(float %x) {
; X86-NEXT: setne %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_issubnormal_or_zero_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: testl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: setne %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_issubnormal_or_zero_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: setne %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_issubnormal_or_zero_f:
; X64-NDD: # %bb.0: # %entry
@@ -1202,12 +1202,12 @@ define i1 @not_issubnormal_or_zero_f_daz(float %x) #0 {
; X86-NEXT: setne %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_issubnormal_or_zero_f_daz:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: testl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: setne %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_issubnormal_or_zero_f_daz:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: setne %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_issubnormal_or_zero_f_daz:
; X64-NDD: # %bb.0: # %entry
@@ -1227,12 +1227,12 @@ define i1 @not_issubnormal_or_zero_f_maybe_daz(float %x) #1 {
; X86-NEXT: setne %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_issubnormal_or_zero_f_maybe_daz:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: testl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: setne %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_issubnormal_or_zero_f_maybe_daz:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: setne %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_issubnormal_or_zero_f_maybe_daz:
; X64-NDD: # %bb.0: # %entry
@@ -1252,12 +1252,12 @@ define i1 @is_plus_zero_f(float %x) {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: is_plus_zero_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: testl %eax, %eax
-; X64-GENERIC-NEXT: sete %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: is_plus_zero_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: testl %eax, %eax
+; X64-NEXT: sete %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: is_plus_zero_f:
; X64-NDD: # %bb.0: # %entry
@@ -1277,12 +1277,12 @@ define i1 @not_is_plus_zero_f(float %x) {
; X86-NEXT: setne %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_is_plus_zero_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: testl %eax, %eax
-; X64-GENERIC-NEXT: setne %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_is_plus_zero_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: testl %eax, %eax
+; X64-NEXT: setne %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_is_plus_zero_f:
; X64-NDD: # %bb.0: # %entry
@@ -1303,12 +1303,12 @@ define i1 @is_minus_zero_f(float %x) {
; X86-NEXT: seto %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: is_minus_zero_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: negl %eax
-; X64-GENERIC-NEXT: seto %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: is_minus_zero_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: negl %eax
+; X64-NEXT: seto %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: is_minus_zero_f:
; X64-NDD: # %bb.0: # %entry
@@ -1329,12 +1329,12 @@ define i1 @not_is_minus_zero_f(float %x) {
; X86-NEXT: setno %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_is_minus_zero_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: negl %eax
-; X64-GENERIC-NEXT: setno %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_is_minus_zero_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: negl %eax
+; X64-NEXT: setno %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_is_minus_zero_f:
; X64-NDD: # %bb.0: # %entry
@@ -1356,13 +1356,13 @@ define i1 @isnan_f_strictfp(float %x) strictfp {
; X86-NEXT: setge %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: isnan_f_strictfp:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-GENERIC-NEXT: setge %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: isnan_f_strictfp:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-NEXT: setge %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: isnan_f_strictfp:
; X64-NDD: # %bb.0: # %entry
@@ -1385,13 +1385,13 @@ define i1 @not_isnan_f_strictfp(float %x) strictfp {
; X86-NEXT: setl %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_isnan_f_strictfp:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-GENERIC-NEXT: setl %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_isnan_f_strictfp:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-NEXT: setl %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_isnan_f_strictfp:
; X64-NDD: # %bb.0: # %entry
@@ -1414,13 +1414,13 @@ define i1 @isfinite_f_strictfp(float %x) strictfp {
; X86-NEXT: setl %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: isfinite_f_strictfp:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: setl %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: isfinite_f_strictfp:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: setl %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: isfinite_f_strictfp:
; X64-NDD: # %bb.0: # %entry
@@ -1443,13 +1443,13 @@ define i1 @not_isfinite_f_strictfp(float %x) strictfp {
; X86-NEXT: setge %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_isfinite_f_strictfp:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: setge %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_isfinite_f_strictfp:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: setge %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_isfinite_f_strictfp:
; X64-NDD: # %bb.0: # %entry
@@ -1470,12 +1470,12 @@ define i1 @iszero_f_strictfp(float %x) strictfp {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: iszero_f_strictfp:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: sete %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: iszero_f_strictfp:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: sete %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: iszero_f_strictfp:
; X64-NDD: # %bb.0: # %entry
@@ -1495,12 +1495,12 @@ define i1 @not_iszero_f_strictfp(float %x) strictfp {
; X86-NEXT: setne %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_iszero_f_strictfp:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: setne %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_iszero_f_strictfp:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: setne %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_iszero_f_strictfp:
; X64-NDD: # %bb.0: # %entry
@@ -1524,11 +1524,11 @@ define i1 @isnan_d(double %x) {
; X86-NEXT: setp %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: isnan_d:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: ucomisd %xmm0, %xmm0
-; X64-GENERIC-NEXT: setp %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: isnan_d:
+; X64: # %bb.0: # %entry
+; X64-NEXT: ucomisd %xmm0, %xmm0
+; X64-NEXT: setp %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: isnan_d:
; X64-NDD: # %bb.0: # %entry
@@ -1550,15 +1550,15 @@ define i1 @isinf_d(double %x) {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: isinf_d:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movq %xmm0, %rax
-; X64-GENERIC-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
-; X64-GENERIC-NEXT: andq %rax, %rcx
-; X64-GENERIC-NEXT: movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000
-; X64-GENERIC-NEXT: cmpq %rax, %rcx
-; X64-GENERIC-NEXT: sete %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: isinf_d:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movq %xmm0, %rax
+; X64-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; X64-NEXT: andq %rax, %rcx
+; X64-NEXT: movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000
+; X64-NEXT: cmpq %rax, %rcx
+; X64-NEXT: sete %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: isinf_d:
; X64-NDD: # %bb.0: # %entry
@@ -1583,15 +1583,15 @@ define i1 @isfinite_d(double %x) {
; X86-NEXT: setl %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: isfinite_d:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movq %xmm0, %rax
-; X64-GENERIC-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
-; X64-GENERIC-NEXT: andq %rax, %rcx
-; X64-GENERIC-NEXT: movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000
-; X64-GENERIC-NEXT: cmpq %rax, %rcx
-; X64-GENERIC-NEXT: setl %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: isfinite_d:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movq %xmm0, %rax
+; X64-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; X64-NEXT: andq %rax, %rcx
+; X64-NEXT: movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000
+; X64-NEXT: cmpq %rax, %rcx
+; X64-NEXT: setl %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: isfinite_d:
; X64-NDD: # %bb.0: # %entry
@@ -1618,17 +1618,17 @@ define i1 @isnormal_d(double %x) {
; X86-NEXT: setb %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: isnormal_d:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movq %xmm0, %rax
-; X64-GENERIC-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
-; X64-GENERIC-NEXT: andq %rax, %rcx
-; X64-GENERIC-NEXT: movabsq $-4503599627370496, %rax # imm = 0xFFF0000000000000
-; X64-GENERIC-NEXT: addq %rcx, %rax
-; X64-GENERIC-NEXT: shrq $53, %rax
-; X64-GENERIC-NEXT: cmpl $1023, %eax # imm = 0x3FF
-; X64-GENERIC-NEXT: setb %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: isnormal_d:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movq %xmm0, %rax
+; X64-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; X64-NEXT: andq %rax, %rcx
+; X64-NEXT: movabsq $-4503599627370496, %rax # imm = 0xFFF0000000000000
+; X64-NEXT: addq %rcx, %rax
+; X64-NEXT: shrq $53, %rax
+; X64-NEXT: cmpl $1023, %eax # imm = 0x3FF
+; X64-NEXT: setb %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: isnormal_d:
; X64-NDD: # %bb.0: # %entry
@@ -1659,16 +1659,16 @@ define i1 @issubnormal_d(double %x) {
; X86-NEXT: setb %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: issubnormal_d:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movq %xmm0, %rax
-; X64-GENERIC-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
-; X64-GENERIC-NEXT: andq %rax, %rcx
-; X64-GENERIC-NEXT: decq %rcx
-; X64-GENERIC-NEXT: movabsq $4503599627370495, %rax # imm = 0xFFFFFFFFFFFFF
-; X64-GENERIC-NEXT: cmpq %rax, %rcx
-; X64-GENERIC-NEXT: setb %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: issubnormal_d:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movq %xmm0, %rax
+; X64-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; X64-NEXT: andq %rax, %rcx
+; X64-NEXT: decq %rcx
+; X64-NEXT: movabsq $4503599627370495, %rax # imm = 0xFFFFFFFFFFFFF
+; X64-NEXT: cmpq %rax, %rcx
+; X64-NEXT: setb %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: issubnormal_d:
; X64-NDD: # %bb.0: # %entry
@@ -1694,13 +1694,13 @@ define i1 @iszero_d(double %x) {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: iszero_d:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movq %xmm0, %rax
-; X64-GENERIC-NEXT: shlq %rax
-; X64-GENERIC-NEXT: testq %rax, %rax
-; X64-GENERIC-NEXT: sete %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: iszero_d:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movq %xmm0, %rax
+; X64-NEXT: shlq %rax
+; X64-NEXT: testq %rax, %rax
+; X64-NEXT: sete %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: iszero_d:
; X64-NDD: # %bb.0: # %entry
@@ -1729,19 +1729,19 @@ define i1 @issignaling_d(double %x) {
; X86-NEXT: andb %cl, %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: issignaling_d:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movq %xmm0, %rax
-; X64-GENERIC-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
-; X64-GENERIC-NEXT: andq %rax, %rcx
-; X64-GENERIC-NEXT: movabsq $9221120237041090560, %rax # imm = 0x7FF8000000000000
-; X64-GENERIC-NEXT: cmpq %rax, %rcx
-; X64-GENERIC-NEXT: setl %dl
-; X64-GENERIC-NEXT: movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000
-; X64-GENERIC-NEXT: cmpq %rax, %rcx
-; X64-GENERIC-NEXT: setg %al
-; X64-GENERIC-NEXT: andb %dl, %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: issignaling_d:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movq %xmm0, %rax
+; X64-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; X64-NEXT: andq %rax, %rcx
+; X64-NEXT: movabsq $9221120237041090560, %rax # imm = 0x7FF8000000000000
+; X64-NEXT: cmpq %rax, %rcx
+; X64-NEXT: setl %dl
+; X64-NEXT: movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000
+; X64-NEXT: cmpq %rax, %rcx
+; X64-NEXT: setg %al
+; X64-NEXT: andb %dl, %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: issignaling_d:
; X64-NDD: # %bb.0: # %entry
@@ -1770,15 +1770,15 @@ define i1 @isquiet_d(double %x) {
; X86-NEXT: setge %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: isquiet_d:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movq %xmm0, %rax
-; X64-GENERIC-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
-; X64-GENERIC-NEXT: andq %rax, %rcx
-; X64-GENERIC-NEXT: movabsq $9221120237041090559, %rax # imm = 0x7FF7FFFFFFFFFFFF
-; X64-GENERIC-NEXT: cmpq %rax, %rcx
-; X64-GENERIC-NEXT: setg %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: isquiet_d:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movq %xmm0, %rax
+; X64-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; X64-NEXT: andq %rax, %rcx
+; X64-NEXT: movabsq $9221120237041090559, %rax # imm = 0x7FF7FFFFFFFFFFFF
+; X64-NEXT: cmpq %rax, %rcx
+; X64-NEXT: setg %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: isquiet_d:
; X64-NDD: # %bb.0: # %entry
@@ -1806,15 +1806,15 @@ define i1 @isnan_d_strictfp(double %x) strictfp {
; X86-NEXT: setl %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: isnan_d_strictfp:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movq %xmm0, %rax
-; X64-GENERIC-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
-; X64-GENERIC-NEXT: andq %rax, %rcx
-; X64-GENERIC-NEXT: movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000
-; X64-GENERIC-NEXT: cmpq %rax, %rcx
-; X64-GENERIC-NEXT: setg %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: isnan_d_strictfp:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movq %xmm0, %rax
+; X64-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; X64-NEXT: andq %rax, %rcx
+; X64-NEXT: movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000
+; X64-NEXT: cmpq %rax, %rcx
+; X64-NEXT: setg %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: isnan_d_strictfp:
; X64-NDD: # %bb.0: # %entry
@@ -1839,13 +1839,13 @@ define i1 @iszero_d_strictfp(double %x) strictfp {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: iszero_d_strictfp:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movq %xmm0, %rax
-; X64-GENERIC-NEXT: shlq %rax
-; X64-GENERIC-NEXT: testq %rax, %rax
-; X64-GENERIC-NEXT: sete %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: iszero_d_strictfp:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movq %xmm0, %rax
+; X64-NEXT: shlq %rax
+; X64-NEXT: testq %rax, %rax
+; X64-NEXT: sete %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: iszero_d_strictfp:
; X64-NDD: # %bb.0: # %entry
@@ -1872,11 +1872,11 @@ define <1 x i1> @isnan_v1f(<1 x float> %x) {
; X86-NEXT: setp %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: isnan_v1f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: ucomiss %xmm0, %xmm0
-; X64-GENERIC-NEXT: setp %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: isnan_v1f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: ucomiss %xmm0, %xmm0
+; X64-NEXT: setp %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: isnan_v1f:
; X64-NDD: # %bb.0: # %entry
@@ -1897,13 +1897,13 @@ define <1 x i1> @isnan_v1f_strictfp(<1 x float> %x) strictfp {
; X86-NEXT: setge %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: isnan_v1f_strictfp:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-GENERIC-NEXT: setge %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: isnan_v1f_strictfp:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-NEXT: setge %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: isnan_v1f_strictfp:
; X64-NDD: # %bb.0: # %entry
@@ -1940,6 +1940,12 @@ define <2 x i1> @isnan_v2f(<2 x float> %x) {
; X64-NEXT: cmpunordps %xmm0, %xmm0
; X64-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1,1,3]
; X64-NEXT: retq
+;
+; X64-NDD-LABEL: isnan_v2f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: cmpunordps %xmm0, %xmm0
+; X64-NDD-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1,1,3]
+; X64-NDD-NEXT: retq
entry:
%0 = tail call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, i32 3) ; "nan"
ret <2 x i1> %0
@@ -1969,6 +1975,12 @@ define <2 x i1> @isnot_nan_v2f(<2 x float> %x) {
; X64-NEXT: cmpordps %xmm0, %xmm0
; X64-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1,1,3]
; X64-NEXT: retq
+;
+; X64-NDD-LABEL: isnot_nan_v2f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: cmpordps %xmm0, %xmm0
+; X64-NDD-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1,1,3]
+; X64-NDD-NEXT: retq
entry:
%0 = tail call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, i32 1020) ; 0x3fc = "zero|subnormal|normal|inf"
ret <2 x i1> %0
@@ -1993,6 +2005,13 @@ define <2 x i1> @isnan_v2f_strictfp(<2 x float> %x) strictfp {
; X64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
+;
+; X64-NDD-LABEL: isnan_v2f_strictfp:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1,1,3]
+; X64-NDD-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-NDD-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-NDD-NEXT: retq
entry:
%0 = tail call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, i32 3) strictfp ; "nan"
ret <2 x i1> %0
@@ -2040,6 +2059,11 @@ define <4 x i1> @isnan_v4f(<4 x float> %x) {
; X64: # %bb.0: # %entry
; X64-NEXT: cmpunordps %xmm0, %xmm0
; X64-NEXT: retq
+;
+; X64-NDD-LABEL: isnan_v4f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: cmpunordps %xmm0, %xmm0
+; X64-NDD-NEXT: retq
entry:
%0 = tail call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> %x, i32 3) ; "nan"
ret <4 x i1> %0
@@ -2084,6 +2108,12 @@ define <4 x i1> @isnan_v4f_strictfp(<4 x float> %x) strictfp {
; X64-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
+;
+; X64-NDD-LABEL: isnan_v4f_strictfp:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-NDD-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-NDD-NEXT: retq
entry:
%0 = tail call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> %x, i32 3) strictfp ; "nan"
ret <4 x i1> %0
@@ -2099,6 +2129,11 @@ define i1 @isnone_f(float %x) {
; X64: # %bb.0: # %entry
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: retq
+;
+; X64-NDD-LABEL: isnone_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: xorl %eax, %eax
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 0)
ret i1 %0
@@ -2114,6 +2149,11 @@ define i1 @isany_f(float %x) {
; X64: # %bb.0: # %entry
; X64-NEXT: movb $1, %al
; X64-NEXT: retq
+;
+; X64-NDD-LABEL: isany_f:
+; X64-NDD: # %bb.0: # %entry
+; X64-NDD-NEXT: movb $1, %al
+; X64-NDD-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1023)
ret i1 %0
@@ -2132,12 +2172,12 @@ define i1 @iszero_or_nan_f(float %x) {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: iszero_or_nan_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: xorps %xmm1, %xmm1
-; X64-GENERIC-NEXT: ucomiss %xmm1, %xmm0
-; X64-GENERIC-NEXT: sete %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: iszero_or_nan_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: xorps %xmm1, %xmm1
+; X64-NEXT: ucomiss %xmm1, %xmm0
+; X64-NEXT: sete %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: iszero_or_nan_f:
; X64-NDD: # %bb.0: # %entry
@@ -2162,16 +2202,16 @@ define i1 @iszero_or_nan_f_daz(float %x) #0 {
; X86-NEXT: orb %cl, %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: iszero_or_nan_f_daz:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-GENERIC-NEXT: setge %cl
-; X64-GENERIC-NEXT: testl %eax, %eax
-; X64-GENERIC-NEXT: sete %al
-; X64-GENERIC-NEXT: orb %cl, %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: iszero_or_nan_f_daz:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-NEXT: setge %cl
+; X64-NEXT: testl %eax, %eax
+; X64-NEXT: sete %al
+; X64-NEXT: orb %cl, %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: iszero_or_nan_f_daz:
; X64-NDD: # %bb.0: # %entry
@@ -2200,16 +2240,16 @@ define i1 @iszero_or_nan_f_maybe_daz(float %x) #1 {
; X86-NEXT: orb %cl, %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: iszero_or_nan_f_maybe_daz:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-GENERIC-NEXT: setge %cl
-; X64-GENERIC-NEXT: testl %eax, %eax
-; X64-GENERIC-NEXT: sete %al
-; X64-GENERIC-NEXT: orb %cl, %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: iszero_or_nan_f_maybe_daz:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-NEXT: setge %cl
+; X64-NEXT: testl %eax, %eax
+; X64-NEXT: sete %al
+; X64-NEXT: orb %cl, %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: iszero_or_nan_f_maybe_daz:
; X64-NDD: # %bb.0: # %entry
@@ -2238,12 +2278,12 @@ define i1 @not_iszero_or_nan_f(float %x) {
; X86-NEXT: setne %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_iszero_or_nan_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: xorps %xmm1, %xmm1
-; X64-GENERIC-NEXT: ucomiss %xmm1, %xmm0
-; X64-GENERIC-NEXT: setne %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_iszero_or_nan_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: xorps %xmm1, %xmm1
+; X64-NEXT: ucomiss %xmm1, %xmm0
+; X64-NEXT: setne %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_iszero_or_nan_f:
; X64-NDD: # %bb.0: # %entry
@@ -2268,16 +2308,16 @@ define i1 @not_iszero_or_nan_f_daz(float %x) #0 {
; X86-NEXT: andb %cl, %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_iszero_or_nan_f_daz:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-GENERIC-NEXT: setl %cl
-; X64-GENERIC-NEXT: testl %eax, %eax
-; X64-GENERIC-NEXT: setne %al
-; X64-GENERIC-NEXT: andb %cl, %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_iszero_or_nan_f_daz:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-NEXT: setl %cl
+; X64-NEXT: testl %eax, %eax
+; X64-NEXT: setne %al
+; X64-NEXT: andb %cl, %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_iszero_or_nan_f_daz:
; X64-NDD: # %bb.0: # %entry
@@ -2306,16 +2346,16 @@ define i1 @not_iszero_or_nan_f_maybe_daz(float %x) #1 {
; X86-NEXT: andb %cl, %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_iszero_or_nan_f_maybe_daz:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-GENERIC-NEXT: setl %cl
-; X64-GENERIC-NEXT: testl %eax, %eax
-; X64-GENERIC-NEXT: setne %al
-; X64-GENERIC-NEXT: andb %cl, %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_iszero_or_nan_f_maybe_daz:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-NEXT: setl %cl
+; X64-NEXT: testl %eax, %eax
+; X64-NEXT: setne %al
+; X64-NEXT: andb %cl, %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_iszero_or_nan_f_maybe_daz:
; X64-NDD: # %bb.0: # %entry
@@ -2344,16 +2384,16 @@ define i1 @iszero_or_qnan_f(float %x) {
; X86-NEXT: orb %cl, %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: iszero_or_qnan_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-GENERIC-NEXT: setge %cl
-; X64-GENERIC-NEXT: testl %eax, %eax
-; X64-GENERIC-NEXT: sete %al
-; X64-GENERIC-NEXT: orb %cl, %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: iszero_or_qnan_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-NEXT: setge %cl
+; X64-NEXT: testl %eax, %eax
+; X64-NEXT: sete %al
+; X64-NEXT: orb %cl, %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: iszero_or_qnan_f:
; X64-NDD: # %bb.0: # %entry
@@ -2385,19 +2425,19 @@ define i1 @iszero_or_snan_f(float %x) {
; X86-NEXT: orb %dl, %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: iszero_or_snan_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-GENERIC-NEXT: setl %cl
-; X64-GENERIC-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-GENERIC-NEXT: setge %dl
-; X64-GENERIC-NEXT: andb %cl, %dl
-; X64-GENERIC-NEXT: testl %eax, %eax
-; X64-GENERIC-NEXT: sete %al
-; X64-GENERIC-NEXT: orb %dl, %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: iszero_or_snan_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-NEXT: setl %cl
+; X64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-NEXT: setge %dl
+; X64-NEXT: andb %cl, %dl
+; X64-NEXT: testl %eax, %eax
+; X64-NEXT: sete %al
+; X64-NEXT: orb %dl, %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: iszero_or_snan_f:
; X64-NDD: # %bb.0: # %entry
@@ -2445,27 +2485,27 @@ define i1 @not_iszero_or_qnan_f(float %x) {
; X86-NEXT: .cfi_def_cfa_offset 4
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_iszero_or_qnan_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-GENERIC-NEXT: setl %cl
-; X64-GENERIC-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-GENERIC-NEXT: setge %dl
-; X64-GENERIC-NEXT: andb %cl, %dl
-; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: sete %cl
-; X64-GENERIC-NEXT: leal -1(%rax), %esi
-; X64-GENERIC-NEXT: cmpl $8388607, %esi # imm = 0x7FFFFF
-; X64-GENERIC-NEXT: setb %sil
-; X64-GENERIC-NEXT: orb %cl, %sil
-; X64-GENERIC-NEXT: addl $-8388608, %eax # imm = 0xFF800000
-; X64-GENERIC-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; X64-GENERIC-NEXT: setb %al
-; X64-GENERIC-NEXT: orb %dl, %al
-; X64-GENERIC-NEXT: orb %sil, %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_iszero_or_qnan_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-NEXT: setl %cl
+; X64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-NEXT: setge %dl
+; X64-NEXT: andb %cl, %dl
+; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: sete %cl
+; X64-NEXT: leal -1(%rax), %esi
+; X64-NEXT: cmpl $8388607, %esi # imm = 0x7FFFFF
+; X64-NEXT: setb %sil
+; X64-NEXT: orb %cl, %sil
+; X64-NEXT: addl $-8388608, %eax # imm = 0xFF800000
+; X64-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
+; X64-NEXT: setb %al
+; X64-NEXT: orb %dl, %al
+; X64-NEXT: orb %sil, %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_iszero_or_qnan_f:
; X64-NDD: # %bb.0: # %entry
@@ -2513,24 +2553,24 @@ define i1 @not_iszero_or_snan_f(float %x) {
; X86-NEXT: orb %ch, %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_iszero_or_snan_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: sete %cl
-; X64-GENERIC-NEXT: leal -1(%rax), %edx
-; X64-GENERIC-NEXT: cmpl $8388607, %edx # imm = 0x7FFFFF
-; X64-GENERIC-NEXT: setb %dl
-; X64-GENERIC-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-GENERIC-NEXT: setge %sil
-; X64-GENERIC-NEXT: orb %cl, %sil
-; X64-GENERIC-NEXT: orb %dl, %sil
-; X64-GENERIC-NEXT: addl $-8388608, %eax # imm = 0xFF800000
-; X64-GENERIC-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; X64-GENERIC-NEXT: setb %al
-; X64-GENERIC-NEXT: orb %sil, %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_iszero_or_snan_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: sete %cl
+; X64-NEXT: leal -1(%rax), %edx
+; X64-NEXT: cmpl $8388607, %edx # imm = 0x7FFFFF
+; X64-NEXT: setb %dl
+; X64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-NEXT: setge %sil
+; X64-NEXT: orb %cl, %sil
+; X64-NEXT: orb %dl, %sil
+; X64-NEXT: addl $-8388608, %eax # imm = 0xFF800000
+; X64-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
+; X64-NEXT: setb %al
+; X64-NEXT: orb %sil, %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_iszero_or_snan_f:
; X64-NDD: # %bb.0: # %entry
@@ -2564,13 +2604,13 @@ define i1 @isinf_or_nan_f(float %x) {
; X86-NEXT: setge %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: isinf_or_nan_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: setge %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: isinf_or_nan_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: setge %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: isinf_or_nan_f:
; X64-NDD: # %bb.0: # %entry
@@ -2593,13 +2633,13 @@ define i1 @not_isinf_or_nan_f(float %x) {
; X86-NEXT: setl %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_isinf_or_nan_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: setl %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_isinf_or_nan_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: setl %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_isinf_or_nan_f:
; X64-NDD: # %bb.0: # %entry
@@ -2622,13 +2662,13 @@ define i1 @isfinite_or_nan_f(float %x) {
; X86-NEXT: setne %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: isfinite_or_nan_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: setne %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: isfinite_or_nan_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: setne %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: isfinite_or_nan_f:
; X64-NDD: # %bb.0: # %entry
@@ -2651,13 +2691,13 @@ define i1 @not_isfinite_or_nan_f(float %x) {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_isfinite_or_nan_f:
-; X64-GENERIC: # %bb.0: # %entry
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: sete %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_isfinite_or_nan_f:
+; X64: # %bb.0: # %entry
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: sete %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_isfinite_or_nan_f:
; X64-NDD: # %bb.0: # %entry
@@ -2683,11 +2723,11 @@ define i1 @is_plus_inf_or_nan_f(float %x) {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: is_plus_inf_or_nan_f:
-; X64-GENERIC: # %bb.0:
-; X64-GENERIC-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; X64-GENERIC-NEXT: sete %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: is_plus_inf_or_nan_f:
+; X64: # %bb.0:
+; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-NEXT: sete %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: is_plus_inf_or_nan_f:
; X64-NDD: # %bb.0:
@@ -2710,11 +2750,11 @@ define i1 @is_minus_inf_or_nan_f(float %x) {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: is_minus_inf_or_nan_f:
-; X64-GENERIC: # %bb.0:
-; X64-GENERIC-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; X64-GENERIC-NEXT: sete %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: is_minus_inf_or_nan_f:
+; X64: # %bb.0:
+; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-NEXT: sete %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: is_minus_inf_or_nan_f:
; X64-NDD: # %bb.0:
@@ -2737,11 +2777,11 @@ define i1 @not_is_plus_inf_or_nan_f(float %x) {
; X86-NEXT: setne %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_is_plus_inf_or_nan_f:
-; X64-GENERIC: # %bb.0:
-; X64-GENERIC-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; X64-GENERIC-NEXT: setne %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_is_plus_inf_or_nan_f:
+; X64: # %bb.0:
+; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-NEXT: setne %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_is_plus_inf_or_nan_f:
; X64-NDD: # %bb.0:
@@ -2764,11 +2804,11 @@ define i1 @not_is_minus_inf_or_nan_f(float %x) {
; X86-NEXT: setne %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_is_minus_inf_or_nan_f:
-; X64-GENERIC: # %bb.0:
-; X64-GENERIC-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; X64-GENERIC-NEXT: setne %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_is_minus_inf_or_nan_f:
+; X64: # %bb.0:
+; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-NEXT: setne %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_is_minus_inf_or_nan_f:
; X64-NDD: # %bb.0:
@@ -2795,20 +2835,20 @@ define i1 @is_plus_inf_or_snan_f(float %x) {
; X86-NEXT: orb %cl, %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: is_plus_inf_or_snan_f:
-; X64-GENERIC: # %bb.0:
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: movl %eax, %ecx
-; X64-GENERIC-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
-; X64-GENERIC-NEXT: setl %dl
-; X64-GENERIC-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
-; X64-GENERIC-NEXT: setge %cl
-; X64-GENERIC-NEXT: andb %dl, %cl
-; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: sete %al
-; X64-GENERIC-NEXT: orb %cl, %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: is_plus_inf_or_snan_f:
+; X64: # %bb.0:
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: movl %eax, %ecx
+; X64-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
+; X64-NEXT: setl %dl
+; X64-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
+; X64-NEXT: setge %cl
+; X64-NEXT: andb %dl, %cl
+; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: sete %al
+; X64-NEXT: orb %cl, %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: is_plus_inf_or_snan_f:
; X64-NDD: # %bb.0:
@@ -2839,16 +2879,16 @@ define i1 @is_plus_inf_or_qnan_f(float %x) {
; X86-NEXT: orb %cl, %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: is_plus_inf_or_qnan_f:
-; X64-GENERIC: # %bb.0:
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: sete %cl
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-GENERIC-NEXT: setge %al
-; X64-GENERIC-NEXT: orb %cl, %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: is_plus_inf_or_qnan_f:
+; X64: # %bb.0:
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: sete %cl
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-NEXT: setge %al
+; X64-NEXT: orb %cl, %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: is_plus_inf_or_qnan_f:
; X64-NDD: # %bb.0:
@@ -2879,19 +2919,19 @@ define i1 @not_is_plus_inf_or_snan_f(float %x) {
; X86-NEXT: orb %dl, %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_is_plus_inf_or_snan_f:
-; X64-GENERIC: # %bb.0:
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
-; X64-GENERIC-NEXT: sete %cl
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: setl %dl
-; X64-GENERIC-NEXT: orb %cl, %dl
-; X64-GENERIC-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-GENERIC-NEXT: setge %al
-; X64-GENERIC-NEXT: orb %dl, %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_is_plus_inf_or_snan_f:
+; X64: # %bb.0:
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
+; X64-NEXT: sete %cl
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: setl %dl
+; X64-NEXT: orb %cl, %dl
+; X64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-NEXT: setge %al
+; X64-NEXT: orb %dl, %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_is_plus_inf_or_snan_f:
; X64-NDD: # %bb.0:
@@ -2929,23 +2969,23 @@ define i1 @not_is_plus_inf_or_qnan_f(float %x) {
; X86-NEXT: orb %dh, %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_is_plus_inf_or_qnan_f:
-; X64-GENERIC: # %bb.0:
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: movl %eax, %ecx
-; X64-GENERIC-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
-; X64-GENERIC-NEXT: setl %dl
-; X64-GENERIC-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
-; X64-GENERIC-NEXT: setge %sil
-; X64-GENERIC-NEXT: andb %dl, %sil
-; X64-GENERIC-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
-; X64-GENERIC-NEXT: sete %dl
-; X64-GENERIC-NEXT: cmpl $2139095040, %ecx # imm = 0x7F800000
-; X64-GENERIC-NEXT: setl %al
-; X64-GENERIC-NEXT: orb %dl, %al
-; X64-GENERIC-NEXT: orb %sil, %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_is_plus_inf_or_qnan_f:
+; X64: # %bb.0:
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: movl %eax, %ecx
+; X64-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
+; X64-NEXT: setl %dl
+; X64-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
+; X64-NEXT: setge %sil
+; X64-NEXT: andb %dl, %sil
+; X64-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
+; X64-NEXT: sete %dl
+; X64-NEXT: cmpl $2139095040, %ecx # imm = 0x7F800000
+; X64-NEXT: setl %al
+; X64-NEXT: orb %dl, %al
+; X64-NEXT: orb %sil, %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_is_plus_inf_or_qnan_f:
; X64-NDD: # %bb.0:
@@ -2983,20 +3023,20 @@ define i1 @is_minus_inf_or_snan_f(float %x) {
; X86-NEXT: orb %cl, %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: is_minus_inf_or_snan_f:
-; X64-GENERIC: # %bb.0:
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: movl %eax, %ecx
-; X64-GENERIC-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
-; X64-GENERIC-NEXT: setl %dl
-; X64-GENERIC-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
-; X64-GENERIC-NEXT: setge %cl
-; X64-GENERIC-NEXT: andb %dl, %cl
-; X64-GENERIC-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
-; X64-GENERIC-NEXT: sete %al
-; X64-GENERIC-NEXT: orb %cl, %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: is_minus_inf_or_snan_f:
+; X64: # %bb.0:
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: movl %eax, %ecx
+; X64-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
+; X64-NEXT: setl %dl
+; X64-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
+; X64-NEXT: setge %cl
+; X64-NEXT: andb %dl, %cl
+; X64-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
+; X64-NEXT: sete %al
+; X64-NEXT: orb %cl, %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: is_minus_inf_or_snan_f:
; X64-NDD: # %bb.0:
@@ -3027,16 +3067,16 @@ define i1 @is_minus_inf_or_qnan_f(float %x) {
; X86-NEXT: orb %cl, %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: is_minus_inf_or_qnan_f:
-; X64-GENERIC: # %bb.0:
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
-; X64-GENERIC-NEXT: sete %cl
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-GENERIC-NEXT: setge %al
-; X64-GENERIC-NEXT: orb %cl, %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: is_minus_inf_or_qnan_f:
+; X64: # %bb.0:
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
+; X64-NEXT: sete %cl
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-NEXT: setge %al
+; X64-NEXT: orb %cl, %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: is_minus_inf_or_qnan_f:
; X64-NDD: # %bb.0:
@@ -3067,19 +3107,19 @@ define i1 @not_is_minus_inf_or_snan_f(float %x) {
; X86-NEXT: orb %dl, %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_is_minus_inf_or_snan_f:
-; X64-GENERIC: # %bb.0:
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: sete %cl
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: setl %dl
-; X64-GENERIC-NEXT: orb %cl, %dl
-; X64-GENERIC-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-GENERIC-NEXT: setge %al
-; X64-GENERIC-NEXT: orb %dl, %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_is_minus_inf_or_snan_f:
+; X64: # %bb.0:
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: sete %cl
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: setl %dl
+; X64-NEXT: orb %cl, %dl
+; X64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-NEXT: setge %al
+; X64-NEXT: orb %dl, %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_is_minus_inf_or_snan_f:
; X64-NDD: # %bb.0:
@@ -3117,23 +3157,23 @@ define i1 @not_is_minus_inf_or_qnan_f(float %x) {
; X86-NEXT: orb %dh, %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_is_minus_inf_or_qnan_f:
-; X64-GENERIC: # %bb.0:
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: movl %eax, %ecx
-; X64-GENERIC-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
-; X64-GENERIC-NEXT: setl %dl
-; X64-GENERIC-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
-; X64-GENERIC-NEXT: setge %sil
-; X64-GENERIC-NEXT: andb %dl, %sil
-; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: sete %dl
-; X64-GENERIC-NEXT: cmpl $2139095040, %ecx # imm = 0x7F800000
-; X64-GENERIC-NEXT: setl %al
-; X64-GENERIC-NEXT: orb %dl, %al
-; X64-GENERIC-NEXT: orb %sil, %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_is_minus_inf_or_qnan_f:
+; X64: # %bb.0:
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: movl %eax, %ecx
+; X64-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
+; X64-NEXT: setl %dl
+; X64-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
+; X64-NEXT: setge %sil
+; X64-NEXT: andb %dl, %sil
+; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: sete %dl
+; X64-NEXT: cmpl $2139095040, %ecx # imm = 0x7F800000
+; X64-NEXT: setl %al
+; X64-NEXT: orb %dl, %al
+; X64-NEXT: orb %sil, %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_is_minus_inf_or_qnan_f:
; X64-NDD: # %bb.0:
@@ -3168,17 +3208,17 @@ define i1 @issubnormal_or_nan_f(float %x) {
; X86-NEXT: orb %cl, %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: issubnormal_or_nan_f:
-; X64-GENERIC: # %bb.0:
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-GENERIC-NEXT: setge %cl
-; X64-GENERIC-NEXT: decl %eax
-; X64-GENERIC-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
-; X64-GENERIC-NEXT: setb %al
-; X64-GENERIC-NEXT: orb %cl, %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: issubnormal_or_nan_f:
+; X64: # %bb.0:
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-NEXT: setge %cl
+; X64-NEXT: decl %eax
+; X64-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-NEXT: setb %al
+; X64-NEXT: orb %cl, %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: issubnormal_or_nan_f:
; X64-NDD: # %bb.0:
@@ -3209,12 +3249,12 @@ define i1 @issubnormal_or_zero_or_nan_f(float %x) {
; X86-NEXT: setb %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: issubnormal_or_zero_or_nan_f:
-; X64-GENERIC: # %bb.0:
-; X64-GENERIC-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; X64-GENERIC-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; X64-GENERIC-NEXT: setb %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: issubnormal_or_zero_or_nan_f:
+; X64: # %bb.0:
+; X64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-NEXT: setb %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: issubnormal_or_zero_or_nan_f:
; X64-NDD: # %bb.0:
@@ -3238,12 +3278,12 @@ define i1 @issubnormal_or_zero_or_nan_f_daz(float %x) #0 {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: issubnormal_or_zero_or_nan_f_daz:
-; X64-GENERIC: # %bb.0:
-; X64-GENERIC-NEXT: xorps %xmm1, %xmm1
-; X64-GENERIC-NEXT: ucomiss %xmm1, %xmm0
-; X64-GENERIC-NEXT: sete %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: issubnormal_or_zero_or_nan_f_daz:
+; X64: # %bb.0:
+; X64-NEXT: xorps %xmm1, %xmm1
+; X64-NEXT: ucomiss %xmm1, %xmm0
+; X64-NEXT: sete %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: issubnormal_or_zero_or_nan_f_daz:
; X64-NDD: # %bb.0:
@@ -3271,20 +3311,20 @@ define i1 @issubnormal_or_zero_or_snan_f(float %x) {
; X86-NEXT: orb %cl, %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: issubnormal_or_zero_or_snan_f:
-; X64-GENERIC: # %bb.0:
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: movl %eax, %ecx
-; X64-GENERIC-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
-; X64-GENERIC-NEXT: setl %dl
-; X64-GENERIC-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
-; X64-GENERIC-NEXT: setge %cl
-; X64-GENERIC-NEXT: andb %dl, %cl
-; X64-GENERIC-NEXT: testl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: sete %al
-; X64-GENERIC-NEXT: orb %cl, %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: issubnormal_or_zero_or_snan_f:
+; X64: # %bb.0:
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: movl %eax, %ecx
+; X64-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
+; X64-NEXT: setl %dl
+; X64-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
+; X64-NEXT: setge %cl
+; X64-NEXT: andb %dl, %cl
+; X64-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: sete %al
+; X64-NEXT: orb %cl, %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: issubnormal_or_zero_or_snan_f:
; X64-NDD: # %bb.0:
@@ -3315,16 +3355,16 @@ define i1 @issubnormal_or_zero_or_qnan_f(float %x) {
; X86-NEXT: orb %cl, %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: issubnormal_or_zero_or_qnan_f:
-; X64-GENERIC: # %bb.0:
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: testl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: sete %cl
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-GENERIC-NEXT: setge %al
-; X64-GENERIC-NEXT: orb %cl, %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: issubnormal_or_zero_or_qnan_f:
+; X64: # %bb.0:
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: sete %cl
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-NEXT: setge %al
+; X64-NEXT: orb %cl, %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: issubnormal_or_zero_or_qnan_f:
; X64-NDD: # %bb.0:
@@ -3356,20 +3396,20 @@ define i1 @not_issubnormal_or_nan_f(float %x) {
; X86-NEXT: orb %dl, %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_issubnormal_or_nan_f:
-; X64-GENERIC: # %bb.0:
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: sete %cl
-; X64-GENERIC-NEXT: testl %eax, %eax
-; X64-GENERIC-NEXT: sete %dl
-; X64-GENERIC-NEXT: orb %cl, %dl
-; X64-GENERIC-NEXT: addl $-8388608, %eax # imm = 0xFF800000
-; X64-GENERIC-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; X64-GENERIC-NEXT: setb %al
-; X64-GENERIC-NEXT: orb %dl, %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_issubnormal_or_nan_f:
+; X64: # %bb.0:
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: sete %cl
+; X64-NEXT: testl %eax, %eax
+; X64-NEXT: sete %dl
+; X64-NEXT: orb %cl, %dl
+; X64-NEXT: addl $-8388608, %eax # imm = 0xFF800000
+; X64-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
+; X64-NEXT: setb %al
+; X64-NEXT: orb %dl, %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_issubnormal_or_nan_f:
; X64-NDD: # %bb.0:
@@ -3403,12 +3443,12 @@ define i1 @not_issubnormal_or_zero_or_nan_f(float %x) {
; X86-NEXT: setae %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_issubnormal_or_zero_or_nan_f:
-; X64-GENERIC: # %bb.0:
-; X64-GENERIC-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; X64-GENERIC-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; X64-GENERIC-NEXT: setae %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_issubnormal_or_zero_or_nan_f:
+; X64: # %bb.0:
+; X64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-NEXT: setae %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_issubnormal_or_zero_or_nan_f:
; X64-NDD: # %bb.0:
@@ -3432,12 +3472,12 @@ define i1 @not_issubnormal_or_zero_or_nan_f_daz(float %x) #0 {
; X86-NEXT: setne %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_issubnormal_or_zero_or_nan_f_daz:
-; X64-GENERIC: # %bb.0:
-; X64-GENERIC-NEXT: xorps %xmm1, %xmm1
-; X64-GENERIC-NEXT: ucomiss %xmm1, %xmm0
-; X64-GENERIC-NEXT: setne %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_issubnormal_or_zero_or_nan_f_daz:
+; X64: # %bb.0:
+; X64-NEXT: xorps %xmm1, %xmm1
+; X64-NEXT: ucomiss %xmm1, %xmm0
+; X64-NEXT: setne %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_issubnormal_or_zero_or_nan_f_daz:
; X64-NDD: # %bb.0:
@@ -3465,20 +3505,20 @@ define i1 @not_issubnormal_or_zero_or_snan_f(float %x) {
; X86-NEXT: orb %dl, %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_issubnormal_or_zero_or_snan_f:
-; X64-GENERIC: # %bb.0:
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-GENERIC-NEXT: setge %cl
-; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: sete %dl
-; X64-GENERIC-NEXT: orb %cl, %dl
-; X64-GENERIC-NEXT: addl $-8388608, %eax # imm = 0xFF800000
-; X64-GENERIC-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; X64-GENERIC-NEXT: setb %al
-; X64-GENERIC-NEXT: orb %dl, %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_issubnormal_or_zero_or_snan_f:
+; X64: # %bb.0:
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-NEXT: setge %cl
+; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: sete %dl
+; X64-NEXT: orb %cl, %dl
+; X64-NEXT: addl $-8388608, %eax # imm = 0xFF800000
+; X64-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
+; X64-NEXT: setb %al
+; X64-NEXT: orb %dl, %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_issubnormal_or_zero_or_snan_f:
; X64-NDD: # %bb.0:
@@ -3517,23 +3557,23 @@ define i1 @not_issubnormal_or_zero_or_qnan_f(float %x) {
; X86-NEXT: orb %cl, %al
; X86-NEXT: retl
;
-; X64-GENERIC-LABEL: not_issubnormal_or_zero_or_qnan_f:
-; X64-GENERIC: # %bb.0:
-; X64-GENERIC-NEXT: movd %xmm0, %eax
-; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-GENERIC-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-GENERIC-NEXT: setl %cl
-; X64-GENERIC-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-GENERIC-NEXT: setge %dl
-; X64-GENERIC-NEXT: andb %cl, %dl
-; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-GENERIC-NEXT: sete %cl
-; X64-GENERIC-NEXT: orb %dl, %cl
-; X64-GENERIC-NEXT: addl $-8388608, %eax # imm = 0xFF800000
-; X64-GENERIC-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; X64-GENERIC-NEXT: setb %al
-; X64-GENERIC-NEXT: orb %cl, %al
-; X64-GENERIC-NEXT: retq
+; X64-LABEL: not_issubnormal_or_zero_or_qnan_f:
+; X64: # %bb.0:
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-NEXT: setl %cl
+; X64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-NEXT: setge %dl
+; X64-NEXT: andb %cl, %dl
+; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-NEXT: sete %cl
+; X64-NEXT: orb %dl, %cl
+; X64-NEXT: addl $-8388608, %eax # imm = 0xFF800000
+; X64-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
+; X64-NEXT: setb %al
+; X64-NEXT: orb %cl, %al
+; X64-NEXT: retq
;
; X64-NDD-LABEL: not_issubnormal_or_zero_or_qnan_f:
; X64-NDD: # %bb.0:
@@ -3567,3 +3607,5 @@ attributes #0 = { "denormal-fp-math"="ieee,preserve-sign" }
; Maybe daz
attributes #1 = { "denormal-fp-math"="ieee,dynamic" }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; X64-GENERIC: {{.*}}
>From 92f4fdd7b1470da5b07ad35f0edffc86e0fe1b42 Mon Sep 17 00:00:00 2001
From: Feng Zou <feng.zou at intel.com>
Date: Fri, 13 Jun 2025 11:46:55 +0800
Subject: [PATCH 4/6] Update per comments.
---
llvm/lib/Target/X86/X86FastISel.cpp | 22 ++++++++++------------
llvm/lib/Target/X86/X86FixupSetCC.cpp | 3 +--
2 files changed, 11 insertions(+), 14 deletions(-)
diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp
index 282d32669d522..ec6d7410c1d91 100644
--- a/llvm/lib/Target/X86/X86FastISel.cpp
+++ b/llvm/lib/Target/X86/X86FastISel.cpp
@@ -1434,6 +1434,8 @@ bool X86FastISel::X86FastEmitCompare(const Value *Op0, const Value *Op1, EVT VT,
return true;
}
+#define GET_SETCC (Subtarget->hasZU() ? X86::SETZUCCr : X86::SETCCr)
+
bool X86FastISel::X86SelectCmp(const Instruction *I) {
const CmpInst *CI = cast<CmpInst>(I);
@@ -1503,11 +1505,11 @@ bool X86FastISel::X86SelectCmp(const Instruction *I) {
Register FlagReg1 = createResultReg(&X86::GR8RegClass);
Register FlagReg2 = createResultReg(&X86::GR8RegClass);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(Subtarget->hasZU() ? X86::SETZUCCr : X86::SETCCr), FlagReg1)
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(GET_SETCC),
+ FlagReg1)
.addImm(SETFOpc[0]);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(Subtarget->hasZU() ? X86::SETZUCCr : X86::SETCCr), FlagReg2)
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(GET_SETCC),
+ FlagReg2)
.addImm(SETFOpc[1]);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(SETFOpc[2]),
ResultReg).addReg(FlagReg1).addReg(FlagReg2);
@@ -1527,8 +1529,7 @@ bool X86FastISel::X86SelectCmp(const Instruction *I) {
if (!X86FastEmitCompare(LHS, RHS, VT, I->getDebugLoc()))
return false;
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(Subtarget->hasZU() ? X86::SETZUCCr : X86::SETCCr), ResultReg)
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(GET_SETCC), ResultReg)
.addImm(CC);
updateValueMap(I, ResultReg);
return true;
@@ -2086,12 +2087,10 @@ bool X86FastISel::X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I) {
if (SETFOpc) {
Register FlagReg1 = createResultReg(&X86::GR8RegClass);
Register FlagReg2 = createResultReg(&X86::GR8RegClass);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(Subtarget->hasZU() ? X86::SETZUCCr : X86::SETCCr),
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(GET_SETCC),
FlagReg1)
.addImm(SETFOpc[0]);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(Subtarget->hasZU() ? X86::SETZUCCr : X86::SETCCr),
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(GET_SETCC),
FlagReg2)
.addImm(SETFOpc[1]);
auto const &II = TII.get(SETFOpc[2]);
@@ -2996,8 +2995,7 @@ bool X86FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
// Assign to a GPR since the overflow return value is lowered to a SETcc.
Register ResultReg2 = createResultReg(&X86::GR8RegClass);
assert((ResultReg+1) == ResultReg2 && "Nonconsecutive result registers.");
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(Subtarget->hasZU() ? X86::SETZUCCr : X86::SETCCr),
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(GET_SETCC),
ResultReg2)
.addImm(CondCode);
diff --git a/llvm/lib/Target/X86/X86FixupSetCC.cpp b/llvm/lib/Target/X86/X86FixupSetCC.cpp
index 8ea5ed695c356..93dc0e7b02d14 100644
--- a/llvm/lib/Target/X86/X86FixupSetCC.cpp
+++ b/llvm/lib/Target/X86/X86FixupSetCC.cpp
@@ -82,8 +82,7 @@ bool X86FixupSetCCPass::runOnMachineFunction(MachineFunction &MF) {
// Find a setcc/setzucc (if ZU is enabled) that is used by a zext.
// This doesn't have to be the only use, the transformation is safe
// regardless.
- if (MI.getOpcode() != X86::SETCCr &&
- (!ST->hasZU() || MI.getOpcode() != X86::SETZUCCr))
+ if (MI.getOpcode() != X86::SETCCr && MI.getOpcode() != X86::SETZUCCr)
continue;
MachineInstr *ZExt = nullptr;
>From 608f9574b257bae2ef496b915c30d693b5959561 Mon Sep 17 00:00:00 2001
From: Feng Zou <feng.zou at intel.com>
Date: Fri, 13 Jun 2025 14:53:39 +0800
Subject: [PATCH 5/6] Update predicate for setcc/setzucc and tests accordingly
---
llvm/lib/Target/X86/X86FixupSetCC.cpp | 4 +-
llvm/lib/Target/X86/X86InstrCMovSetCC.td | 4 +-
llvm/lib/Target/X86/X86InstrPredicates.td | 1 +
llvm/test/CodeGen/X86/apx/add.ll | 4 +-
llvm/test/CodeGen/X86/apx/and.ll | 404 +++-
llvm/test/CodeGen/X86/apx/ccmp.ll | 528 +++-
llvm/test/CodeGen/X86/apx/ctest.ll | 459 +++-
.../CodeGen/X86/apx/flags-copy-lowering.mir | 989 ++++----
llvm/test/CodeGen/X86/apx/mul-i1024.ll | 70 +-
llvm/test/CodeGen/X86/apx/or.ll | 60 +-
llvm/test/CodeGen/X86/apx/xor.ll | 60 +-
llvm/test/CodeGen/X86/cmp.ll | 1656 ++++++-------
llvm/test/CodeGen/X86/is_fpclass.ll | 2154 ++++++++++-------
llvm/test/CodeGen/X86/scmp.ll | 607 +++++
llvm/test/CodeGen/X86/select_const_i128.ll | 26 +-
15 files changed, 4623 insertions(+), 2403 deletions(-)
diff --git a/llvm/lib/Target/X86/X86FixupSetCC.cpp b/llvm/lib/Target/X86/X86FixupSetCC.cpp
index 93dc0e7b02d14..2bb86ee53a08f 100644
--- a/llvm/lib/Target/X86/X86FixupSetCC.cpp
+++ b/llvm/lib/Target/X86/X86FixupSetCC.cpp
@@ -122,8 +122,8 @@ bool X86FixupSetCCPass::runOnMachineFunction(MachineFunction &MF) {
// register.
Register ZeroReg = MRI->createVirtualRegister(RC);
if (ST->hasZU()) {
- if (MI.getOpcode() != X86::SETZUCCr)
- MI.setDesc(TII->get(X86::SETZUCCr));
+ assert((MI.getOpcode() == X86::SETZUCCr) &&
+ "Expect setzucc instruction!");
BuildMI(*ZExt->getParent(), ZExt, ZExt->getDebugLoc(),
TII->get(TargetOpcode::IMPLICIT_DEF), ZeroReg);
} else {
diff --git a/llvm/lib/Target/X86/X86InstrCMovSetCC.td b/llvm/lib/Target/X86/X86InstrCMovSetCC.td
index 06bf70f18e30d..0c2123f5836ec 100644
--- a/llvm/lib/Target/X86/X86InstrCMovSetCC.td
+++ b/llvm/lib/Target/X86/X86InstrCMovSetCC.td
@@ -137,7 +137,7 @@ let Predicates = [HasCMOV, HasCF] in {
}
// SetCC instructions.
-let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1, Predicates = [NoNDD] in {
+let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1, Predicates = [NoZU] in {
def SETCCr : I<0x90, MRMXrCC, (outs GR8:$dst), (ins ccode:$cond),
"set${cond}\t$dst",
[(set GR8:$dst, (X86setcc timm:$cond, EFLAGS))]>,
@@ -153,7 +153,7 @@ let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1 in {
// SetZUCC and promoted SetCC instructions.
let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1,
- hasSideEffects = 0, Predicates = [In64BitMode], Predicates = [HasNDD] in {
+ hasSideEffects = 0, Predicates = [In64BitMode], Predicates = [HasZU] in {
def SETZUCCr : I<0x40, MRMXrCC, (outs GR8:$dst), (ins ccode:$cond),
"setzu${cond}\t$dst",
[(set GR8:$dst, (X86setcc timm:$cond, EFLAGS))]>,
diff --git a/llvm/lib/Target/X86/X86InstrPredicates.td b/llvm/lib/Target/X86/X86InstrPredicates.td
index 307c03c8ef541..fd3fb4ae9d9e8 100644
--- a/llvm/lib/Target/X86/X86InstrPredicates.td
+++ b/llvm/lib/Target/X86/X86InstrPredicates.td
@@ -46,6 +46,7 @@ def NoEGPR : Predicate<"!Subtarget->hasEGPR()">;
def HasNDD : Predicate<"Subtarget->hasNDD()">;
def NoNDD : Predicate<"!Subtarget->hasNDD()">;
def HasZU : Predicate<"Subtarget->hasZU()">;
+def NoZU : Predicate<"!Subtarget->hasZU()">;
def HasCF : Predicate<"Subtarget->hasCF()">;
def HasCMOV : Predicate<"Subtarget->canUseCMOV()">;
def NoCMOV : Predicate<"!Subtarget->canUseCMOV()">;
diff --git a/llvm/test/CodeGen/X86/apx/add.ll b/llvm/test/CodeGen/X86/apx/add.ll
index c8e1e055f8ca4..86343811901a9 100644
--- a/llvm/test/CodeGen/X86/apx/add.ll
+++ b/llvm/test/CodeGen/X86/apx/add.ll
@@ -758,7 +758,7 @@ define i1 @add64ri_reloc(i16 %k) {
; CHECK-NEXT: addq %rax, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x01,0xc0]
; CHECK-NEXT: addq $val, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x05,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: val, kind: reloc_signed_4byte
-; CHECK-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; CHECK-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: add64ri_reloc:
@@ -768,7 +768,7 @@ define i1 @add64ri_reloc(i16 %k) {
; NF-NEXT: addq %rax, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x01,0xc0]
; NF-NEXT: addq $val, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x05,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: val, kind: reloc_signed_4byte
-; NF-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NF-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
; NF-NEXT: retq # encoding: [0xc3]
%g = getelementptr inbounds i16, ptr @val, i16 %k
%cmp = icmp ne ptr %g, null
diff --git a/llvm/test/CodeGen/X86/apx/and.ll b/llvm/test/CodeGen/X86/apx/and.ll
index 6de07a5b72587..c65ba4e50417a 100644
--- a/llvm/test/CodeGen/X86/apx/and.ll
+++ b/llvm/test/CodeGen/X86/apx/and.ll
@@ -2,6 +2,7 @@
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd -verify-machineinstrs --show-mc-encoding | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd,nf -verify-machineinstrs --show-mc-encoding | FileCheck --check-prefix=NF %s
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ndd,nf -x86-enable-apx-for-relocation=true -verify-machineinstrs --show-mc-encoding | FileCheck --check-prefix=NF %s
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+zu -verify-machineinstrs --show-mc-encoding | FileCheck %s --check-prefix=ZU
define i8 @and8rr(i8 noundef %a, i8 noundef %b) {
; CHECK-LABEL: and8rr:
@@ -15,6 +16,13 @@ define i8 @and8rr(i8 noundef %a, i8 noundef %b) {
; NF-NEXT: {nf} andl %esi, %edi, %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x21,0xf7]
; NF-NEXT: # kill: def $al killed $al killed $eax
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and8rr:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: movl %edi, %eax # encoding: [0x89,0xf8]
+; ZU-NEXT: andl %esi, %eax # encoding: [0x21,0xf0]
+; ZU-NEXT: # kill: def $al killed $al killed $eax
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%and = and i8 %a, %b
ret i8 %and
@@ -32,6 +40,13 @@ define i16 @and16rr(i16 noundef %a, i16 noundef %b) {
; NF-NEXT: {nf} andl %esi, %edi, %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x21,0xf7]
; NF-NEXT: # kill: def $ax killed $ax killed $eax
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and16rr:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: movl %edi, %eax # encoding: [0x89,0xf8]
+; ZU-NEXT: andl %esi, %eax # encoding: [0x21,0xf0]
+; ZU-NEXT: # kill: def $ax killed $ax killed $eax
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%and = and i16 %a, %b
ret i16 %and
@@ -47,6 +62,12 @@ define i32 @and32rr(i32 noundef %a, i32 noundef %b) {
; NF: # %bb.0: # %entry
; NF-NEXT: {nf} andl %esi, %edi, %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x21,0xf7]
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and32rr:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: movl %edi, %eax # encoding: [0x89,0xf8]
+; ZU-NEXT: andl %esi, %eax # encoding: [0x21,0xf0]
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%and = and i32 %a, %b
ret i32 %and
@@ -62,6 +83,12 @@ define i64 @and64rr(i64 noundef %a, i64 noundef %b) {
; NF: # %bb.0: # %entry
; NF-NEXT: {nf} andq %rsi, %rdi, %rax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0xfc,0x1c,0x21,0xf7]
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and64rr:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: movq %rdi, %rax # encoding: [0x48,0x89,0xf8]
+; ZU-NEXT: andq %rsi, %rax # encoding: [0x48,0x21,0xf0]
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%and = and i64 %a, %b
ret i64 %and
@@ -77,6 +104,13 @@ define i8 @and8rm(i8 noundef %a, ptr %b) {
; NF: # %bb.0: # %entry
; NF-NEXT: {nf} andb (%rsi), %dil, %al # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x22,0x3e]
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and8rm:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: movl %edi, %eax # encoding: [0x89,0xf8]
+; ZU-NEXT: andb (%rsi), %al # encoding: [0x22,0x06]
+; ZU-NEXT: # kill: def $al killed $al killed $eax
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%t = load i8, ptr %b
%and = and i8 %a, %t
@@ -93,6 +127,13 @@ define i16 @and16rm(i16 noundef %a, ptr %b) {
; NF: # %bb.0: # %entry
; NF-NEXT: {nf} andw (%rsi), %di, %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0x23,0x3e]
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and16rm:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: movl %edi, %eax # encoding: [0x89,0xf8]
+; ZU-NEXT: andw (%rsi), %ax # encoding: [0x66,0x23,0x06]
+; ZU-NEXT: # kill: def $ax killed $ax killed $eax
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%t = load i16, ptr %b
%and = and i16 %a, %t
@@ -109,6 +150,12 @@ define i32 @and32rm(i32 noundef %a, ptr %b) {
; NF: # %bb.0: # %entry
; NF-NEXT: {nf} andl (%rsi), %edi, %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x23,0x3e]
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and32rm:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: movl %edi, %eax # encoding: [0x89,0xf8]
+; ZU-NEXT: andl (%rsi), %eax # encoding: [0x23,0x06]
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%t = load i32, ptr %b
%and = and i32 %a, %t
@@ -125,6 +172,12 @@ define i64 @and64rm(i64 noundef %a, ptr %b) {
; NF: # %bb.0: # %entry
; NF-NEXT: {nf} andq (%rsi), %rdi, %rax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0xfc,0x1c,0x23,0x3e]
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and64rm:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: movq %rdi, %rax # encoding: [0x48,0x89,0xf8]
+; ZU-NEXT: andq (%rsi), %rax # encoding: [0x48,0x23,0x06]
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%t = load i64, ptr %b
%and = and i64 %a, %t
@@ -141,6 +194,13 @@ define i16 @and16ri8(i16 noundef %a) {
; NF: # %bb.0: # %entry
; NF-NEXT: {nf} andw $123, %di, %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0x83,0xe7,0x7b]
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and16ri8:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: movl %edi, %eax # encoding: [0x89,0xf8]
+; ZU-NEXT: andl $123, %eax # encoding: [0x83,0xe0,0x7b]
+; ZU-NEXT: # kill: def $ax killed $ax killed $eax
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%and = and i16 %a, 123
ret i16 %and
@@ -156,6 +216,12 @@ define i32 @and32ri8(i32 noundef %a) {
; NF: # %bb.0: # %entry
; NF-NEXT: {nf} andl $123, %edi, %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x83,0xe7,0x7b]
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and32ri8:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: movl %edi, %eax # encoding: [0x89,0xf8]
+; ZU-NEXT: andl $123, %eax # encoding: [0x83,0xe0,0x7b]
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%and = and i32 %a, 123
ret i32 %and
@@ -171,6 +237,12 @@ define i64 @and64ri8(i64 noundef %a) {
; NF: # %bb.0: # %entry
; NF-NEXT: {nf} andl $123, %edi, %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x83,0xe7,0x7b]
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and64ri8:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: movq %rdi, %rax # encoding: [0x48,0x89,0xf8]
+; ZU-NEXT: andl $123, %eax # encoding: [0x83,0xe0,0x7b]
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%and = and i64 %a, 123
ret i64 %and
@@ -186,6 +258,13 @@ define i8 @and8ri(i8 noundef %a) {
; NF: # %bb.0: # %entry
; NF-NEXT: {nf} andb $123, %dil, %al # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x80,0xe7,0x7b]
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and8ri:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: movl %edi, %eax # encoding: [0x89,0xf8]
+; ZU-NEXT: andb $123, %al # encoding: [0x24,0x7b]
+; ZU-NEXT: # kill: def $al killed $al killed $eax
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%and = and i8 %a, 123
ret i8 %and
@@ -203,6 +282,14 @@ define i16 @and16ri(i16 noundef %a) {
; NF-NEXT: {nf} andw $1234, %di, %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0x81,0xe7,0xd2,0x04]
; NF-NEXT: # imm = 0x4D2
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and16ri:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: movl %edi, %eax # encoding: [0x89,0xf8]
+; ZU-NEXT: andl $1234, %eax # encoding: [0x25,0xd2,0x04,0x00,0x00]
+; ZU-NEXT: # imm = 0x4D2
+; ZU-NEXT: # kill: def $ax killed $ax killed $eax
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%and = and i16 %a, 1234
ret i16 %and
@@ -220,6 +307,13 @@ define i32 @and32ri(i32 noundef %a) {
; NF-NEXT: {nf} andl $123456, %edi, %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x81,0xe7,0x40,0xe2,0x01,0x00]
; NF-NEXT: # imm = 0x1E240
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and32ri:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: movl %edi, %eax # encoding: [0x89,0xf8]
+; ZU-NEXT: andl $123456, %eax # encoding: [0x25,0x40,0xe2,0x01,0x00]
+; ZU-NEXT: # imm = 0x1E240
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%and = and i32 %a, 123456
ret i32 %and
@@ -237,6 +331,13 @@ define i64 @and64ri(i64 noundef %a) {
; NF-NEXT: {nf} andl $123456, %edi, %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x81,0xe7,0x40,0xe2,0x01,0x00]
; NF-NEXT: # imm = 0x1E240
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and64ri:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: movq %rdi, %rax # encoding: [0x48,0x89,0xf8]
+; ZU-NEXT: andl $123456, %eax # encoding: [0x25,0x40,0xe2,0x01,0x00]
+; ZU-NEXT: # imm = 0x1E240
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%and = and i64 %a, 123456
ret i64 %and
@@ -252,6 +353,13 @@ define i8 @and8mr(ptr %a, i8 noundef %b) {
; NF: # %bb.0: # %entry
; NF-NEXT: {nf} andb (%rdi), %sil, %al # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x22,0x37]
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and8mr:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: movl %esi, %eax # encoding: [0x89,0xf0]
+; ZU-NEXT: andb (%rdi), %al # encoding: [0x22,0x07]
+; ZU-NEXT: # kill: def $al killed $al killed $eax
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%t= load i8, ptr %a
%and = and i8 %t, %b
@@ -268,6 +376,13 @@ define i16 @and16mr(ptr %a, i16 noundef %b) {
; NF: # %bb.0: # %entry
; NF-NEXT: {nf} andw (%rdi), %si, %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0x23,0x37]
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and16mr:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: movl %esi, %eax # encoding: [0x89,0xf0]
+; ZU-NEXT: andw (%rdi), %ax # encoding: [0x66,0x23,0x07]
+; ZU-NEXT: # kill: def $ax killed $ax killed $eax
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%t= load i16, ptr %a
%and = and i16 %t, %b
@@ -284,6 +399,12 @@ define i32 @and32mr(ptr %a, i32 noundef %b) {
; NF: # %bb.0: # %entry
; NF-NEXT: {nf} andl (%rdi), %esi, %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x23,0x37]
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and32mr:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: movl %esi, %eax # encoding: [0x89,0xf0]
+; ZU-NEXT: andl (%rdi), %eax # encoding: [0x23,0x07]
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%t= load i32, ptr %a
%and = and i32 %t, %b
@@ -300,6 +421,12 @@ define i64 @and64mr(ptr %a, i64 noundef %b) {
; NF: # %bb.0: # %entry
; NF-NEXT: {nf} andq (%rdi), %rsi, %rax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0xfc,0x1c,0x23,0x37]
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and64mr:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: movq %rsi, %rax # encoding: [0x48,0x89,0xf0]
+; ZU-NEXT: andq (%rdi), %rax # encoding: [0x48,0x23,0x07]
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%t= load i64, ptr %a
%and = and i64 %t, %b
@@ -316,6 +443,13 @@ define i16 @and16mi8(ptr %a) {
; NF: # %bb.0: # %entry
; NF-NEXT: {nf} andw $123, (%rdi), %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0x83,0x27,0x7b]
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and16mi8:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: movzwl (%rdi), %eax # encoding: [0x0f,0xb7,0x07]
+; ZU-NEXT: andl $123, %eax # encoding: [0x83,0xe0,0x7b]
+; ZU-NEXT: # kill: def $ax killed $ax killed $eax
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%t= load i16, ptr %a
%and = and i16 %t, 123
@@ -332,6 +466,12 @@ define i32 @and32mi8(ptr %a) {
; NF: # %bb.0: # %entry
; NF-NEXT: {nf} andl $123, (%rdi), %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x83,0x27,0x7b]
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and32mi8:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: movl (%rdi), %eax # encoding: [0x8b,0x07]
+; ZU-NEXT: andl $123, %eax # encoding: [0x83,0xe0,0x7b]
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%t= load i32, ptr %a
%and = and i32 %t, 123
@@ -350,6 +490,12 @@ define i64 @and64mi8(ptr %a) {
; NF-NEXT: movq (%rdi), %rax # encoding: [0x48,0x8b,0x07]
; NF-NEXT: andl $123, %eax # EVEX TO LEGACY Compression encoding: [0x83,0xe0,0x7b]
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and64mi8:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: movq (%rdi), %rax # encoding: [0x48,0x8b,0x07]
+; ZU-NEXT: andl $123, %eax # encoding: [0x83,0xe0,0x7b]
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%t= load i64, ptr %a
%and = and i64 %t, 123
@@ -366,6 +512,12 @@ define i8 @and8mi(ptr %a) {
; NF: # %bb.0: # %entry
; NF-NEXT: {nf} andb $123, (%rdi), %al # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x80,0x27,0x7b]
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and8mi:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: movzbl (%rdi), %eax # encoding: [0x0f,0xb6,0x07]
+; ZU-NEXT: andb $123, %al # encoding: [0x24,0x7b]
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%t= load i8, ptr %a
%and = and i8 %t, 123
@@ -384,6 +536,14 @@ define i16 @and16mi(ptr %a) {
; NF-NEXT: {nf} andw $1234, (%rdi), %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0x81,0x27,0xd2,0x04]
; NF-NEXT: # imm = 0x4D2
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and16mi:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: movzwl (%rdi), %eax # encoding: [0x0f,0xb7,0x07]
+; ZU-NEXT: andl $1234, %eax # encoding: [0x25,0xd2,0x04,0x00,0x00]
+; ZU-NEXT: # imm = 0x4D2
+; ZU-NEXT: # kill: def $ax killed $ax killed $eax
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%t= load i16, ptr %a
%and = and i16 %t, 1234
@@ -402,6 +562,13 @@ define i32 @and32mi(ptr %a) {
; NF-NEXT: {nf} andl $123456, (%rdi), %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x81,0x27,0x40,0xe2,0x01,0x00]
; NF-NEXT: # imm = 0x1E240
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and32mi:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: movl $123456, %eax # encoding: [0xb8,0x40,0xe2,0x01,0x00]
+; ZU-NEXT: # imm = 0x1E240
+; ZU-NEXT: andl (%rdi), %eax # encoding: [0x23,0x07]
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%t= load i32, ptr %a
%and = and i32 %t, 123456
@@ -422,6 +589,13 @@ define i64 @and64mi(ptr %a) {
; NF-NEXT: andl $123456, %eax # EVEX TO LEGACY Compression encoding: [0x25,0x40,0xe2,0x01,0x00]
; NF-NEXT: # imm = 0x1E240
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and64mi:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: movq (%rdi), %rax # encoding: [0x48,0x8b,0x07]
+; ZU-NEXT: andl $123456, %eax # encoding: [0x25,0x40,0xe2,0x01,0x00]
+; ZU-NEXT: # imm = 0x1E240
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%t= load i64, ptr %a
%and = and i64 %t, 123456
@@ -435,7 +609,7 @@ define i1 @andflag8rr(i8 %a, i8 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: notb %sil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xf6,0xd6]
; CHECK-NEXT: andb %al, %dil, %cl # encoding: [0x62,0xf4,0x74,0x18,0x20,0xc7]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -444,10 +618,19 @@ define i1 @andflag8rr(i8 %a, i8 %b) {
; NF: # %bb.0:
; NF-NEXT: notb %sil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xf6,0xd6]
; NF-NEXT: andb %al, %dil, %cl # encoding: [0x62,0xf4,0x74,0x18,0x20,0xc7]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: andflag8rr:
+; ZU: # %bb.0:
+; ZU-NEXT: notb %sil # encoding: [0x40,0xf6,0xd6]
+; ZU-NEXT: andb %dil, %sil # encoding: [0x40,0x20,0xfe]
+; ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; ZU-NEXT: movb %sil, d64(%rip) # encoding: [0x40,0x88,0x35,A,A,A,A]
+; ZU-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
+; ZU-NEXT: retq # encoding: [0xc3]
%xor = xor i8 %b, -1
%v0 = and i8 %a, %xor ; 0xff << 50
%v1 = icmp eq i8 %v0, 0
@@ -460,7 +643,7 @@ define i1 @andflag16rr(i16 %a, i16 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: notw %si, %ax # encoding: [0x62,0xf4,0x7d,0x18,0xf7,0xd6]
; CHECK-NEXT: andw %ax, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x21,0xc7]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -469,10 +652,19 @@ define i1 @andflag16rr(i16 %a, i16 %b) {
; NF: # %bb.0:
; NF-NEXT: notw %si, %ax # encoding: [0x62,0xf4,0x7d,0x18,0xf7,0xd6]
; NF-NEXT: andw %ax, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x21,0xc7]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: andflag16rr:
+; ZU: # %bb.0:
+; ZU-NEXT: notl %esi # encoding: [0xf7,0xd6]
+; ZU-NEXT: andw %di, %si # encoding: [0x66,0x21,0xfe]
+; ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; ZU-NEXT: movw %si, d64(%rip) # encoding: [0x66,0x89,0x35,A,A,A,A]
+; ZU-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
+; ZU-NEXT: retq # encoding: [0xc3]
%xor = xor i16 %b, -1
%v0 = and i16 %a, %xor ; 0xff << 50
%v1 = icmp eq i16 %v0, 0
@@ -484,7 +676,7 @@ define i1 @andflag32rr(i32 %a, i32 %b) {
; CHECK-LABEL: andflag32rr:
; CHECK: # %bb.0:
; CHECK-NEXT: andl %edi, %esi # EVEX TO LEGACY Compression encoding: [0x21,0xfe]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movl %esi, d64(%rip) # encoding: [0x89,0x35,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -492,10 +684,18 @@ define i1 @andflag32rr(i32 %a, i32 %b) {
; NF-LABEL: andflag32rr:
; NF: # %bb.0:
; NF-NEXT: andl %edi, %esi # EVEX TO LEGACY Compression encoding: [0x21,0xfe]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movl %esi, d64(%rip) # encoding: [0x89,0x35,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: andflag32rr:
+; ZU: # %bb.0:
+; ZU-NEXT: andl %esi, %edi # encoding: [0x21,0xf7]
+; ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; ZU-NEXT: movl %edi, d64(%rip) # encoding: [0x89,0x3d,A,A,A,A]
+; ZU-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
+; ZU-NEXT: retq # encoding: [0xc3]
%v0 = and i32 %a, %b ; 0xff << 50
%v1 = icmp eq i32 %v0, 0
store i32 %v0, ptr @d64
@@ -506,7 +706,7 @@ define i1 @andflag64rr(i64 %a, i64 %b) {
; CHECK-LABEL: andflag64rr:
; CHECK: # %bb.0:
; CHECK-NEXT: andq %rdi, %rsi # EVEX TO LEGACY Compression encoding: [0x48,0x21,0xfe]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movq %rsi, d64(%rip) # encoding: [0x48,0x89,0x35,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -514,10 +714,18 @@ define i1 @andflag64rr(i64 %a, i64 %b) {
; NF-LABEL: andflag64rr:
; NF: # %bb.0:
; NF-NEXT: andq %rdi, %rsi # EVEX TO LEGACY Compression encoding: [0x48,0x21,0xfe]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movq %rsi, d64(%rip) # encoding: [0x48,0x89,0x35,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: andflag64rr:
+; ZU: # %bb.0:
+; ZU-NEXT: andq %rsi, %rdi # encoding: [0x48,0x21,0xf7]
+; ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; ZU-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
+; ZU-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
+; ZU-NEXT: retq # encoding: [0xc3]
%v0 = and i64 %a, %b ; 0xff << 50
%v1 = icmp eq i64 %v0, 0
store i64 %v0, ptr @d64
@@ -529,7 +737,7 @@ define i1 @andflag8rm(ptr %ptr, i8 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: notb %sil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xf6,0xd6]
; CHECK-NEXT: andb (%rdi), %al, %cl # encoding: [0x62,0xf4,0x74,0x18,0x22,0x07]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -538,10 +746,19 @@ define i1 @andflag8rm(ptr %ptr, i8 %b) {
; NF: # %bb.0:
; NF-NEXT: notb %sil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xf6,0xd6]
; NF-NEXT: andb (%rdi), %al, %cl # encoding: [0x62,0xf4,0x74,0x18,0x22,0x07]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: andflag8rm:
+; ZU: # %bb.0:
+; ZU-NEXT: notb %sil # encoding: [0x40,0xf6,0xd6]
+; ZU-NEXT: andb (%rdi), %sil # encoding: [0x40,0x22,0x37]
+; ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; ZU-NEXT: movb %sil, d64(%rip) # encoding: [0x40,0x88,0x35,A,A,A,A]
+; ZU-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
+; ZU-NEXT: retq # encoding: [0xc3]
%a = load i8, ptr %ptr
%xor = xor i8 %b, -1
%v0 = and i8 %a, %xor ; 0xff << 50
@@ -555,7 +772,7 @@ define i1 @andflag16rm(ptr %ptr, i16 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: notw %si, %ax # encoding: [0x62,0xf4,0x7d,0x18,0xf7,0xd6]
; CHECK-NEXT: andw (%rdi), %ax, %cx # encoding: [0x62,0xf4,0x75,0x18,0x23,0x07]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -564,10 +781,19 @@ define i1 @andflag16rm(ptr %ptr, i16 %b) {
; NF: # %bb.0:
; NF-NEXT: notw %si, %ax # encoding: [0x62,0xf4,0x7d,0x18,0xf7,0xd6]
; NF-NEXT: andw (%rdi), %ax, %cx # encoding: [0x62,0xf4,0x75,0x18,0x23,0x07]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: andflag16rm:
+; ZU: # %bb.0:
+; ZU-NEXT: notl %esi # encoding: [0xf7,0xd6]
+; ZU-NEXT: andw (%rdi), %si # encoding: [0x66,0x23,0x37]
+; ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; ZU-NEXT: movw %si, d64(%rip) # encoding: [0x66,0x89,0x35,A,A,A,A]
+; ZU-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
+; ZU-NEXT: retq # encoding: [0xc3]
%a = load i16, ptr %ptr
%xor = xor i16 %b, -1
%v0 = and i16 %a, %xor ; 0xff << 50
@@ -580,7 +806,7 @@ define i1 @andflag32rm(ptr %ptr, i32 %b) {
; CHECK-LABEL: andflag32rm:
; CHECK: # %bb.0:
; CHECK-NEXT: andl (%rdi), %esi # EVEX TO LEGACY Compression encoding: [0x23,0x37]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movl %esi, d64(%rip) # encoding: [0x89,0x35,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -588,10 +814,18 @@ define i1 @andflag32rm(ptr %ptr, i32 %b) {
; NF-LABEL: andflag32rm:
; NF: # %bb.0:
; NF-NEXT: andl (%rdi), %esi # EVEX TO LEGACY Compression encoding: [0x23,0x37]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movl %esi, d64(%rip) # encoding: [0x89,0x35,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: andflag32rm:
+; ZU: # %bb.0:
+; ZU-NEXT: andl (%rdi), %esi # encoding: [0x23,0x37]
+; ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; ZU-NEXT: movl %esi, d64(%rip) # encoding: [0x89,0x35,A,A,A,A]
+; ZU-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
+; ZU-NEXT: retq # encoding: [0xc3]
%a = load i32, ptr %ptr
%v0 = and i32 %a, %b ; 0xff << 50
%v1 = icmp eq i32 %v0, 0
@@ -603,7 +837,7 @@ define i1 @andflag64rm(ptr %ptr, i64 %b) {
; CHECK-LABEL: andflag64rm:
; CHECK: # %bb.0:
; CHECK-NEXT: andq (%rdi), %rsi # EVEX TO LEGACY Compression encoding: [0x48,0x23,0x37]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movq %rsi, d64(%rip) # encoding: [0x48,0x89,0x35,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -611,10 +845,18 @@ define i1 @andflag64rm(ptr %ptr, i64 %b) {
; NF-LABEL: andflag64rm:
; NF: # %bb.0:
; NF-NEXT: andq (%rdi), %rsi # EVEX TO LEGACY Compression encoding: [0x48,0x23,0x37]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movq %rsi, d64(%rip) # encoding: [0x48,0x89,0x35,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: andflag64rm:
+; ZU: # %bb.0:
+; ZU-NEXT: andq (%rdi), %rsi # encoding: [0x48,0x23,0x37]
+; ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; ZU-NEXT: movq %rsi, d64(%rip) # encoding: [0x48,0x89,0x35,A,A,A,A]
+; ZU-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
+; ZU-NEXT: retq # encoding: [0xc3]
%a = load i64, ptr %ptr
%v0 = and i64 %a, %b ; 0xff << 50
%v1 = icmp eq i64 %v0, 0
@@ -626,7 +868,7 @@ define i1 @andflag8ri(i8 %a) {
; CHECK-LABEL: andflag8ri:
; CHECK: # %bb.0:
; CHECK-NEXT: andb $-124, %dil, %cl # encoding: [0x62,0xf4,0x74,0x18,0x80,0xe7,0x84]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -634,10 +876,18 @@ define i1 @andflag8ri(i8 %a) {
; NF-LABEL: andflag8ri:
; NF: # %bb.0:
; NF-NEXT: andb $-124, %dil, %cl # encoding: [0x62,0xf4,0x74,0x18,0x80,0xe7,0x84]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: andflag8ri:
+; ZU: # %bb.0:
+; ZU-NEXT: andb $-124, %dil # encoding: [0x40,0x80,0xe7,0x84]
+; ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; ZU-NEXT: movb %dil, d64(%rip) # encoding: [0x40,0x88,0x3d,A,A,A,A]
+; ZU-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
+; ZU-NEXT: retq # encoding: [0xc3]
%xor = xor i8 123, -1
%v0 = and i8 %a, %xor ; 0xff << 50
%v1 = icmp eq i8 %v0, 0
@@ -650,7 +900,7 @@ define i1 @andflag16ri(i16 %a) {
; CHECK: # %bb.0:
; CHECK-NEXT: andw $-1235, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x81,0xe7,0x2d,0xfb]
; CHECK-NEXT: # imm = 0xFB2D
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -659,10 +909,19 @@ define i1 @andflag16ri(i16 %a) {
; NF: # %bb.0:
; NF-NEXT: andw $-1235, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x81,0xe7,0x2d,0xfb]
; NF-NEXT: # imm = 0xFB2D
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: andflag16ri:
+; ZU: # %bb.0:
+; ZU-NEXT: andw $-1235, %di # encoding: [0x66,0x81,0xe7,0x2d,0xfb]
+; ZU-NEXT: # imm = 0xFB2D
+; ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; ZU-NEXT: movw %di, d64(%rip) # encoding: [0x66,0x89,0x3d,A,A,A,A]
+; ZU-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
+; ZU-NEXT: retq # encoding: [0xc3]
%xor = xor i16 1234, -1
%v0 = and i16 %a, %xor ; 0xff << 50
%v1 = icmp eq i16 %v0, 0
@@ -675,7 +934,7 @@ define i1 @andflag32ri(i32 %a) {
; CHECK: # %bb.0:
; CHECK-NEXT: andl $123456, %edi # EVEX TO LEGACY Compression encoding: [0x81,0xe7,0x40,0xe2,0x01,0x00]
; CHECK-NEXT: # imm = 0x1E240
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movl %edi, d64(%rip) # encoding: [0x89,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -684,10 +943,19 @@ define i1 @andflag32ri(i32 %a) {
; NF: # %bb.0:
; NF-NEXT: andl $123456, %edi # EVEX TO LEGACY Compression encoding: [0x81,0xe7,0x40,0xe2,0x01,0x00]
; NF-NEXT: # imm = 0x1E240
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movl %edi, d64(%rip) # encoding: [0x89,0x3d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: andflag32ri:
+; ZU: # %bb.0:
+; ZU-NEXT: andl $123456, %edi # encoding: [0x81,0xe7,0x40,0xe2,0x01,0x00]
+; ZU-NEXT: # imm = 0x1E240
+; ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; ZU-NEXT: movl %edi, d64(%rip) # encoding: [0x89,0x3d,A,A,A,A]
+; ZU-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
+; ZU-NEXT: retq # encoding: [0xc3]
%v0 = and i32 %a, 123456 ; 0xff << 50
%v1 = icmp eq i32 %v0, 0
store i32 %v0, ptr @d64
@@ -699,7 +967,7 @@ define i1 @andflag64ri(i64 %a) {
; CHECK: # %bb.0:
; CHECK-NEXT: andq $123456, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x81,0xe7,0x40,0xe2,0x01,0x00]
; CHECK-NEXT: # imm = 0x1E240
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -708,10 +976,19 @@ define i1 @andflag64ri(i64 %a) {
; NF: # %bb.0:
; NF-NEXT: andq $123456, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x81,0xe7,0x40,0xe2,0x01,0x00]
; NF-NEXT: # imm = 0x1E240
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: andflag64ri:
+; ZU: # %bb.0:
+; ZU-NEXT: andq $123456, %rdi # encoding: [0x48,0x81,0xe7,0x40,0xe2,0x01,0x00]
+; ZU-NEXT: # imm = 0x1E240
+; ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; ZU-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
+; ZU-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
+; ZU-NEXT: retq # encoding: [0xc3]
%v0 = and i64 %a, 123456 ; 0xff << 50
%v1 = icmp eq i64 %v0, 0
store i64 %v0, ptr @d64
@@ -722,7 +999,7 @@ define i1 @andflag16ri8(i16 %a) {
; CHECK-LABEL: andflag16ri8:
; CHECK: # %bb.0:
; CHECK-NEXT: andw $-124, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x83,0xe7,0x84]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -730,10 +1007,18 @@ define i1 @andflag16ri8(i16 %a) {
; NF-LABEL: andflag16ri8:
; NF: # %bb.0:
; NF-NEXT: andw $-124, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x83,0xe7,0x84]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: andflag16ri8:
+; ZU: # %bb.0:
+; ZU-NEXT: andw $-124, %di # encoding: [0x66,0x83,0xe7,0x84]
+; ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; ZU-NEXT: movw %di, d64(%rip) # encoding: [0x66,0x89,0x3d,A,A,A,A]
+; ZU-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
+; ZU-NEXT: retq # encoding: [0xc3]
%xor = xor i16 123, -1
%v0 = and i16 %a, %xor ; 0xff << 50
%v1 = icmp eq i16 %v0, 0
@@ -745,7 +1030,7 @@ define i1 @andflag32ri8(i32 %a) {
; CHECK-LABEL: andflag32ri8:
; CHECK: # %bb.0:
; CHECK-NEXT: andl $123, %edi # EVEX TO LEGACY Compression encoding: [0x83,0xe7,0x7b]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movl %edi, d64(%rip) # encoding: [0x89,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -753,10 +1038,18 @@ define i1 @andflag32ri8(i32 %a) {
; NF-LABEL: andflag32ri8:
; NF: # %bb.0:
; NF-NEXT: andl $123, %edi # EVEX TO LEGACY Compression encoding: [0x83,0xe7,0x7b]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movl %edi, d64(%rip) # encoding: [0x89,0x3d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: andflag32ri8:
+; ZU: # %bb.0:
+; ZU-NEXT: andl $123, %edi # encoding: [0x83,0xe7,0x7b]
+; ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; ZU-NEXT: movl %edi, d64(%rip) # encoding: [0x89,0x3d,A,A,A,A]
+; ZU-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
+; ZU-NEXT: retq # encoding: [0xc3]
%v0 = and i32 %a, 123 ; 0xff << 50
%v1 = icmp eq i32 %v0, 0
store i32 %v0, ptr @d64
@@ -767,7 +1060,7 @@ define i1 @andflag64ri8(i64 %a) {
; CHECK-LABEL: andflag64ri8:
; CHECK: # %bb.0:
; CHECK-NEXT: andq $123, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x83,0xe7,0x7b]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -775,10 +1068,18 @@ define i1 @andflag64ri8(i64 %a) {
; NF-LABEL: andflag64ri8:
; NF: # %bb.0:
; NF-NEXT: andq $123, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x83,0xe7,0x7b]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: andflag64ri8:
+; ZU: # %bb.0:
+; ZU-NEXT: andq $123, %rdi # encoding: [0x48,0x83,0xe7,0x7b]
+; ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; ZU-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
+; ZU-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
+; ZU-NEXT: retq # encoding: [0xc3]
%v0 = and i64 %a, 123 ; 0xff << 50
%v1 = icmp eq i64 %v0, 0
store i64 %v0, ptr @d64
@@ -795,6 +1096,11 @@ define void @and8mr_legacy(ptr %a, i8 noundef %b) {
; NF: # %bb.0: # %entry
; NF-NEXT: andb %sil, (%rdi) # encoding: [0x40,0x20,0x37]
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and8mr_legacy:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: andb %sil, (%rdi) # encoding: [0x40,0x20,0x37]
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%t= load i8, ptr %a
%and = and i8 %t, %b
@@ -812,6 +1118,11 @@ define void @and16mr_legacy(ptr %a, i16 noundef %b) {
; NF: # %bb.0: # %entry
; NF-NEXT: andw %si, (%rdi) # encoding: [0x66,0x21,0x37]
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and16mr_legacy:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: andw %si, (%rdi) # encoding: [0x66,0x21,0x37]
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%t= load i16, ptr %a
%and = and i16 %t, %b
@@ -829,6 +1140,11 @@ define void @and32mr_legacy(ptr %a, i32 noundef %b) {
; NF: # %bb.0: # %entry
; NF-NEXT: andl %esi, (%rdi) # encoding: [0x21,0x37]
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and32mr_legacy:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: andl %esi, (%rdi) # encoding: [0x21,0x37]
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%t= load i32, ptr %a
%and = and i32 %t, %b
@@ -846,6 +1162,11 @@ define void @and64mr_legacy(ptr %a, i64 noundef %b) {
; NF: # %bb.0: # %entry
; NF-NEXT: andq %rsi, (%rdi) # encoding: [0x48,0x21,0x37]
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and64mr_legacy:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: andq %rsi, (%rdi) # encoding: [0x48,0x21,0x37]
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%t= load i64, ptr %a
%and = and i64 %t, %b
@@ -863,6 +1184,11 @@ define void @and8mi_legacy(ptr %a) {
; NF: # %bb.0: # %entry
; NF-NEXT: andb $123, (%rdi) # encoding: [0x80,0x27,0x7b]
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and8mi_legacy:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: andb $123, (%rdi) # encoding: [0x80,0x27,0x7b]
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%t= load i8, ptr %a
%and = and i8 %t, 123
@@ -882,6 +1208,12 @@ define void @and16mi_legacy(ptr %a) {
; NF-NEXT: andw $1234, (%rdi) # encoding: [0x66,0x81,0x27,0xd2,0x04]
; NF-NEXT: # imm = 0x4D2
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and16mi_legacy:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: andw $1234, (%rdi) # encoding: [0x66,0x81,0x27,0xd2,0x04]
+; ZU-NEXT: # imm = 0x4D2
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%t= load i16, ptr %a
%and = and i16 %t, 1234
@@ -901,6 +1233,12 @@ define void @and32mi_legacy(ptr %a) {
; NF-NEXT: andl $123456, (%rdi) # encoding: [0x81,0x27,0x40,0xe2,0x01,0x00]
; NF-NEXT: # imm = 0x1E240
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and32mi_legacy:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: andl $123456, (%rdi) # encoding: [0x81,0x27,0x40,0xe2,0x01,0x00]
+; ZU-NEXT: # imm = 0x1E240
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%t= load i32, ptr %a
%and = and i32 %t, 123456
@@ -920,6 +1258,12 @@ define void @and64mi_legacy(ptr %a) {
; NF-NEXT: andq $123456, (%rdi) # encoding: [0x48,0x81,0x27,0x40,0xe2,0x01,0x00]
; NF-NEXT: # imm = 0x1E240
; NF-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: and64mi_legacy:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: andq $123456, (%rdi) # encoding: [0x48,0x81,0x27,0x40,0xe2,0x01,0x00]
+; ZU-NEXT: # imm = 0x1E240
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%t= load i64, ptr %a
%and = and i64 %t, 123456
diff --git a/llvm/test/CodeGen/X86/apx/ccmp.ll b/llvm/test/CodeGen/X86/apx/ccmp.ll
index 210079537a38b..45f00a173cfc1 100644
--- a/llvm/test/CodeGen/X86/apx/ccmp.ll
+++ b/llvm/test/CodeGen/X86/apx/ccmp.ll
@@ -1,6 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ccmp -show-mc-encoding -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ccmp,+ndd -show-mc-encoding -verify-machineinstrs | FileCheck %s --check-prefix=NDD
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+zu -verify-machineinstrs --show-mc-encoding | FileCheck %s --check-prefix=ZU
define void @ccmp8rr_zf(i8 noundef %a, i8 noundef %b, i8 noundef %c) {
; CHECK-LABEL: ccmp8rr_zf:
@@ -30,6 +31,23 @@ define void @ccmp8rr_zf(i8 noundef %a, i8 noundef %b, i8 noundef %c) {
; NDD-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
; NDD-NEXT: .LBB0_1: # %if.end
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: ccmp8rr_zf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: cmpb %dl, %dil # encoding: [0x40,0x38,0xd7]
+; ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; ZU-NEXT: cmpb %dl, %sil # encoding: [0x40,0x38,0xd6]
+; ZU-NEXT: setzune %cl # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc1]
+; ZU-NEXT: testb %cl, %al # encoding: [0x84,0xc8]
+; ZU-NEXT: jne .LBB0_1 # encoding: [0x75,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB0_1-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
+; ZU-NEXT: .LBB0_1: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%cmp = icmp eq i8 %a, %c
%cmp1 = icmp eq i8 %b, %c
@@ -72,6 +90,23 @@ define void @ccmp8rr_cf(i8 noundef %a, i8 noundef %b) {
; NDD-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
; NDD-NEXT: .LBB1_1: # %if.end
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: ccmp8rr_cf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: cmpb $2, %dil # encoding: [0x40,0x80,0xff,0x02]
+; ZU-NEXT: setzul %al # encoding: [0x62,0xf4,0x7f,0x18,0x4c,0xc0]
+; ZU-NEXT: cmpb $2, %sil # encoding: [0x40,0x80,0xfe,0x02]
+; ZU-NEXT: setzub %cl # encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc1]
+; ZU-NEXT: orb %al, %cl # encoding: [0x08,0xc1]
+; ZU-NEXT: jne .LBB1_1 # encoding: [0x75,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB1_1-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
+; ZU-NEXT: .LBB1_1: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%cmp = icmp sgt i8 %a, 1
%tobool = icmp ugt i8 %b, 1
@@ -110,6 +145,22 @@ define i8 @ccmp8rr_sf(i8 %a, i8 %b, i8* nocapture %c) {
; NDD-NEXT: .LBB2_2: # %if.end
; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: ccmp8rr_sf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: testb %dil, %dil # encoding: [0x40,0x84,0xff]
+; ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; ZU-NEXT: cmpb $2, %sil # encoding: [0x40,0x80,0xfe,0x02]
+; ZU-NEXT: setzuge %cl # encoding: [0x62,0xf4,0x7f,0x18,0x4d,0xc1]
+; ZU-NEXT: andb %al, %cl # encoding: [0x20,0xc1]
+; ZU-NEXT: cmpb $1, %cl # encoding: [0x80,0xf9,0x01]
+; ZU-NEXT: jne .LBB2_2 # encoding: [0x75,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB2_2-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.1: # %if.then
+; ZU-NEXT: movb %dil, (%rdx) # encoding: [0x40,0x88,0x3a]
+; ZU-NEXT: .LBB2_2: # %if.end
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%tobool = icmp ne i8 %a, 0
%cmp = icmp sgt i8 %b, 1
@@ -148,6 +199,22 @@ define i8 @ccmp8rr_none(i8 %a, i8 %b, i8* nocapture %c) {
; NDD-NEXT: .LBB3_2: # %if.end
; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: ccmp8rr_none:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: testb %dil, %dil # encoding: [0x40,0x84,0xff]
+; ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; ZU-NEXT: cmpb $2, %sil # encoding: [0x40,0x80,0xfe,0x02]
+; ZU-NEXT: setzuge %cl # encoding: [0x62,0xf4,0x7f,0x18,0x4d,0xc1]
+; ZU-NEXT: orb %al, %cl # encoding: [0x08,0xc1]
+; ZU-NEXT: cmpb $1, %cl # encoding: [0x80,0xf9,0x01]
+; ZU-NEXT: jne .LBB3_2 # encoding: [0x75,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB3_2-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.1: # %if.then
+; ZU-NEXT: movb %dil, (%rdx) # encoding: [0x40,0x88,0x3a]
+; ZU-NEXT: .LBB3_2: # %if.end
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%tobool = icmp ne i8 %a, 0
%cmp = icmp sgt i8 %b, 1
@@ -190,6 +257,23 @@ define void @ccmp16rr_sf(i16 noundef %a, i16 noundef %b, i16 noundef %c) {
; NDD-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
; NDD-NEXT: .LBB4_1: # %if.end
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: ccmp16rr_sf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: cmpw %dx, %di # encoding: [0x66,0x39,0xd7]
+; ZU-NEXT: setzule %al # encoding: [0x62,0xf4,0x7f,0x18,0x4e,0xc0]
+; ZU-NEXT: cmpw %dx, %si # encoding: [0x66,0x39,0xd6]
+; ZU-NEXT: setzuge %cl # encoding: [0x62,0xf4,0x7f,0x18,0x4d,0xc1]
+; ZU-NEXT: testb %cl, %al # encoding: [0x84,0xc8]
+; ZU-NEXT: jne .LBB4_1 # encoding: [0x75,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB4_1-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
+; ZU-NEXT: .LBB4_1: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%cmp = icmp sgt i16 %a, %c
%cmp1 = icmp slt i16 %b, %c
@@ -232,6 +316,23 @@ define void @ccmp32rr_cf(i32 noundef %a, i32 noundef %b, i32 noundef %c) {
; NDD-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
; NDD-NEXT: .LBB5_1: # %if.end
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: ccmp32rr_cf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: cmpl %edx, %edi # encoding: [0x39,0xd7]
+; ZU-NEXT: setzub %al # encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc0]
+; ZU-NEXT: cmpl %edx, %esi # encoding: [0x39,0xd6]
+; ZU-NEXT: setzua %cl # encoding: [0x62,0xf4,0x7f,0x18,0x47,0xc1]
+; ZU-NEXT: testb %cl, %al # encoding: [0x84,0xc8]
+; ZU-NEXT: jne .LBB5_1 # encoding: [0x75,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB5_1-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
+; ZU-NEXT: .LBB5_1: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%cmp = icmp uge i32 %a, %c
%cmp1 = icmp ule i32 %b, %c
@@ -274,6 +375,23 @@ define void @ccmp64rr_of(i64 %a, i64 %b, i64 %c) {
; NDD-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
; NDD-NEXT: .LBB6_1: # %if.end
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: ccmp64rr_of:
+; ZU: # %bb.0: # %bb
+; ZU-NEXT: cmpq %rdx, %rdi # encoding: [0x48,0x39,0xd7]
+; ZU-NEXT: setzub %al # encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc0]
+; ZU-NEXT: cmpq %rsi, %rdi # encoding: [0x48,0x39,0xf7]
+; ZU-NEXT: setzuno %cl # encoding: [0x62,0xf4,0x7f,0x18,0x41,0xc1]
+; ZU-NEXT: testb %cl, %al # encoding: [0x84,0xc8]
+; ZU-NEXT: jne .LBB6_1 # encoding: [0x75,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB6_1-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
+; ZU-NEXT: .LBB6_1: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
bb:
%cmp = icmp uge i64 %a, %c
%smul = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %a, i64 %b)
@@ -309,6 +427,16 @@ define void @ccmp64rr_of_crossbb(i64 %a, i64 %b) {
; NDD-NEXT: cmpq %rsi, %rdi # encoding: [0x48,0x39,0xf7]
; NDD-NEXT: .LBB7_2: # %bb3
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: ccmp64rr_of_crossbb:
+; ZU: # %bb.0: # %bb
+; ZU-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff]
+; ZU-NEXT: je .LBB7_2 # encoding: [0x74,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB7_2-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.1: # %bb1
+; ZU-NEXT: cmpq %rsi, %rdi # encoding: [0x48,0x39,0xf7]
+; ZU-NEXT: .LBB7_2: # %bb3
+; ZU-NEXT: retq # encoding: [0xc3]
bb:
%cond1 = icmp eq i64 %a, 0
br i1 %cond1, label %bb3, label %bb1
@@ -354,6 +482,23 @@ define void @ccmp8ri_zf(i8 noundef %a, i8 noundef %b, i8 noundef %c) {
; NDD-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
; NDD-NEXT: .LBB8_1: # %if.end
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: ccmp8ri_zf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: cmpb %dl, %dil # encoding: [0x40,0x38,0xd7]
+; ZU-NEXT: setzule %al # encoding: [0x62,0xf4,0x7f,0x18,0x4e,0xc0]
+; ZU-NEXT: cmpb $123, %sil # encoding: [0x40,0x80,0xfe,0x7b]
+; ZU-NEXT: setzune %cl # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc1]
+; ZU-NEXT: testb %cl, %al # encoding: [0x84,0xc8]
+; ZU-NEXT: jne .LBB8_1 # encoding: [0x75,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB8_1-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
+; ZU-NEXT: .LBB8_1: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%cmp = icmp sgt i8 %a, %c
%cmp1 = icmp eq i8 %b, 123
@@ -394,6 +539,22 @@ define i8 @ccmp8ri_zf_double(i8 %a, double %b, i8* nocapture %c) {
; NDD-NEXT: .LBB9_2: # %if.end
; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: ccmp8ri_zf_double:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: cmpb $123, %dil # encoding: [0x40,0x80,0xff,0x7b]
+; ZU-NEXT: je .LBB9_3 # encoding: [0x74,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB9_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.1: # %entry
+; ZU-NEXT: xorpd %xmm1, %xmm1 # encoding: [0x66,0x0f,0x57,0xc9]
+; ZU-NEXT: ucomisd %xmm1, %xmm0 # encoding: [0x66,0x0f,0x2e,0xc1]
+; ZU-NEXT: jne .LBB9_3 # encoding: [0x75,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB9_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.then
+; ZU-NEXT: movb %dil, (%rsi) # encoding: [0x40,0x88,0x3e]
+; ZU-NEXT: .LBB9_3: # %if.end
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%tobool = icmp ne i8 %a, 123
%cmp = fcmp ueq double %b, 0.0
@@ -428,9 +589,9 @@ define i8 @ccmp8ri_zf_double_p(i8 %a, double %b, i8* nocapture %c) {
; NDD-LABEL: ccmp8ri_zf_double_p:
; NDD: # %bb.0: # %entry
; NDD-NEXT: cmpb $123, %dil # encoding: [0x40,0x80,0xff,0x7b]
-; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
; NDD-NEXT: ucomisd %xmm0, %xmm0 # encoding: [0x66,0x0f,0x2e,0xc0]
-; NDD-NEXT: setzup %cl # encoding: [0x62,0xf4,0x7f,0x18,0x4a,0xc1]
+; NDD-NEXT: setp %cl # encoding: [0x0f,0x9a,0xc1]
; NDD-NEXT: andb %cl, %al # EVEX TO LEGACY Compression encoding: [0x20,0xc8]
; NDD-NEXT: cmpb $1, %al # encoding: [0x3c,0x01]
; NDD-NEXT: jne .LBB10_2 # encoding: [0x75,A]
@@ -440,6 +601,21 @@ define i8 @ccmp8ri_zf_double_p(i8 %a, double %b, i8* nocapture %c) {
; NDD-NEXT: .LBB10_2: # %if.end
; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: ccmp8ri_zf_double_p:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: cmpb $123, %dil # encoding: [0x40,0x80,0xff,0x7b]
+; ZU-NEXT: je .LBB10_3 # encoding: [0x74,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB10_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.1: # %entry
+; ZU-NEXT: ucomisd %xmm0, %xmm0 # encoding: [0x66,0x0f,0x2e,0xc0]
+; ZU-NEXT: jnp .LBB10_3 # encoding: [0x7b,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB10_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.then
+; ZU-NEXT: movb %dil, (%rsi) # encoding: [0x40,0x88,0x3e]
+; ZU-NEXT: .LBB10_3: # %if.end
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%tobool = icmp ne i8 %a, 123
%cmp = fcmp uno double %b, 0.0
@@ -474,9 +650,9 @@ define i8 @ccmp8ri_zf_double_np(i8 %a, double %b, i8* nocapture %c) {
; NDD-LABEL: ccmp8ri_zf_double_np:
; NDD: # %bb.0: # %entry
; NDD-NEXT: cmpb $123, %dil # encoding: [0x40,0x80,0xff,0x7b]
-; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
; NDD-NEXT: ucomisd %xmm0, %xmm0 # encoding: [0x66,0x0f,0x2e,0xc0]
-; NDD-NEXT: setzunp %cl # encoding: [0x62,0xf4,0x7f,0x18,0x4b,0xc1]
+; NDD-NEXT: setnp %cl # encoding: [0x0f,0x9b,0xc1]
; NDD-NEXT: andb %cl, %al # EVEX TO LEGACY Compression encoding: [0x20,0xc8]
; NDD-NEXT: cmpb $1, %al # encoding: [0x3c,0x01]
; NDD-NEXT: jne .LBB11_2 # encoding: [0x75,A]
@@ -486,6 +662,21 @@ define i8 @ccmp8ri_zf_double_np(i8 %a, double %b, i8* nocapture %c) {
; NDD-NEXT: .LBB11_2: # %if.end
; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: ccmp8ri_zf_double_np:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: cmpb $123, %dil # encoding: [0x40,0x80,0xff,0x7b]
+; ZU-NEXT: je .LBB11_3 # encoding: [0x74,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB11_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.1: # %entry
+; ZU-NEXT: ucomisd %xmm0, %xmm0 # encoding: [0x66,0x0f,0x2e,0xc0]
+; ZU-NEXT: jp .LBB11_3 # encoding: [0x7a,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB11_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.then
+; ZU-NEXT: movb %dil, (%rsi) # encoding: [0x40,0x88,0x3e]
+; ZU-NEXT: .LBB11_3: # %if.end
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%tobool = icmp ne i8 %a, 123
%cmp = fcmp ord double %b, 0.0
@@ -532,6 +723,25 @@ define void @ccmp16ri_zf(i16 noundef %a, i16 noundef %b, i16 noundef %c) {
; NDD-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
; NDD-NEXT: .LBB12_1: # %if.end
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: ccmp16ri_zf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: cmpw %dx, %di # encoding: [0x66,0x39,0xd7]
+; ZU-NEXT: setzuae %al # encoding: [0x62,0xf4,0x7f,0x18,0x43,0xc0]
+; ZU-NEXT: movswl %si, %ecx # encoding: [0x0f,0xbf,0xce]
+; ZU-NEXT: cmpl $1234, %ecx # encoding: [0x81,0xf9,0xd2,0x04,0x00,0x00]
+; ZU-NEXT: # imm = 0x4D2
+; ZU-NEXT: setzuge %cl # encoding: [0x62,0xf4,0x7f,0x18,0x4d,0xc1]
+; ZU-NEXT: testb %cl, %al # encoding: [0x84,0xc8]
+; ZU-NEXT: jne .LBB12_1 # encoding: [0x75,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB12_1-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
+; ZU-NEXT: .LBB12_1: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%cmp = icmp ult i16 %a, %c
%cmp1 = icmp slt i16 %b, 1234
@@ -576,6 +786,24 @@ define void @ccmp32ri_cf(i32 noundef %a, i32 noundef %b, i32 noundef %c) {
; NDD-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
; NDD-NEXT: .LBB13_1: # %if.end
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: ccmp32ri_cf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: cmpl %edx, %edi # encoding: [0x39,0xd7]
+; ZU-NEXT: setzub %al # encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc0]
+; ZU-NEXT: cmpl $1048577, %esi # encoding: [0x81,0xfe,0x01,0x00,0x10,0x00]
+; ZU-NEXT: # imm = 0x100001
+; ZU-NEXT: setzuae %cl # encoding: [0x62,0xf4,0x7f,0x18,0x43,0xc1]
+; ZU-NEXT: testb %cl, %al # encoding: [0x84,0xc8]
+; ZU-NEXT: jne .LBB13_1 # encoding: [0x75,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB13_1-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
+; ZU-NEXT: .LBB13_1: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%cmp = icmp uge i32 %a, %c
%cmp1 = icmp ule i32 %b, 1048576
@@ -620,6 +848,24 @@ define void @ccmp64ri32_zf(i64 noundef %a, i64 noundef %b, i64 noundef %c) {
; NDD-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
; NDD-NEXT: .LBB14_1: # %if.end
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: ccmp64ri32_zf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: cmpq %rdx, %rdi # encoding: [0x48,0x39,0xd7]
+; ZU-NEXT: setzube %al # encoding: [0x62,0xf4,0x7f,0x18,0x46,0xc0]
+; ZU-NEXT: cmpq $123456, %rsi # encoding: [0x48,0x81,0xfe,0x40,0xe2,0x01,0x00]
+; ZU-NEXT: # imm = 0x1E240
+; ZU-NEXT: setzuge %cl # encoding: [0x62,0xf4,0x7f,0x18,0x4d,0xc1]
+; ZU-NEXT: testb %cl, %al # encoding: [0x84,0xc8]
+; ZU-NEXT: jne .LBB14_1 # encoding: [0x75,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB14_1-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
+; ZU-NEXT: .LBB14_1: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%cmp = icmp ugt i64 %a, %c
%cmp1 = icmp slt i64 %b, 123456
@@ -662,6 +908,23 @@ define void @ccmp8rm_zf(i8 noundef %a, i8 noundef %b, i8 noundef %c, ptr %ptr) {
; NDD-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
; NDD-NEXT: .LBB15_1: # %if.end
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: ccmp8rm_zf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: cmpb %dl, %dil # encoding: [0x40,0x38,0xd7]
+; ZU-NEXT: je .LBB15_3 # encoding: [0x74,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB15_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.1: # %entry
+; ZU-NEXT: cmpb (%rcx), %sil # encoding: [0x40,0x3a,0x31]
+; ZU-NEXT: je .LBB15_3 # encoding: [0x74,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB15_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
+; ZU-NEXT: .LBB15_3: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
entry:
%d = load i8, ptr %ptr
%cmp = icmp eq i8 %a, %c
@@ -705,6 +968,23 @@ define void @ccmp16rm_sf(i16 noundef %a, i16 noundef %b, i16 noundef %c, ptr %pt
; NDD-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
; NDD-NEXT: .LBB16_1: # %if.end
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: ccmp16rm_sf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: cmpw %dx, %di # encoding: [0x66,0x39,0xd7]
+; ZU-NEXT: jg .LBB16_3 # encoding: [0x7f,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB16_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.1: # %entry
+; ZU-NEXT: cmpw (%rcx), %si # encoding: [0x66,0x3b,0x31]
+; ZU-NEXT: jl .LBB16_3 # encoding: [0x7c,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB16_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
+; ZU-NEXT: .LBB16_3: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
entry:
%d = load i16, ptr %ptr
%cmp = icmp sgt i16 %a, %c
@@ -748,6 +1028,23 @@ define void @ccmp32rm_cf(i32 noundef %a, i32 noundef %b, i32 noundef %c, ptr %pt
; NDD-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
; NDD-NEXT: .LBB17_1: # %if.end
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: ccmp32rm_cf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: cmpl %edx, %edi # encoding: [0x39,0xd7]
+; ZU-NEXT: jle .LBB17_3 # encoding: [0x7e,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB17_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.1: # %entry
+; ZU-NEXT: cmpl (%rcx), %esi # encoding: [0x3b,0x31]
+; ZU-NEXT: jbe .LBB17_3 # encoding: [0x76,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB17_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
+; ZU-NEXT: .LBB17_3: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
entry:
%d = load i32, ptr %ptr
%cmp = icmp sle i32 %a, %c
@@ -791,6 +1088,23 @@ define void @ccmp64rm_sf(i64 noundef %a, i64 noundef %b, i64 noundef %c, ptr %pt
; NDD-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
; NDD-NEXT: .LBB18_1: # %if.end
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: ccmp64rm_sf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: cmpq %rdx, %rdi # encoding: [0x48,0x39,0xd7]
+; ZU-NEXT: jg .LBB18_3 # encoding: [0x7f,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB18_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.1: # %entry
+; ZU-NEXT: cmpq (%rcx), %rsi # encoding: [0x48,0x3b,0x31]
+; ZU-NEXT: jl .LBB18_3 # encoding: [0x7c,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB18_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
+; ZU-NEXT: .LBB18_3: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
entry:
%d = load i64, ptr %ptr
%cmp = icmp sgt i64 %a, %c
@@ -834,6 +1148,23 @@ define void @ccmp8mr_zf(i8 noundef %a, i8 noundef %c, ptr %ptr) {
; NDD-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
; NDD-NEXT: .LBB19_1: # %if.end
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: ccmp8mr_zf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: cmpb %sil, %dil # encoding: [0x40,0x38,0xf7]
+; ZU-NEXT: jl .LBB19_3 # encoding: [0x7c,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB19_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.1: # %entry
+; ZU-NEXT: cmpb %sil, (%rdx) # encoding: [0x40,0x38,0x32]
+; ZU-NEXT: je .LBB19_3 # encoding: [0x74,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB19_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
+; ZU-NEXT: .LBB19_3: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
entry:
%b = load i8, ptr %ptr
%cmp = icmp slt i8 %a, %c
@@ -877,6 +1208,23 @@ define void @ccmp16mr_sf(i16 noundef %a, i16 noundef %c, ptr %ptr) {
; NDD-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
; NDD-NEXT: .LBB20_1: # %if.end
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: ccmp16mr_sf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: cmpw %si, %di # encoding: [0x66,0x39,0xf7]
+; ZU-NEXT: jg .LBB20_3 # encoding: [0x7f,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB20_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.1: # %entry
+; ZU-NEXT: cmpw %si, (%rdx) # encoding: [0x66,0x39,0x32]
+; ZU-NEXT: jl .LBB20_3 # encoding: [0x7c,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB20_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
+; ZU-NEXT: .LBB20_3: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
entry:
%b = load i16, ptr %ptr
%cmp = icmp sgt i16 %a, %c
@@ -920,6 +1268,23 @@ define void @ccmp32mr_cf(i32 noundef %a, i32 noundef %c, ptr %ptr) {
; NDD-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
; NDD-NEXT: .LBB21_1: # %if.end
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: ccmp32mr_cf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: cmpl %esi, %edi # encoding: [0x39,0xf7]
+; ZU-NEXT: jge .LBB21_3 # encoding: [0x7d,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB21_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.1: # %entry
+; ZU-NEXT: cmpl %esi, (%rdx) # encoding: [0x39,0x32]
+; ZU-NEXT: jbe .LBB21_3 # encoding: [0x76,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB21_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
+; ZU-NEXT: .LBB21_3: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
entry:
%b = load i32, ptr %ptr
%cmp = icmp sge i32 %a, %c
@@ -963,6 +1328,23 @@ define void @ccmp64mr_sf(i64 noundef %a, i64 noundef %c, ptr %ptr) {
; NDD-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
; NDD-NEXT: .LBB22_1: # %if.end
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: ccmp64mr_sf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: cmpq %rsi, %rdi # encoding: [0x48,0x39,0xf7]
+; ZU-NEXT: jg .LBB22_3 # encoding: [0x7f,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB22_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.1: # %entry
+; ZU-NEXT: cmpq %rsi, (%rdx) # encoding: [0x48,0x39,0x32]
+; ZU-NEXT: jl .LBB22_3 # encoding: [0x7c,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB22_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
+; ZU-NEXT: .LBB22_3: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
entry:
%b = load i64, ptr %ptr
%cmp = icmp sgt i64 %a, %c
@@ -1006,6 +1388,23 @@ define void @ccmp8mi_zf(i8 noundef %a, i8 noundef %c, ptr %ptr) {
; NDD-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
; NDD-NEXT: .LBB23_1: # %if.end
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: ccmp8mi_zf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: cmpb %sil, %dil # encoding: [0x40,0x38,0xf7]
+; ZU-NEXT: je .LBB23_3 # encoding: [0x74,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB23_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.1: # %entry
+; ZU-NEXT: cmpb $123, (%rdx) # encoding: [0x80,0x3a,0x7b]
+; ZU-NEXT: je .LBB23_3 # encoding: [0x74,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB23_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
+; ZU-NEXT: .LBB23_3: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
entry:
%b = load i8, ptr %ptr
%cmp = icmp eq i8 %a, %c
@@ -1051,6 +1450,25 @@ define void @ccmp16mi_zf(i16 noundef %a, i16 noundef %c, ptr %ptr) {
; NDD-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
; NDD-NEXT: .LBB24_1: # %if.end
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: ccmp16mi_zf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: cmpw %si, %di # encoding: [0x66,0x39,0xf7]
+; ZU-NEXT: jg .LBB24_3 # encoding: [0x7f,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB24_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.1: # %entry
+; ZU-NEXT: movswl (%rdx), %eax # encoding: [0x0f,0xbf,0x02]
+; ZU-NEXT: cmpl $1233, %eax # encoding: [0x3d,0xd1,0x04,0x00,0x00]
+; ZU-NEXT: # imm = 0x4D1
+; ZU-NEXT: jle .LBB24_3 # encoding: [0x7e,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB24_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
+; ZU-NEXT: .LBB24_3: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
entry:
%b = load i16, ptr %ptr
%cmp = icmp sgt i16 %a, %c
@@ -1096,6 +1514,24 @@ define void @ccmp32mi_cf(i32 noundef %a, i32 noundef %c, ptr %ptr) {
; NDD-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
; NDD-NEXT: .LBB25_1: # %if.end
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: ccmp32mi_cf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: cmpl %esi, %edi # encoding: [0x39,0xf7]
+; ZU-NEXT: je .LBB25_3 # encoding: [0x74,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB25_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.1: # %entry
+; ZU-NEXT: cmpl $123456, (%rdx) # encoding: [0x81,0x3a,0x40,0xe2,0x01,0x00]
+; ZU-NEXT: # imm = 0x1E240
+; ZU-NEXT: jbe .LBB25_3 # encoding: [0x76,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB25_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
+; ZU-NEXT: .LBB25_3: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
entry:
%b = load i32, ptr %ptr
%cmp = icmp eq i32 %a, %c
@@ -1141,6 +1577,24 @@ define void @ccmp64mi32_zf(i64 noundef %a, i64 noundef %c, ptr %ptr) {
; NDD-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
; NDD-NEXT: .LBB26_1: # %if.end
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: ccmp64mi32_zf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: cmpq %rsi, %rdi # encoding: [0x48,0x39,0xf7]
+; ZU-NEXT: jg .LBB26_3 # encoding: [0x7f,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB26_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.1: # %entry
+; ZU-NEXT: cmpq $123455, (%rdx) # encoding: [0x48,0x81,0x3a,0x3f,0xe2,0x01,0x00]
+; ZU-NEXT: # imm = 0x1E23F
+; ZU-NEXT: jle .LBB26_3 # encoding: [0x7e,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB26_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
+; ZU-NEXT: .LBB26_3: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
entry:
%b = load i64, ptr %ptr
%cmp = icmp sgt i64 %a, %c
@@ -1186,6 +1640,26 @@ define void @ccmp_continous(i32 noundef %a, i32 noundef %b, i32 noundef %c) {
; NDD-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
; NDD-NEXT: .LBB27_1: # %if.end
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: ccmp_continous:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: testl %edi, %edi # encoding: [0x85,0xff]
+; ZU-NEXT: setzug %al # encoding: [0x62,0xf4,0x7f,0x18,0x4f,0xc0]
+; ZU-NEXT: cmpl $2, %esi # encoding: [0x83,0xfe,0x02]
+; ZU-NEXT: setzuge %cl # encoding: [0x62,0xf4,0x7f,0x18,0x4d,0xc1]
+; ZU-NEXT: orb %al, %cl # encoding: [0x08,0xc1]
+; ZU-NEXT: cmpl $3, %edx # encoding: [0x83,0xfa,0x03]
+; ZU-NEXT: setzuge %al # encoding: [0x62,0xf4,0x7f,0x18,0x4d,0xc0]
+; ZU-NEXT: orb %cl, %al # encoding: [0x08,0xc8]
+; ZU-NEXT: jne .LBB27_1 # encoding: [0x75,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB27_1-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
+; ZU-NEXT: .LBB27_1: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%cmp = icmp slt i32 %a, 1
%cmp1 = icmp slt i32 %b, 2
@@ -1215,9 +1689,19 @@ define i32 @ccmp_nobranch(i32 noundef %a, i32 noundef %b) {
; NDD: # %bb.0: # %entry
; NDD-NEXT: testl %edi, %edi # encoding: [0x85,0xff]
; NDD-NEXT: ccmplel {dfv=} $2, %esi # encoding: [0x62,0xf4,0x04,0x0e,0x83,0xfe,0x02]
-; NDD-NEXT: setzuge %al # encoding: [0x62,0xf4,0x7f,0x18,0x4d,0xc0]
+; NDD-NEXT: setge %al # encoding: [0x0f,0x9d,0xc0]
; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: ccmp_nobranch:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: testl %edi, %edi # encoding: [0x85,0xff]
+; ZU-NEXT: setzug %al # encoding: [0x62,0xf4,0x7f,0x18,0x4f,0xc0]
+; ZU-NEXT: cmpl $2, %esi # encoding: [0x83,0xfe,0x02]
+; ZU-NEXT: setzuge %cl # encoding: [0x62,0xf4,0x7f,0x18,0x4d,0xc1]
+; ZU-NEXT: orb %al, %cl # encoding: [0x08,0xc1]
+; ZU-NEXT: movzbl %cl, %eax # encoding: [0x0f,0xb6,0xc1]
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%cmp = icmp sgt i32 %a, 0
%cmp1 = icmp sgt i32 %b, 1
@@ -1241,9 +1725,22 @@ define i32 @ccmp_continous_nobranch(i32 noundef %a, i32 noundef %b, i32 noundef
; NDD-NEXT: cmpl $2, %edi # encoding: [0x83,0xff,0x02]
; NDD-NEXT: ccmpll {dfv=sf} $2, %esi # encoding: [0x62,0xf4,0x24,0x0c,0x83,0xfe,0x02]
; NDD-NEXT: ccmpll {dfv=sf} $4, %edx # encoding: [0x62,0xf4,0x24,0x0c,0x83,0xfa,0x04]
-; NDD-NEXT: setzuge %al # encoding: [0x62,0xf4,0x7f,0x18,0x4d,0xc0]
+; NDD-NEXT: setge %al # encoding: [0x0f,0x9d,0xc0]
; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: ccmp_continous_nobranch:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: cmpl $2, %edi # encoding: [0x83,0xff,0x02]
+; ZU-NEXT: setzuge %al # encoding: [0x62,0xf4,0x7f,0x18,0x4d,0xc0]
+; ZU-NEXT: cmpl $2, %esi # encoding: [0x83,0xfe,0x02]
+; ZU-NEXT: setzul %cl # encoding: [0x62,0xf4,0x7f,0x18,0x4c,0xc1]
+; ZU-NEXT: cmpl $4, %edx # encoding: [0x83,0xfa,0x04]
+; ZU-NEXT: setzuge %dl # encoding: [0x62,0xf4,0x7f,0x18,0x4d,0xc2]
+; ZU-NEXT: orb %al, %cl # encoding: [0x08,0xc1]
+; ZU-NEXT: andb %dl, %cl # encoding: [0x20,0xd1]
+; ZU-NEXT: movzbl %cl, %eax # encoding: [0x0f,0xb6,0xc1]
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%cmp = icmp sgt i32 %a, 1
%cmp1 = icmp slt i32 %b, 2
@@ -1286,6 +1783,25 @@ define void @ccmp64ri64(i64 noundef %a, i64 noundef %b, i64 noundef %c) {
; NDD-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
; NDD-NEXT: .LBB30_1: # %if.end
; NDD-NEXT: retq # encoding: [0xc3]
+;
+; ZU-LABEL: ccmp64ri64:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: cmpq %rdx, %rdi # encoding: [0x48,0x39,0xd7]
+; ZU-NEXT: setzube %al # encoding: [0x62,0xf4,0x7f,0x18,0x46,0xc0]
+; ZU-NEXT: movabsq $9992147483646, %rcx # encoding: [0x48,0xb9,0xfe,0xbb,0x66,0x7a,0x16,0x09,0x00,0x00]
+; ZU-NEXT: # imm = 0x9167A66BBFE
+; ZU-NEXT: cmpq %rcx, %rsi # encoding: [0x48,0x39,0xce]
+; ZU-NEXT: setzug %cl # encoding: [0x62,0xf4,0x7f,0x18,0x4f,0xc1]
+; ZU-NEXT: testb %cl, %al # encoding: [0x84,0xc8]
+; ZU-NEXT: jne .LBB30_1 # encoding: [0x75,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB30_1-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
+; ZU-NEXT: .LBB30_1: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%cmp = icmp ugt i64 %a, %c
%cmp1 = icmp slt i64 %b, 9992147483647
diff --git a/llvm/test/CodeGen/X86/apx/ctest.ll b/llvm/test/CodeGen/X86/apx/ctest.ll
index 7477b687c427b..431f454ec701f 100644
--- a/llvm/test/CodeGen/X86/apx/ctest.ll
+++ b/llvm/test/CodeGen/X86/apx/ctest.ll
@@ -1,6 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ccmp,+nf -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ccmp,+ndd,+nf -verify-machineinstrs | FileCheck %s --check-prefix=NDD
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+zu -verify-machineinstrs --show-mc-encoding | FileCheck %s --check-prefix=ZU
define void @ctest8rr_zf(i8 noundef %a, i8 noundef %b) {
; CHECK-LABEL: ctest8rr_zf:
@@ -24,6 +25,23 @@ define void @ctest8rr_zf(i8 noundef %a, i8 noundef %b) {
; NDD-NEXT: jmp foo # TAILCALL
; NDD-NEXT: .LBB0_1: # %if.end
; NDD-NEXT: retq
+;
+; ZU-LABEL: ctest8rr_zf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: testb %dil, %dil # encoding: [0x40,0x84,0xff]
+; ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; ZU-NEXT: testb %sil, %sil # encoding: [0x40,0x84,0xf6]
+; ZU-NEXT: setzune %cl # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc1]
+; ZU-NEXT: testb %cl, %al # encoding: [0x84,0xc8]
+; ZU-NEXT: jne .LBB0_1 # encoding: [0x75,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB0_1-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
+; ZU-NEXT: .LBB0_1: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%cmp = icmp eq i8 %a, 0
%cmp1 = icmp eq i8 %b, 0
@@ -62,6 +80,22 @@ define i8 @ctest8rr_zf_double(i8 %a, double %b, i8* nocapture %c) {
; NDD-NEXT: .LBB1_2: # %if.end
; NDD-NEXT: xorl %eax, %eax
; NDD-NEXT: retq
+;
+; ZU-LABEL: ctest8rr_zf_double:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: testb %dil, %dil # encoding: [0x40,0x84,0xff]
+; ZU-NEXT: je .LBB1_3 # encoding: [0x74,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB1_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.1: # %entry
+; ZU-NEXT: xorpd %xmm1, %xmm1 # encoding: [0x66,0x0f,0x57,0xc9]
+; ZU-NEXT: ucomisd %xmm1, %xmm0 # encoding: [0x66,0x0f,0x2e,0xc1]
+; ZU-NEXT: jne .LBB1_3 # encoding: [0x75,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB1_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.then
+; ZU-NEXT: movb %dil, (%rsi) # encoding: [0x40,0x88,0x3e]
+; ZU-NEXT: .LBB1_3: # %if.end
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%tobool = icmp ne i8 %a, 0
%cmp = fcmp ueq double %b, 0.0
@@ -95,9 +129,9 @@ define i8 @ctest8rr_zf_double_p(i8 %a, double %b, i8* nocapture %c) {
; NDD-LABEL: ctest8rr_zf_double_p:
; NDD: # %bb.0: # %entry
; NDD-NEXT: testb %dil, %dil
-; NDD-NEXT: setzune %al
+; NDD-NEXT: setne %al
; NDD-NEXT: ucomisd %xmm0, %xmm0
-; NDD-NEXT: setzup %cl
+; NDD-NEXT: setp %cl
; NDD-NEXT: andb %cl, %al
; NDD-NEXT: cmpb $1, %al
; NDD-NEXT: jne .LBB2_2
@@ -106,6 +140,21 @@ define i8 @ctest8rr_zf_double_p(i8 %a, double %b, i8* nocapture %c) {
; NDD-NEXT: .LBB2_2: # %if.end
; NDD-NEXT: xorl %eax, %eax
; NDD-NEXT: retq
+;
+; ZU-LABEL: ctest8rr_zf_double_p:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: testb %dil, %dil # encoding: [0x40,0x84,0xff]
+; ZU-NEXT: je .LBB2_3 # encoding: [0x74,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB2_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.1: # %entry
+; ZU-NEXT: ucomisd %xmm0, %xmm0 # encoding: [0x66,0x0f,0x2e,0xc0]
+; ZU-NEXT: jnp .LBB2_3 # encoding: [0x7b,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB2_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.then
+; ZU-NEXT: movb %dil, (%rsi) # encoding: [0x40,0x88,0x3e]
+; ZU-NEXT: .LBB2_3: # %if.end
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%tobool = icmp ne i8 %a, 0
%cmp = fcmp uno double %b, 0.0
@@ -139,9 +188,9 @@ define i8 @ctest8rr_zf_double_np(i8 %a, double %b, i8* nocapture %c) {
; NDD-LABEL: ctest8rr_zf_double_np:
; NDD: # %bb.0: # %entry
; NDD-NEXT: testb %dil, %dil
-; NDD-NEXT: setzune %al
+; NDD-NEXT: setne %al
; NDD-NEXT: ucomisd %xmm0, %xmm0
-; NDD-NEXT: setzunp %cl
+; NDD-NEXT: setnp %cl
; NDD-NEXT: andb %cl, %al
; NDD-NEXT: cmpb $1, %al
; NDD-NEXT: jne .LBB3_2
@@ -150,6 +199,21 @@ define i8 @ctest8rr_zf_double_np(i8 %a, double %b, i8* nocapture %c) {
; NDD-NEXT: .LBB3_2: # %if.end
; NDD-NEXT: xorl %eax, %eax
; NDD-NEXT: retq
+;
+; ZU-LABEL: ctest8rr_zf_double_np:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: testb %dil, %dil # encoding: [0x40,0x84,0xff]
+; ZU-NEXT: je .LBB3_3 # encoding: [0x74,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB3_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.1: # %entry
+; ZU-NEXT: ucomisd %xmm0, %xmm0 # encoding: [0x66,0x0f,0x2e,0xc0]
+; ZU-NEXT: jp .LBB3_3 # encoding: [0x7a,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB3_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.then
+; ZU-NEXT: movb %dil, (%rsi) # encoding: [0x40,0x88,0x3e]
+; ZU-NEXT: .LBB3_3: # %if.end
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%tobool = icmp ne i8 %a, 0
%cmp = fcmp ord double %b, 0.0
@@ -186,6 +250,23 @@ define void @ctest8rr_sf(i8 noundef %a, i8 noundef %b) {
; NDD-NEXT: jmp foo # TAILCALL
; NDD-NEXT: .LBB4_1: # %if.end
; NDD-NEXT: retq
+;
+; ZU-LABEL: ctest8rr_sf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: testb %dil, %dil # encoding: [0x40,0x84,0xff]
+; ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; ZU-NEXT: testb %sil, %sil # encoding: [0x40,0x84,0xf6]
+; ZU-NEXT: setzus %cl # encoding: [0x62,0xf4,0x7f,0x18,0x48,0xc1]
+; ZU-NEXT: orb %al, %cl # encoding: [0x08,0xc1]
+; ZU-NEXT: jne .LBB4_1 # encoding: [0x75,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB4_1-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
+; ZU-NEXT: .LBB4_1: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%cmp = icmp ule i8 %a, 0
%tobool = icmp sge i8 %b, 0
@@ -222,6 +303,22 @@ define i8 @ctest8rr_sf_2(i8 %a, i8 %b, i8* nocapture %c) {
; NDD-NEXT: .LBB5_2: # %if.end
; NDD-NEXT: xorl %eax, %eax
; NDD-NEXT: retq
+;
+; ZU-LABEL: ctest8rr_sf_2:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: testb %dil, %dil # encoding: [0x40,0x84,0xff]
+; ZU-NEXT: setzug %al # encoding: [0x62,0xf4,0x7f,0x18,0x4f,0xc0]
+; ZU-NEXT: testb %sil, %sil # encoding: [0x40,0x84,0xf6]
+; ZU-NEXT: setzus %cl # encoding: [0x62,0xf4,0x7f,0x18,0x48,0xc1]
+; ZU-NEXT: orb %al, %cl # encoding: [0x08,0xc1]
+; ZU-NEXT: cmpb $1, %cl # encoding: [0x80,0xf9,0x01]
+; ZU-NEXT: jne .LBB5_2 # encoding: [0x75,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB5_2-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.1: # %if.then
+; ZU-NEXT: movb %dil, (%rdx) # encoding: [0x40,0x88,0x3a]
+; ZU-NEXT: .LBB5_2: # %if.end
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%tobool = icmp sgt i8 %a, 0
%cmp = icmp slt i8 %b, 0
@@ -258,6 +355,22 @@ define i8 @ctest8rr_none(i8 %a, i8 %b, i8* nocapture %c) {
; NDD-NEXT: .LBB6_2: # %if.end
; NDD-NEXT: xorl %eax, %eax
; NDD-NEXT: retq
+;
+; ZU-LABEL: ctest8rr_none:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: testb %dil, %dil # encoding: [0x40,0x84,0xff]
+; ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; ZU-NEXT: testb %sil, %sil # encoding: [0x40,0x84,0xf6]
+; ZU-NEXT: setzue %cl # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc1]
+; ZU-NEXT: andb %al, %cl # encoding: [0x20,0xc1]
+; ZU-NEXT: cmpb $1, %cl # encoding: [0x80,0xf9,0x01]
+; ZU-NEXT: jne .LBB6_2 # encoding: [0x75,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB6_2-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.1: # %if.then
+; ZU-NEXT: movb %dil, (%rdx) # encoding: [0x40,0x88,0x3a]
+; ZU-NEXT: .LBB6_2: # %if.end
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%tobool = icmp ne i8 %a, 0
%cmp = icmp eq i8 %b, 0
@@ -294,6 +407,23 @@ define void @ctest16rr_sf(i16 noundef %a, i16 noundef %b) {
; NDD-NEXT: jmp foo # TAILCALL
; NDD-NEXT: .LBB7_1: # %if.end
; NDD-NEXT: retq
+;
+; ZU-LABEL: ctest16rr_sf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: testw %di, %di # encoding: [0x66,0x85,0xff]
+; ZU-NEXT: setzule %al # encoding: [0x62,0xf4,0x7f,0x18,0x4e,0xc0]
+; ZU-NEXT: testw %si, %si # encoding: [0x66,0x85,0xf6]
+; ZU-NEXT: setzuns %cl # encoding: [0x62,0xf4,0x7f,0x18,0x49,0xc1]
+; ZU-NEXT: testb %cl, %al # encoding: [0x84,0xc8]
+; ZU-NEXT: jne .LBB7_1 # encoding: [0x75,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB7_1-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
+; ZU-NEXT: .LBB7_1: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%cmp = icmp sgt i16 %a, 0
%cmp1 = icmp slt i16 %b, 0
@@ -330,6 +460,23 @@ define void @ctest32rr_zf(i32 noundef %a, i32 noundef %b) {
; NDD-NEXT: jmp foo # TAILCALL
; NDD-NEXT: .LBB8_1: # %if.end
; NDD-NEXT: retq
+;
+; ZU-LABEL: ctest32rr_zf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: testl %edi, %edi # encoding: [0x85,0xff]
+; ZU-NEXT: setzus %al # encoding: [0x62,0xf4,0x7f,0x18,0x48,0xc0]
+; ZU-NEXT: testl %esi, %esi # encoding: [0x85,0xf6]
+; ZU-NEXT: setzune %cl # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc1]
+; ZU-NEXT: testb %cl, %al # encoding: [0x84,0xc8]
+; ZU-NEXT: jne .LBB8_1 # encoding: [0x75,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB8_1-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
+; ZU-NEXT: .LBB8_1: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%cmp = icmp sge i32 %a, 0
%cmp1 = icmp eq i32 %b, 0
@@ -366,6 +513,23 @@ define void @ctest8ri_zf(i8 noundef %a, i8 noundef %b) {
; NDD-NEXT: jmp foo # TAILCALL
; NDD-NEXT: .LBB9_1: # %if.end
; NDD-NEXT: retq
+;
+; ZU-LABEL: ctest8ri_zf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: testb %dil, %dil # encoding: [0x40,0x84,0xff]
+; ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; ZU-NEXT: testb $123, %sil # encoding: [0x40,0xf6,0xc6,0x7b]
+; ZU-NEXT: setzune %cl # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc1]
+; ZU-NEXT: testb %cl, %al # encoding: [0x84,0xc8]
+; ZU-NEXT: jne .LBB9_1 # encoding: [0x75,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB9_1-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
+; ZU-NEXT: .LBB9_1: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%cmp = icmp eq i8 %a, 0
%and = and i8 %b, 123
@@ -404,6 +568,24 @@ define void @ctest16ri_zf(i16 noundef %a, i16 noundef %b) {
; NDD-NEXT: jmp foo # TAILCALL
; NDD-NEXT: .LBB10_1: # %if.end
; NDD-NEXT: retq
+;
+; ZU-LABEL: ctest16ri_zf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: testw %di, %di # encoding: [0x66,0x85,0xff]
+; ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; ZU-NEXT: testl $1234, %esi # encoding: [0xf7,0xc6,0xd2,0x04,0x00,0x00]
+; ZU-NEXT: # imm = 0x4D2
+; ZU-NEXT: setzune %cl # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc1]
+; ZU-NEXT: testb %cl, %al # encoding: [0x84,0xc8]
+; ZU-NEXT: jne .LBB10_1 # encoding: [0x75,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB10_1-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
+; ZU-NEXT: .LBB10_1: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%cmp = icmp eq i16 %a, 0
%and = and i16 %b, 1234
@@ -441,6 +623,24 @@ define void @ctest32ri_zf(i32 noundef %a, i32 noundef %b) {
; NDD-NEXT: jmp foo # TAILCALL
; NDD-NEXT: .LBB11_1: # %if.end
; NDD-NEXT: retq
+;
+; ZU-LABEL: ctest32ri_zf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: testl %edi, %edi # encoding: [0x85,0xff]
+; ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; ZU-NEXT: testl $12345, %esi # encoding: [0xf7,0xc6,0x39,0x30,0x00,0x00]
+; ZU-NEXT: # imm = 0x3039
+; ZU-NEXT: setzune %cl # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc1]
+; ZU-NEXT: testb %cl, %al # encoding: [0x84,0xc8]
+; ZU-NEXT: jne .LBB11_1 # encoding: [0x75,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB11_1-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
+; ZU-NEXT: .LBB11_1: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%cmp = icmp eq i32 %a, 0
%and = and i32 %b, 12345
@@ -478,6 +678,24 @@ define void @ctest64ri32_zf(i64 noundef %a, i64 noundef %b) {
; NDD-NEXT: jmp foo # TAILCALL
; NDD-NEXT: .LBB12_1: # %if.end
; NDD-NEXT: retq
+;
+; ZU-LABEL: ctest64ri32_zf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff]
+; ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; ZU-NEXT: testl $123456, %esi # encoding: [0xf7,0xc6,0x40,0xe2,0x01,0x00]
+; ZU-NEXT: # imm = 0x1E240
+; ZU-NEXT: setzune %cl # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc1]
+; ZU-NEXT: testb %cl, %al # encoding: [0x84,0xc8]
+; ZU-NEXT: jne .LBB12_1 # encoding: [0x75,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB12_1-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
+; ZU-NEXT: .LBB12_1: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%cmp = icmp eq i64 %a, 0
%and = and i64 %b, 123456
@@ -517,6 +735,23 @@ define void @ctest8mr_zf(i8 noundef %a, ptr %ptr) {
; NDD-NEXT: jmp foo # TAILCALL
; NDD-NEXT: .LBB13_1: # %if.end
; NDD-NEXT: retq
+;
+; ZU-LABEL: ctest8mr_zf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: testb %dil, %dil # encoding: [0x40,0x84,0xff]
+; ZU-NEXT: je .LBB13_3 # encoding: [0x74,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB13_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.1: # %entry
+; ZU-NEXT: cmpb $0, (%rsi) # encoding: [0x80,0x3e,0x00]
+; ZU-NEXT: je .LBB13_3 # encoding: [0x74,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB13_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
+; ZU-NEXT: .LBB13_3: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
entry:
%b = load i8, ptr %ptr
%cmp = icmp eq i8 %a, 0
@@ -556,6 +791,23 @@ define void @ctest16mr_zf(i16 noundef %a, ptr %ptr) {
; NDD-NEXT: jmp foo # TAILCALL
; NDD-NEXT: .LBB14_1: # %if.end
; NDD-NEXT: retq
+;
+; ZU-LABEL: ctest16mr_zf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: testw %di, %di # encoding: [0x66,0x85,0xff]
+; ZU-NEXT: je .LBB14_3 # encoding: [0x74,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB14_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.1: # %entry
+; ZU-NEXT: cmpw $0, (%rsi) # encoding: [0x66,0x83,0x3e,0x00]
+; ZU-NEXT: je .LBB14_3 # encoding: [0x74,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB14_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
+; ZU-NEXT: .LBB14_3: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
entry:
%b = load i16, ptr %ptr
%cmp = icmp eq i16 %a, 0
@@ -595,6 +847,23 @@ define void @ctest32mr_cf(i32 noundef %a, ptr %ptr) {
; NDD-NEXT: jmp foo # TAILCALL
; NDD-NEXT: .LBB15_1: # %if.end
; NDD-NEXT: retq
+;
+; ZU-LABEL: ctest32mr_cf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: testl %edi, %edi # encoding: [0x85,0xff]
+; ZU-NEXT: je .LBB15_3 # encoding: [0x74,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB15_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.1: # %entry
+; ZU-NEXT: cmpl $0, (%rsi) # encoding: [0x83,0x3e,0x00]
+; ZU-NEXT: je .LBB15_3 # encoding: [0x74,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB15_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
+; ZU-NEXT: .LBB15_3: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
entry:
%b = load i32, ptr %ptr
%cmp = icmp eq i32 %a, 0
@@ -634,6 +903,23 @@ define void @ctest64mr_zf(i64 noundef %a, ptr %ptr) {
; NDD-NEXT: jmp foo # TAILCALL
; NDD-NEXT: .LBB16_1: # %if.end
; NDD-NEXT: retq
+;
+; ZU-LABEL: ctest64mr_zf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff]
+; ZU-NEXT: je .LBB16_3 # encoding: [0x74,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB16_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.1: # %entry
+; ZU-NEXT: cmpq $0, (%rsi) # encoding: [0x48,0x83,0x3e,0x00]
+; ZU-NEXT: je .LBB16_3 # encoding: [0x74,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB16_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
+; ZU-NEXT: .LBB16_3: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
entry:
%b = load i64, ptr %ptr
%cmp = icmp eq i64 %a, 0
@@ -671,6 +957,24 @@ define void @ctest8mi_zf(i8 noundef %a, ptr %ptr) {
; NDD-NEXT: jmp foo # TAILCALL
; NDD-NEXT: .LBB17_1: # %if.end
; NDD-NEXT: retq
+;
+; ZU-LABEL: ctest8mi_zf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: testb %dil, %dil # encoding: [0x40,0x84,0xff]
+; ZU-NEXT: je .LBB17_3 # encoding: [0x74,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB17_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.1: # %entry
+; ZU-NEXT: movzbl (%rsi), %eax # encoding: [0x0f,0xb6,0x06]
+; ZU-NEXT: andb $123, %al # encoding: [0x24,0x7b]
+; ZU-NEXT: je .LBB17_3 # encoding: [0x74,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB17_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
+; ZU-NEXT: .LBB17_3: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
entry:
%b = load i8, ptr %ptr
%cmp = icmp eq i8 %a, 0
@@ -711,6 +1015,25 @@ define void @ctest16mi_zf(i16 noundef %a, ptr %ptr) {
; NDD-NEXT: jmp foo # TAILCALL
; NDD-NEXT: .LBB18_1: # %if.end
; NDD-NEXT: retq
+;
+; ZU-LABEL: ctest16mi_zf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: testw %di, %di # encoding: [0x66,0x85,0xff]
+; ZU-NEXT: je .LBB18_3 # encoding: [0x74,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB18_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.1: # %entry
+; ZU-NEXT: movzwl (%rsi), %eax # encoding: [0x0f,0xb7,0x06]
+; ZU-NEXT: andl $1234, %eax # encoding: [0x25,0xd2,0x04,0x00,0x00]
+; ZU-NEXT: # imm = 0x4D2
+; ZU-NEXT: je .LBB18_3 # encoding: [0x74,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB18_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
+; ZU-NEXT: .LBB18_3: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
entry:
%b = load i16, ptr %ptr
%cmp = icmp eq i16 %a, 0
@@ -751,6 +1074,25 @@ define void @ctest32mi_zf(i32 noundef %a, ptr %ptr) {
; NDD-NEXT: jmp foo # TAILCALL
; NDD-NEXT: .LBB19_1: # %if.end
; NDD-NEXT: retq
+;
+; ZU-LABEL: ctest32mi_zf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: testl %edi, %edi # encoding: [0x85,0xff]
+; ZU-NEXT: je .LBB19_3 # encoding: [0x74,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB19_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.1: # %entry
+; ZU-NEXT: movl $12345, %eax # encoding: [0xb8,0x39,0x30,0x00,0x00]
+; ZU-NEXT: # imm = 0x3039
+; ZU-NEXT: andl (%rsi), %eax # encoding: [0x23,0x06]
+; ZU-NEXT: je .LBB19_3 # encoding: [0x74,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB19_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
+; ZU-NEXT: .LBB19_3: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
entry:
%b = load i32, ptr %ptr
%cmp = icmp eq i32 %a, 0
@@ -789,6 +1131,25 @@ define void @ctest64mi32_zf(i64 noundef %a, ptr %ptr) {
; NDD-NEXT: jmp foo # TAILCALL
; NDD-NEXT: .LBB20_1: # %if.end
; NDD-NEXT: retq
+;
+; ZU-LABEL: ctest64mi32_zf:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff]
+; ZU-NEXT: je .LBB20_3 # encoding: [0x74,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB20_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.1: # %entry
+; ZU-NEXT: movq (%rsi), %rax # encoding: [0x48,0x8b,0x06]
+; ZU-NEXT: andl $123456, %eax # encoding: [0x25,0x40,0xe2,0x01,0x00]
+; ZU-NEXT: # imm = 0x1E240
+; ZU-NEXT: je .LBB20_3 # encoding: [0x74,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB20_3-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
+; ZU-NEXT: .LBB20_3: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
entry:
%b = load i64, ptr %ptr
%cmp = icmp eq i64 %a, 0
@@ -829,6 +1190,26 @@ define void @ctest_continous(i32 noundef %a, i32 noundef %b, i32 noundef %c) {
; NDD-NEXT: jmp foo # TAILCALL
; NDD-NEXT: .LBB21_1: # %if.end
; NDD-NEXT: retq
+;
+; ZU-LABEL: ctest_continous:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: cmpl %esi, %edi # encoding: [0x39,0xf7]
+; ZU-NEXT: setzuge %al # encoding: [0x62,0xf4,0x7f,0x18,0x4d,0xc0]
+; ZU-NEXT: testl %esi, %esi # encoding: [0x85,0xf6]
+; ZU-NEXT: setzuns %cl # encoding: [0x62,0xf4,0x7f,0x18,0x49,0xc1]
+; ZU-NEXT: orb %al, %cl # encoding: [0x08,0xc1]
+; ZU-NEXT: testl %edx, %edx # encoding: [0x85,0xd2]
+; ZU-NEXT: setzuns %al # encoding: [0x62,0xf4,0x7f,0x18,0x49,0xc0]
+; ZU-NEXT: testb %al, %cl # encoding: [0x84,0xc1]
+; ZU-NEXT: jne .LBB21_1 # encoding: [0x75,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB21_1-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
+; ZU-NEXT: .LBB21_1: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%cmp = icmp slt i32 %a, %b
%cmp1 = icmp slt i32 %b, 0
@@ -858,9 +1239,19 @@ define i32 @ctest_nobranch(i32 noundef %a, i32 noundef %b) {
; NDD: # %bb.0: # %entry
; NDD-NEXT: testl %edi, %edi
; NDD-NEXT: ctestlel {dfv=} %esi, %esi
-; NDD-NEXT: setzug %al
+; NDD-NEXT: setg %al
; NDD-NEXT: movzbl %al, %eax
; NDD-NEXT: retq
+;
+; ZU-LABEL: ctest_nobranch:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: testl %edi, %edi # encoding: [0x85,0xff]
+; ZU-NEXT: setzug %al # encoding: [0x62,0xf4,0x7f,0x18,0x4f,0xc0]
+; ZU-NEXT: testl %esi, %esi # encoding: [0x85,0xf6]
+; ZU-NEXT: setzug %cl # encoding: [0x62,0xf4,0x7f,0x18,0x4f,0xc1]
+; ZU-NEXT: orb %al, %cl # encoding: [0x08,0xc1]
+; ZU-NEXT: movzbl %cl, %eax # encoding: [0x0f,0xb6,0xc1]
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%cmp = icmp sgt i32 %a, 0
%cmp1 = icmp sgt i32 %b, 0
@@ -884,9 +1275,22 @@ define i32 @ctest_continous_nobranch(i32 noundef %a, i32 noundef %b, i32 noundef
; NDD-NEXT: testl %edi, %edi
; NDD-NEXT: ctestlel {dfv=sf} %esi, %esi
; NDD-NEXT: ctestsl {dfv=zf} %edx, %edx
-; NDD-NEXT: setzug %al
+; NDD-NEXT: setg %al
; NDD-NEXT: movzbl %al, %eax
; NDD-NEXT: retq
+;
+; ZU-LABEL: ctest_continous_nobranch:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: testl %edi, %edi # encoding: [0x85,0xff]
+; ZU-NEXT: setzug %al # encoding: [0x62,0xf4,0x7f,0x18,0x4f,0xc0]
+; ZU-NEXT: testl %esi, %esi # encoding: [0x85,0xf6]
+; ZU-NEXT: setzus %cl # encoding: [0x62,0xf4,0x7f,0x18,0x48,0xc1]
+; ZU-NEXT: testl %edx, %edx # encoding: [0x85,0xd2]
+; ZU-NEXT: setzug %dl # encoding: [0x62,0xf4,0x7f,0x18,0x4f,0xc2]
+; ZU-NEXT: orb %al, %cl # encoding: [0x08,0xc1]
+; ZU-NEXT: andb %dl, %cl # encoding: [0x20,0xd1]
+; ZU-NEXT: movzbl %cl, %eax # encoding: [0x0f,0xb6,0xc1]
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%cmp = icmp sgt i32 %a, 0
%cmp1 = icmp slt i32 %b, 0
@@ -921,6 +1325,25 @@ define void @ctest64ri64(i64 noundef %a, i64 noundef %b) {
; NDD-NEXT: jmp foo # TAILCALL
; NDD-NEXT: .LBB24_1: # %if.end
; NDD-NEXT: retq
+;
+; ZU-LABEL: ctest64ri64:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff]
+; ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; ZU-NEXT: movabsq $9992147483647, %rcx # encoding: [0x48,0xb9,0xff,0xbb,0x66,0x7a,0x16,0x09,0x00,0x00]
+; ZU-NEXT: # imm = 0x9167A66BBFF
+; ZU-NEXT: testq %rcx, %rsi # encoding: [0x48,0x85,0xce]
+; ZU-NEXT: setzune %cl # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc1]
+; ZU-NEXT: testb %cl, %al # encoding: [0x84,0xc8]
+; ZU-NEXT: jne .LBB24_1 # encoding: [0x75,A]
+; ZU-NEXT: # fixup A - offset: 1, value: .LBB24_1-1, kind: FK_PCRel_1
+; ZU-NEXT: # %bb.2: # %if.then
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: jmp foo # TAILCALL
+; ZU-NEXT: # encoding: [0xeb,A]
+; ZU-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
+; ZU-NEXT: .LBB24_1: # %if.end
+; ZU-NEXT: retq # encoding: [0xc3]
entry:
%cmp = icmp eq i64 %a, 0
%and = and i64 %b, 9992147483647
@@ -962,13 +1385,33 @@ define void @cmp_srem(ptr %p, i32 %a, ptr %b) {
; NDD-NEXT: cltd
; NDD-NEXT: {nf} idivl %edi
; NDD-NEXT: ctestnel {dfv=} %edx, %edx
-; NDD-NEXT: setzue %al
+; NDD-NEXT: sete %al
; NDD-NEXT: cmpl $1, %esi
; NDD-NEXT: ccmpael {dfv=zf} $1, %edi
-; NDD-NEXT: setzue %dl
+; NDD-NEXT: sete %dl
; NDD-NEXT: orb %dl, %al
; NDD-NEXT: movb %al, (%rcx)
; NDD-NEXT: retq
+;
+; ZU-LABEL: cmp_srem:
+; ZU: # %bb.0: # %bb
+; ZU-NEXT: movq %rdx, %rcx # encoding: [0x48,0x89,0xd1]
+; ZU-NEXT: movl %esi, %eax # encoding: [0x89,0xf0]
+; ZU-NEXT: movl (%rdi), %esi # encoding: [0x8b,0x37]
+; ZU-NEXT: cmpl $1, %esi # encoding: [0x83,0xfe,0x01]
+; ZU-NEXT: setzue %dl # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc2]
+; ZU-NEXT: subl $1, %eax # encoding: [0x83,0xe8,0x01]
+; ZU-NEXT: setzub %dil # encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc7]
+; ZU-NEXT: setzune %r8b # encoding: [0x62,0xd4,0x7f,0x18,0x45,0xc0]
+; ZU-NEXT: orb %dl, %dil # encoding: [0x40,0x08,0xd7]
+; ZU-NEXT: cltd # encoding: [0x99]
+; ZU-NEXT: idivl %esi # encoding: [0xf7,0xfe]
+; ZU-NEXT: testl %edx, %edx # encoding: [0x85,0xd2]
+; ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; ZU-NEXT: andb %r8b, %al # encoding: [0x44,0x20,0xc0]
+; ZU-NEXT: orb %dil, %al # encoding: [0x40,0x08,0xf8]
+; ZU-NEXT: movb %al, (%rcx) # encoding: [0x88,0x01]
+; ZU-NEXT: retq # encoding: [0xc3]
bb:
%i = icmp eq i32 %a, 0
%i2 = load i32, ptr %p, align 4
diff --git a/llvm/test/CodeGen/X86/apx/flags-copy-lowering.mir b/llvm/test/CodeGen/X86/apx/flags-copy-lowering.mir
index 39d9f26fd5ae8..8395ac192cdaa 100644
--- a/llvm/test/CodeGen/X86/apx/flags-copy-lowering.mir
+++ b/llvm/test/CodeGen/X86/apx/flags-copy-lowering.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=x86_64 -run-pass x86-flags-copy-lowering -mattr=+ndd -verify-machineinstrs -o - %s | FileCheck --check-prefixes=CHECK,NDD %s
-# RUN: llc -mtriple=x86_64 -run-pass x86-flags-copy-lowering -mattr=+ndd,+zu -verify-machineinstrs -o - %s | FileCheck --check-prefix=NDD-ZU %s
-# RUN: llc -O0 -mtriple=x86_64 -run-pass x86-flags-copy-lowering -mattr=+ndd,+zu -verify-machineinstrs -o - %s | FileCheck --check-prefix=O0-NDD-ZU %s
+# RUN: llc -mtriple=x86_64 -run-pass x86-flags-copy-lowering -mattr=+zu -verify-machineinstrs -o - %s | FileCheck --check-prefix=ZU %s
+# RUN: llc -O0 -mtriple=x86_64 -run-pass x86-flags-copy-lowering -mattr=+zu -verify-machineinstrs -o - %s | FileCheck --check-prefix=O0-ZU %s
# RUN: llc -mtriple=x86_64 -run-pass x86-flags-copy-lowering -mattr=+ndd,+nf -verify-machineinstrs -o - %s | FileCheck --check-prefixes=CHECK,NDD-NF %s
# RUN: llc -mtriple=x86_64 -run-pass x86-flags-copy-lowering -mattr=+ndd,+nf -x86-enable-apx-for-relocation=true -verify-machineinstrs -o - %s | FileCheck --check-prefixes=CHECK,NDD-NF %s
@@ -28,33 +28,33 @@ body: |
; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[ADC64ri32_ND1]]
; CHECK-NEXT: RET 0
;
- ; NDD-ZU-LABEL: name: test_adc
- ; NDD-ZU: liveins: $rdi, $rsi
- ; NDD-ZU-NEXT: {{ $}}
- ; NDD-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; NDD-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; NDD-ZU-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
- ; NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
- ; NDD-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; NDD-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr]], 255, implicit-def $eflags
- ; NDD-ZU-NEXT: [[ADC64ri32_ND:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADD64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
- ; NDD-ZU-NEXT: [[ADC64ri32_ND1:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADC64ri32_ND]], 42, implicit-def $eflags, implicit $eflags
- ; NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[ADC64ri32_ND1]]
- ; NDD-ZU-NEXT: RET 0
+ ; ZU-LABEL: name: test_adc
+ ; ZU: liveins: $rdi, $rsi
+ ; ZU-NEXT: {{ $}}
+ ; ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; ZU-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; ZU-NEXT: dead [[ADD8ri:%[0-9]+]]:gr8 = ADD8ri [[SETZUCCr]], 255, implicit-def $eflags
+ ; ZU-NEXT: [[ADC64ri32_ND:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADD64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
+ ; ZU-NEXT: [[ADC64ri32_ND1:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADC64ri32_ND]], 42, implicit-def $eflags, implicit $eflags
+ ; ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[ADC64ri32_ND1]]
+ ; ZU-NEXT: RET 0
;
- ; O0-NDD-ZU-LABEL: name: test_adc
- ; O0-NDD-ZU: liveins: $rdi, $rsi
- ; O0-NDD-ZU-NEXT: {{ $}}
- ; O0-NDD-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; O0-NDD-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; O0-NDD-ZU-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
- ; O0-NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
- ; O0-NDD-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; O0-NDD-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr]], 255, implicit-def $eflags
- ; O0-NDD-ZU-NEXT: [[ADC64ri32_ND:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADD64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
- ; O0-NDD-ZU-NEXT: [[ADC64ri32_ND1:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADC64ri32_ND]], 42, implicit-def $eflags, implicit $eflags
- ; O0-NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[ADC64ri32_ND1]]
- ; O0-NDD-ZU-NEXT: RET 0
+ ; O0-ZU-LABEL: name: test_adc
+ ; O0-ZU: liveins: $rdi, $rsi
+ ; O0-ZU-NEXT: {{ $}}
+ ; O0-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; O0-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; O0-ZU-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; O0-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; O0-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; O0-ZU-NEXT: dead [[ADD8ri:%[0-9]+]]:gr8 = ADD8ri [[SETZUCCr]], 255, implicit-def $eflags
+ ; O0-ZU-NEXT: [[ADC64ri32_ND:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADD64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
+ ; O0-ZU-NEXT: [[ADC64ri32_ND1:%[0-9]+]]:gr64 = ADC64ri32_ND [[ADC64ri32_ND]], 42, implicit-def $eflags, implicit $eflags
+ ; O0-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[ADC64ri32_ND1]]
+ ; O0-ZU-NEXT: RET 0
%0:gr64 = COPY $rdi
%1:gr64 = COPY $rsi
%2:gr64 = ADD64rr_ND %0, %1, implicit-def $eflags
@@ -90,33 +90,33 @@ body: |
; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[SBB64ri32_ND1]]
; CHECK-NEXT: RET 0
;
- ; NDD-ZU-LABEL: name: test_sbb
- ; NDD-ZU: liveins: $rdi, $rsi
- ; NDD-ZU-NEXT: {{ $}}
- ; NDD-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; NDD-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; NDD-ZU-NEXT: [[SUB64rr_ND:%[0-9]+]]:gr64 = SUB64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
- ; NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
- ; NDD-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; NDD-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr]], 255, implicit-def $eflags
- ; NDD-ZU-NEXT: [[SBB64ri32_ND:%[0-9]+]]:gr64 = SBB64ri32_ND [[SUB64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
- ; NDD-ZU-NEXT: [[SBB64ri32_ND1:%[0-9]+]]:gr64 = SBB64ri32_ND [[SBB64ri32_ND]], 42, implicit-def dead $eflags, implicit killed $eflags
- ; NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[SBB64ri32_ND1]]
- ; NDD-ZU-NEXT: RET 0
+ ; ZU-LABEL: name: test_sbb
+ ; ZU: liveins: $rdi, $rsi
+ ; ZU-NEXT: {{ $}}
+ ; ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; ZU-NEXT: [[SUB64rr_ND:%[0-9]+]]:gr64 = SUB64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; ZU-NEXT: dead [[ADD8ri:%[0-9]+]]:gr8 = ADD8ri [[SETZUCCr]], 255, implicit-def $eflags
+ ; ZU-NEXT: [[SBB64ri32_ND:%[0-9]+]]:gr64 = SBB64ri32_ND [[SUB64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
+ ; ZU-NEXT: [[SBB64ri32_ND1:%[0-9]+]]:gr64 = SBB64ri32_ND [[SBB64ri32_ND]], 42, implicit-def dead $eflags, implicit killed $eflags
+ ; ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[SBB64ri32_ND1]]
+ ; ZU-NEXT: RET 0
;
- ; O0-NDD-ZU-LABEL: name: test_sbb
- ; O0-NDD-ZU: liveins: $rdi, $rsi
- ; O0-NDD-ZU-NEXT: {{ $}}
- ; O0-NDD-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; O0-NDD-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; O0-NDD-ZU-NEXT: [[SUB64rr_ND:%[0-9]+]]:gr64 = SUB64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
- ; O0-NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
- ; O0-NDD-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; O0-NDD-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr]], 255, implicit-def $eflags
- ; O0-NDD-ZU-NEXT: [[SBB64ri32_ND:%[0-9]+]]:gr64 = SBB64ri32_ND [[SUB64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
- ; O0-NDD-ZU-NEXT: [[SBB64ri32_ND1:%[0-9]+]]:gr64 = SBB64ri32_ND [[SBB64ri32_ND]], 42, implicit-def dead $eflags, implicit killed $eflags
- ; O0-NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[SBB64ri32_ND1]]
- ; O0-NDD-ZU-NEXT: RET 0
+ ; O0-ZU-LABEL: name: test_sbb
+ ; O0-ZU: liveins: $rdi, $rsi
+ ; O0-ZU-NEXT: {{ $}}
+ ; O0-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; O0-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; O0-ZU-NEXT: [[SUB64rr_ND:%[0-9]+]]:gr64 = SUB64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; O0-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; O0-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; O0-ZU-NEXT: dead [[ADD8ri:%[0-9]+]]:gr8 = ADD8ri [[SETZUCCr]], 255, implicit-def $eflags
+ ; O0-ZU-NEXT: [[SBB64ri32_ND:%[0-9]+]]:gr64 = SBB64ri32_ND [[SUB64rr_ND]], 42, implicit-def $eflags, implicit killed $eflags
+ ; O0-ZU-NEXT: [[SBB64ri32_ND1:%[0-9]+]]:gr64 = SBB64ri32_ND [[SBB64ri32_ND]], 42, implicit-def dead $eflags, implicit killed $eflags
+ ; O0-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[SBB64ri32_ND1]]
+ ; O0-ZU-NEXT: RET 0
%0:gr64 = COPY $rdi
%1:gr64 = COPY $rsi
%2:gr64 = SUB64rr_ND %0, %1, implicit-def $eflags
@@ -152,33 +152,33 @@ body: |
; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCL64r1_ND1]]
; CHECK-NEXT: RET 0
;
- ; NDD-ZU-LABEL: name: test_rcl
- ; NDD-ZU: liveins: $rdi, $rsi
- ; NDD-ZU-NEXT: {{ $}}
- ; NDD-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; NDD-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; NDD-ZU-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
- ; NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
- ; NDD-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; NDD-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr]], 255, implicit-def $eflags
- ; NDD-ZU-NEXT: [[RCL64r1_ND:%[0-9]+]]:gr64 = RCL64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
- ; NDD-ZU-NEXT: [[RCL64r1_ND1:%[0-9]+]]:gr64 = RCL64r1_ND [[RCL64r1_ND]], implicit-def $eflags, implicit $eflags
- ; NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCL64r1_ND1]]
- ; NDD-ZU-NEXT: RET 0
+ ; ZU-LABEL: name: test_rcl
+ ; ZU: liveins: $rdi, $rsi
+ ; ZU-NEXT: {{ $}}
+ ; ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; ZU-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; ZU-NEXT: dead [[ADD8ri:%[0-9]+]]:gr8 = ADD8ri [[SETZUCCr]], 255, implicit-def $eflags
+ ; ZU-NEXT: [[RCL64r1_ND:%[0-9]+]]:gr64 = RCL64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
+ ; ZU-NEXT: [[RCL64r1_ND1:%[0-9]+]]:gr64 = RCL64r1_ND [[RCL64r1_ND]], implicit-def $eflags, implicit $eflags
+ ; ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCL64r1_ND1]]
+ ; ZU-NEXT: RET 0
;
- ; O0-NDD-ZU-LABEL: name: test_rcl
- ; O0-NDD-ZU: liveins: $rdi, $rsi
- ; O0-NDD-ZU-NEXT: {{ $}}
- ; O0-NDD-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; O0-NDD-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; O0-NDD-ZU-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
- ; O0-NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
- ; O0-NDD-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; O0-NDD-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr]], 255, implicit-def $eflags
- ; O0-NDD-ZU-NEXT: [[RCL64r1_ND:%[0-9]+]]:gr64 = RCL64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
- ; O0-NDD-ZU-NEXT: [[RCL64r1_ND1:%[0-9]+]]:gr64 = RCL64r1_ND [[RCL64r1_ND]], implicit-def $eflags, implicit $eflags
- ; O0-NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCL64r1_ND1]]
- ; O0-NDD-ZU-NEXT: RET 0
+ ; O0-ZU-LABEL: name: test_rcl
+ ; O0-ZU: liveins: $rdi, $rsi
+ ; O0-ZU-NEXT: {{ $}}
+ ; O0-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; O0-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; O0-ZU-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; O0-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; O0-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; O0-ZU-NEXT: dead [[ADD8ri:%[0-9]+]]:gr8 = ADD8ri [[SETZUCCr]], 255, implicit-def $eflags
+ ; O0-ZU-NEXT: [[RCL64r1_ND:%[0-9]+]]:gr64 = RCL64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
+ ; O0-ZU-NEXT: [[RCL64r1_ND1:%[0-9]+]]:gr64 = RCL64r1_ND [[RCL64r1_ND]], implicit-def $eflags, implicit $eflags
+ ; O0-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCL64r1_ND1]]
+ ; O0-ZU-NEXT: RET 0
%0:gr64 = COPY $rdi
%1:gr64 = COPY $rsi
%2:gr64 = ADD64rr_ND %0, %1, implicit-def $eflags
@@ -214,33 +214,33 @@ body: |
; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCR64r1_ND1]]
; CHECK-NEXT: RET 0
;
- ; NDD-ZU-LABEL: name: test_rcr
- ; NDD-ZU: liveins: $rdi, $rsi
- ; NDD-ZU-NEXT: {{ $}}
- ; NDD-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; NDD-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; NDD-ZU-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
- ; NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
- ; NDD-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; NDD-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr]], 255, implicit-def $eflags
- ; NDD-ZU-NEXT: [[RCR64r1_ND:%[0-9]+]]:gr64 = RCR64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
- ; NDD-ZU-NEXT: [[RCR64r1_ND1:%[0-9]+]]:gr64 = RCR64r1_ND [[RCR64r1_ND]], implicit-def $eflags, implicit $eflags
- ; NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCR64r1_ND1]]
- ; NDD-ZU-NEXT: RET 0
+ ; ZU-LABEL: name: test_rcr
+ ; ZU: liveins: $rdi, $rsi
+ ; ZU-NEXT: {{ $}}
+ ; ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; ZU-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; ZU-NEXT: dead [[ADD8ri:%[0-9]+]]:gr8 = ADD8ri [[SETZUCCr]], 255, implicit-def $eflags
+ ; ZU-NEXT: [[RCR64r1_ND:%[0-9]+]]:gr64 = RCR64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
+ ; ZU-NEXT: [[RCR64r1_ND1:%[0-9]+]]:gr64 = RCR64r1_ND [[RCR64r1_ND]], implicit-def $eflags, implicit $eflags
+ ; ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCR64r1_ND1]]
+ ; ZU-NEXT: RET 0
;
- ; O0-NDD-ZU-LABEL: name: test_rcr
- ; O0-NDD-ZU: liveins: $rdi, $rsi
- ; O0-NDD-ZU-NEXT: {{ $}}
- ; O0-NDD-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; O0-NDD-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; O0-NDD-ZU-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
- ; O0-NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
- ; O0-NDD-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; O0-NDD-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr]], 255, implicit-def $eflags
- ; O0-NDD-ZU-NEXT: [[RCR64r1_ND:%[0-9]+]]:gr64 = RCR64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
- ; O0-NDD-ZU-NEXT: [[RCR64r1_ND1:%[0-9]+]]:gr64 = RCR64r1_ND [[RCR64r1_ND]], implicit-def $eflags, implicit $eflags
- ; O0-NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCR64r1_ND1]]
- ; O0-NDD-ZU-NEXT: RET 0
+ ; O0-ZU-LABEL: name: test_rcr
+ ; O0-ZU: liveins: $rdi, $rsi
+ ; O0-ZU-NEXT: {{ $}}
+ ; O0-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; O0-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; O0-ZU-NEXT: [[ADD64rr_ND:%[0-9]+]]:gr64 = ADD64rr_ND [[COPY]], [[COPY1]], implicit-def $eflags
+ ; O0-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; O0-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; O0-ZU-NEXT: dead [[ADD8ri:%[0-9]+]]:gr8 = ADD8ri [[SETZUCCr]], 255, implicit-def $eflags
+ ; O0-ZU-NEXT: [[RCR64r1_ND:%[0-9]+]]:gr64 = RCR64r1_ND [[ADD64rr_ND]], implicit-def $eflags, implicit killed $eflags
+ ; O0-ZU-NEXT: [[RCR64r1_ND1:%[0-9]+]]:gr64 = RCR64r1_ND [[RCR64r1_ND]], implicit-def $eflags, implicit $eflags
+ ; O0-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[RCR64r1_ND1]]
+ ; O0-ZU-NEXT: RET 0
%0:gr64 = COPY $rdi
%1:gr64 = COPY $rsi
%2:gr64 = ADD64rr_ND %0, %1, implicit-def $eflags
@@ -286,53 +286,53 @@ body: |
; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND3]]
; CHECK-NEXT: RET 0
;
- ; NDD-ZU-LABEL: name: test_cmov
- ; NDD-ZU: liveins: $rdi, $rsi
- ; NDD-ZU-NEXT: {{ $}}
- ; NDD-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; NDD-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; NDD-ZU-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
- ; NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
- ; NDD-ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
- ; NDD-ZU-NEXT: [[SETZUCCr2:%[0-9]+]]:gr8 = SETZUCCr 4, implicit $eflags
- ; NDD-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; NDD-ZU-NEXT: [[CMOV64rr_ND:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
- ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr1]], [[SETZUCCr1]], implicit-def $eflags
- ; NDD-ZU-NEXT: [[CMOV64rr_ND1:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
- ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
- ; NDD-ZU-NEXT: [[CMOV64rr_ND2:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
- ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
- ; NDD-ZU-NEXT: [[CMOV64rr_ND3:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
- ; NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND]]
- ; NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND1]]
- ; NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND2]]
- ; NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND3]]
- ; NDD-ZU-NEXT: RET 0
+ ; ZU-LABEL: name: test_cmov
+ ; ZU: liveins: $rdi, $rsi
+ ; ZU-NEXT: {{ $}}
+ ; ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; ZU-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
+ ; ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; ZU-NEXT: [[SETZUCCr2:%[0-9]+]]:gr8 = SETZUCCr 4, implicit $eflags
+ ; ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; ZU-NEXT: [[CMOV64rr_ND:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; ZU-NEXT: TEST8rr [[SETZUCCr1]], [[SETZUCCr1]], implicit-def $eflags
+ ; ZU-NEXT: [[CMOV64rr_ND1:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
+ ; ZU-NEXT: [[CMOV64rr_ND2:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
+ ; ZU-NEXT: [[CMOV64rr_ND3:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
+ ; ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND]]
+ ; ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND1]]
+ ; ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND2]]
+ ; ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND3]]
+ ; ZU-NEXT: RET 0
;
- ; O0-NDD-ZU-LABEL: name: test_cmov
- ; O0-NDD-ZU: liveins: $rdi, $rsi
- ; O0-NDD-ZU-NEXT: {{ $}}
- ; O0-NDD-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; O0-NDD-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; O0-NDD-ZU-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
- ; O0-NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
- ; O0-NDD-ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
- ; O0-NDD-ZU-NEXT: [[SETZUCCr2:%[0-9]+]]:gr8 = SETZUCCr 4, implicit $eflags
- ; O0-NDD-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; O0-NDD-ZU-NEXT: [[CMOV64rr_ND:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
- ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr1]], [[SETZUCCr1]], implicit-def $eflags
- ; O0-NDD-ZU-NEXT: [[CMOV64rr_ND1:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
- ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
- ; O0-NDD-ZU-NEXT: [[CMOV64rr_ND2:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
- ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
- ; O0-NDD-ZU-NEXT: [[CMOV64rr_ND3:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
- ; O0-NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND]]
- ; O0-NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND1]]
- ; O0-NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND2]]
- ; O0-NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND3]]
- ; O0-NDD-ZU-NEXT: RET 0
+ ; O0-ZU-LABEL: name: test_cmov
+ ; O0-ZU: liveins: $rdi, $rsi
+ ; O0-ZU-NEXT: {{ $}}
+ ; O0-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; O0-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; O0-ZU-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
+ ; O0-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; O0-ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; O0-ZU-NEXT: [[SETZUCCr2:%[0-9]+]]:gr8 = SETZUCCr 4, implicit $eflags
+ ; O0-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; O0-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; O0-ZU-NEXT: [[CMOV64rr_ND:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; O0-ZU-NEXT: TEST8rr [[SETZUCCr1]], [[SETZUCCr1]], implicit-def $eflags
+ ; O0-ZU-NEXT: [[CMOV64rr_ND1:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; O0-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
+ ; O0-ZU-NEXT: [[CMOV64rr_ND2:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; O0-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
+ ; O0-ZU-NEXT: [[CMOV64rr_ND3:%[0-9]+]]:gr64 = CMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
+ ; O0-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND]]
+ ; O0-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND1]]
+ ; O0-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND2]]
+ ; O0-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CMOV64rr_ND3]]
+ ; O0-ZU-NEXT: RET 0
%0:gr64 = COPY $rdi
%1:gr64 = COPY $rsi
CMP64rr %0, %1, implicit-def $eflags
@@ -382,53 +382,53 @@ body: |
; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND1]]
; CHECK-NEXT: RET 0
;
- ; NDD-ZU-LABEL: name: test_cfcmov
- ; NDD-ZU: liveins: $rdi, $rsi
- ; NDD-ZU-NEXT: {{ $}}
- ; NDD-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; NDD-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; NDD-ZU-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
- ; NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
- ; NDD-ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
- ; NDD-ZU-NEXT: [[SETZUCCr2:%[0-9]+]]:gr8 = SETZUCCr 4, implicit $eflags
- ; NDD-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; NDD-ZU-NEXT: [[CFCMOV64rr:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
- ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr1]], [[SETZUCCr1]], implicit-def $eflags
- ; NDD-ZU-NEXT: [[CFCMOV64rr1:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
- ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
- ; NDD-ZU-NEXT: [[CFCMOV64rr_ND:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
- ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
- ; NDD-ZU-NEXT: [[CFCMOV64rr_ND1:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
- ; NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr]]
- ; NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr1]]
- ; NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND]]
- ; NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND1]]
- ; NDD-ZU-NEXT: RET 0
+ ; ZU-LABEL: name: test_cfcmov
+ ; ZU: liveins: $rdi, $rsi
+ ; ZU-NEXT: {{ $}}
+ ; ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; ZU-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
+ ; ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; ZU-NEXT: [[SETZUCCr2:%[0-9]+]]:gr8 = SETZUCCr 4, implicit $eflags
+ ; ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; ZU-NEXT: [[CFCMOV64rr:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
+ ; ZU-NEXT: TEST8rr [[SETZUCCr1]], [[SETZUCCr1]], implicit-def $eflags
+ ; ZU-NEXT: [[CFCMOV64rr1:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
+ ; ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
+ ; ZU-NEXT: [[CFCMOV64rr_ND:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
+ ; ZU-NEXT: [[CFCMOV64rr_ND1:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
+ ; ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr]]
+ ; ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr1]]
+ ; ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND]]
+ ; ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND1]]
+ ; ZU-NEXT: RET 0
;
- ; O0-NDD-ZU-LABEL: name: test_cfcmov
- ; O0-NDD-ZU: liveins: $rdi, $rsi
- ; O0-NDD-ZU-NEXT: {{ $}}
- ; O0-NDD-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; O0-NDD-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; O0-NDD-ZU-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
- ; O0-NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
- ; O0-NDD-ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
- ; O0-NDD-ZU-NEXT: [[SETZUCCr2:%[0-9]+]]:gr8 = SETZUCCr 4, implicit $eflags
- ; O0-NDD-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
- ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; O0-NDD-ZU-NEXT: [[CFCMOV64rr:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
- ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr1]], [[SETZUCCr1]], implicit-def $eflags
- ; O0-NDD-ZU-NEXT: [[CFCMOV64rr1:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
- ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
- ; O0-NDD-ZU-NEXT: [[CFCMOV64rr_ND:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
- ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
- ; O0-NDD-ZU-NEXT: [[CFCMOV64rr_ND1:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
- ; O0-NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr]]
- ; O0-NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr1]]
- ; O0-NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND]]
- ; O0-NDD-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND1]]
- ; O0-NDD-ZU-NEXT: RET 0
+ ; O0-ZU-LABEL: name: test_cfcmov
+ ; O0-ZU: liveins: $rdi, $rsi
+ ; O0-ZU-NEXT: {{ $}}
+ ; O0-ZU-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; O0-ZU-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; O0-ZU-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
+ ; O0-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; O0-ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; O0-ZU-NEXT: [[SETZUCCr2:%[0-9]+]]:gr8 = SETZUCCr 4, implicit $eflags
+ ; O0-ZU-NEXT: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead $eflags
+ ; O0-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; O0-ZU-NEXT: [[CFCMOV64rr:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
+ ; O0-ZU-NEXT: TEST8rr [[SETZUCCr1]], [[SETZUCCr1]], implicit-def $eflags
+ ; O0-ZU-NEXT: [[CFCMOV64rr1:%[0-9]+]]:gr64 = CFCMOV64rr [[COPY1]], 5, implicit killed $eflags
+ ; O0-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
+ ; O0-ZU-NEXT: [[CFCMOV64rr_ND:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 5, implicit killed $eflags
+ ; O0-ZU-NEXT: TEST8rr [[SETZUCCr2]], [[SETZUCCr2]], implicit-def $eflags
+ ; O0-ZU-NEXT: [[CFCMOV64rr_ND1:%[0-9]+]]:gr64 = CFCMOV64rr_ND [[COPY]], [[COPY1]], 4, implicit killed $eflags
+ ; O0-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr]]
+ ; O0-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr1]]
+ ; O0-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND]]
+ ; O0-ZU-NEXT: MOV64mr $rsp, 1, $noreg, -16, $noreg, killed [[CFCMOV64rr_ND1]]
+ ; O0-ZU-NEXT: RET 0
%0:gr64 = COPY $rdi
%1:gr64 = COPY $rsi
CMP64rr %0, %1, implicit-def $eflags
@@ -464,25 +464,25 @@ body: |
; NDD-NEXT: CCMP32rr [[ADD32rr]], [[ADD32rr]], 0, 5, implicit-def $eflags, implicit killed $eflags
; NDD-NEXT: RET 0, $al
;
- ; NDD-ZU-LABEL: name: test_ccmp
- ; NDD-ZU: liveins: $edi
- ; NDD-ZU-NEXT: {{ $}}
- ; NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 1, implicit $eflags
- ; NDD-ZU-NEXT: [[ADD32rr:%[0-9]+]]:gr32 = ADD32rr $edi, $edi, implicit-def dead $eflags
- ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; NDD-ZU-NEXT: CCMP32rr [[ADD32rr]], [[ADD32rr]], 0, 5, implicit-def $eflags, implicit killed $eflags
- ; NDD-ZU-NEXT: RET 0, $al
+ ; ZU-LABEL: name: test_ccmp
+ ; ZU: liveins: $edi
+ ; ZU-NEXT: {{ $}}
+ ; ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 1, implicit $eflags
+ ; ZU-NEXT: [[ADD32rr:%[0-9]+]]:gr32 = ADD32rr $edi, $edi, implicit-def dead $eflags
+ ; ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; ZU-NEXT: CCMP32rr [[ADD32rr]], [[ADD32rr]], 0, 5, implicit-def $eflags, implicit killed $eflags
+ ; ZU-NEXT: RET 0, $al
;
- ; O0-NDD-ZU-LABEL: name: test_ccmp
- ; O0-NDD-ZU: liveins: $edi
- ; O0-NDD-ZU-NEXT: {{ $}}
- ; O0-NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; O0-NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 1, implicit $eflags
- ; O0-NDD-ZU-NEXT: [[ADD32rr:%[0-9]+]]:gr32 = ADD32rr $edi, $edi, implicit-def dead $eflags
- ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; O0-NDD-ZU-NEXT: CCMP32rr [[ADD32rr]], [[ADD32rr]], 0, 5, implicit-def $eflags, implicit killed $eflags
- ; O0-NDD-ZU-NEXT: RET 0, $al
+ ; O0-ZU-LABEL: name: test_ccmp
+ ; O0-ZU: liveins: $edi
+ ; O0-ZU-NEXT: {{ $}}
+ ; O0-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; O0-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 1, implicit $eflags
+ ; O0-ZU-NEXT: [[ADD32rr:%[0-9]+]]:gr32 = ADD32rr $edi, $edi, implicit-def dead $eflags
+ ; O0-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; O0-ZU-NEXT: CCMP32rr [[ADD32rr]], [[ADD32rr]], 0, 5, implicit-def $eflags, implicit killed $eflags
+ ; O0-ZU-NEXT: RET 0, $al
;
; NDD-NF-LABEL: name: test_ccmp
; NDD-NF: liveins: $edi
@@ -515,25 +515,25 @@ body: |
; NDD-NEXT: CTEST32rr [[ADD32rr]], [[ADD32rr]], 0, 5, implicit-def $eflags, implicit killed $eflags
; NDD-NEXT: RET 0, $al
;
- ; NDD-ZU-LABEL: name: test_ctest
- ; NDD-ZU: liveins: $edi
- ; NDD-ZU-NEXT: {{ $}}
- ; NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 1, implicit $eflags
- ; NDD-ZU-NEXT: [[ADD32rr:%[0-9]+]]:gr32 = ADD32rr $edi, $edi, implicit-def dead $eflags
- ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; NDD-ZU-NEXT: CTEST32rr [[ADD32rr]], [[ADD32rr]], 0, 5, implicit-def $eflags, implicit killed $eflags
- ; NDD-ZU-NEXT: RET 0, $al
+ ; ZU-LABEL: name: test_ctest
+ ; ZU: liveins: $edi
+ ; ZU-NEXT: {{ $}}
+ ; ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 1, implicit $eflags
+ ; ZU-NEXT: [[ADD32rr:%[0-9]+]]:gr32 = ADD32rr $edi, $edi, implicit-def dead $eflags
+ ; ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; ZU-NEXT: CTEST32rr [[ADD32rr]], [[ADD32rr]], 0, 5, implicit-def $eflags, implicit killed $eflags
+ ; ZU-NEXT: RET 0, $al
;
- ; O0-NDD-ZU-LABEL: name: test_ctest
- ; O0-NDD-ZU: liveins: $edi
- ; O0-NDD-ZU-NEXT: {{ $}}
- ; O0-NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; O0-NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 1, implicit $eflags
- ; O0-NDD-ZU-NEXT: [[ADD32rr:%[0-9]+]]:gr32 = ADD32rr $edi, $edi, implicit-def dead $eflags
- ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; O0-NDD-ZU-NEXT: CTEST32rr [[ADD32rr]], [[ADD32rr]], 0, 5, implicit-def $eflags, implicit killed $eflags
- ; O0-NDD-ZU-NEXT: RET 0, $al
+ ; O0-ZU-LABEL: name: test_ctest
+ ; O0-ZU: liveins: $edi
+ ; O0-ZU-NEXT: {{ $}}
+ ; O0-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; O0-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 1, implicit $eflags
+ ; O0-ZU-NEXT: [[ADD32rr:%[0-9]+]]:gr32 = ADD32rr $edi, $edi, implicit-def dead $eflags
+ ; O0-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; O0-ZU-NEXT: CTEST32rr [[ADD32rr]], [[ADD32rr]], 0, 5, implicit-def $eflags, implicit killed $eflags
+ ; O0-ZU-NEXT: RET 0, $al
;
; NDD-NF-LABEL: name: test_ctest
; NDD-NF: liveins: $edi
@@ -566,25 +566,25 @@ body: |
; NDD-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND]], 5, implicit killed $eflags
; NDD-NEXT: RET 0, $al
;
- ; NDD-ZU-LABEL: name: test_evitable_clobber
- ; NDD-ZU: liveins: $edi
- ; NDD-ZU-NEXT: {{ $}}
- ; NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
- ; NDD-ZU-NEXT: [[ADD32rr_ND:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
- ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND]], 5, implicit killed $eflags
- ; NDD-ZU-NEXT: RET 0, $al
+ ; ZU-LABEL: name: test_evitable_clobber
+ ; ZU: liveins: $edi
+ ; ZU-NEXT: {{ $}}
+ ; ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; ZU-NEXT: [[ADD32rr_ND:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
+ ; ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND]], 5, implicit killed $eflags
+ ; ZU-NEXT: RET 0, $al
;
- ; O0-NDD-ZU-LABEL: name: test_evitable_clobber
- ; O0-NDD-ZU: liveins: $edi
- ; O0-NDD-ZU-NEXT: {{ $}}
- ; O0-NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; O0-NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
- ; O0-NDD-ZU-NEXT: [[ADD32rr_ND:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
- ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; O0-NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND]], 5, implicit killed $eflags
- ; O0-NDD-ZU-NEXT: RET 0, $al
+ ; O0-ZU-LABEL: name: test_evitable_clobber
+ ; O0-ZU: liveins: $edi
+ ; O0-ZU-NEXT: {{ $}}
+ ; O0-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; O0-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; O0-ZU-NEXT: [[ADD32rr_ND:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
+ ; O0-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; O0-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND]], 5, implicit killed $eflags
+ ; O0-ZU-NEXT: RET 0, $al
;
; NDD-NF-LABEL: name: test_evitable_clobber
; NDD-NF: liveins: $edi
@@ -617,25 +617,25 @@ body: |
; CHECK-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
; CHECK-NEXT: RET 0, $al
;
- ; NDD-ZU-LABEL: name: test_inevitable_clobber
- ; NDD-ZU: liveins: $edi
- ; NDD-ZU-NEXT: {{ $}}
- ; NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
- ; NDD-ZU-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
- ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
- ; NDD-ZU-NEXT: RET 0, $al
+ ; ZU-LABEL: name: test_inevitable_clobber
+ ; ZU: liveins: $edi
+ ; ZU-NEXT: {{ $}}
+ ; ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; ZU-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
+ ; ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
+ ; ZU-NEXT: RET 0, $al
;
- ; O0-NDD-ZU-LABEL: name: test_inevitable_clobber
- ; O0-NDD-ZU: liveins: $edi
- ; O0-NDD-ZU-NEXT: {{ $}}
- ; O0-NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; O0-NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
- ; O0-NDD-ZU-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
- ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; O0-NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
- ; O0-NDD-ZU-NEXT: RET 0, $al
+ ; O0-ZU-LABEL: name: test_inevitable_clobber
+ ; O0-ZU: liveins: $edi
+ ; O0-ZU-NEXT: {{ $}}
+ ; O0-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; O0-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; O0-ZU-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
+ ; O0-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; O0-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
+ ; O0-ZU-NEXT: RET 0, $al
MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
%1:gr64 = COPY $eflags
%2:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
@@ -663,33 +663,33 @@ body: |
; NDD-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND1]], 5, implicit killed $eflags
; NDD-NEXT: RET 0, $al
;
- ; NDD-ZU-LABEL: name: test_evitable_clobber_multiple_uses
- ; NDD-ZU: liveins: $edi
- ; NDD-ZU-NEXT: {{ $}}
- ; NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
- ; NDD-ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 9, implicit $eflags
- ; NDD-ZU-NEXT: [[ADD32rr_ND:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
- ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND]], 5, implicit killed $eflags
- ; NDD-ZU-NEXT: [[ADD32rr_ND1:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $eax, implicit-def dead $eflags
- ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr1]], [[SETZUCCr1]], implicit-def $eflags
- ; NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND1]], 5, implicit killed $eflags
- ; NDD-ZU-NEXT: RET 0, $al
+ ; ZU-LABEL: name: test_evitable_clobber_multiple_uses
+ ; ZU: liveins: $edi
+ ; ZU-NEXT: {{ $}}
+ ; ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 9, implicit $eflags
+ ; ZU-NEXT: [[ADD32rr_ND:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
+ ; ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND]], 5, implicit killed $eflags
+ ; ZU-NEXT: [[ADD32rr_ND1:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $eax, implicit-def dead $eflags
+ ; ZU-NEXT: TEST8rr [[SETZUCCr1]], [[SETZUCCr1]], implicit-def $eflags
+ ; ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND1]], 5, implicit killed $eflags
+ ; ZU-NEXT: RET 0, $al
;
- ; O0-NDD-ZU-LABEL: name: test_evitable_clobber_multiple_uses
- ; O0-NDD-ZU: liveins: $edi
- ; O0-NDD-ZU-NEXT: {{ $}}
- ; O0-NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; O0-NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
- ; O0-NDD-ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 9, implicit $eflags
- ; O0-NDD-ZU-NEXT: [[ADD32rr_ND:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
- ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; O0-NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND]], 5, implicit killed $eflags
- ; O0-NDD-ZU-NEXT: [[ADD32rr_ND1:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $eax, implicit-def dead $eflags
- ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr1]], [[SETZUCCr1]], implicit-def $eflags
- ; O0-NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND1]], 5, implicit killed $eflags
- ; O0-NDD-ZU-NEXT: RET 0, $al
+ ; O0-ZU-LABEL: name: test_evitable_clobber_multiple_uses
+ ; O0-ZU: liveins: $edi
+ ; O0-ZU-NEXT: {{ $}}
+ ; O0-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; O0-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; O0-ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 9, implicit $eflags
+ ; O0-ZU-NEXT: [[ADD32rr_ND:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
+ ; O0-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; O0-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND]], 5, implicit killed $eflags
+ ; O0-ZU-NEXT: [[ADD32rr_ND1:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $eax, implicit-def dead $eflags
+ ; O0-ZU-NEXT: TEST8rr [[SETZUCCr1]], [[SETZUCCr1]], implicit-def $eflags
+ ; O0-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND1]], 5, implicit killed $eflags
+ ; O0-ZU-NEXT: RET 0, $al
;
; NDD-NF-LABEL: name: test_evitable_clobber_multiple_uses
; NDD-NF: liveins: $edi
@@ -732,35 +732,35 @@ body: |
; NDD-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND]], 5, implicit killed $eflags
; NDD-NEXT: RET 0, $al
;
- ; NDD-ZU-LABEL: name: test_mixed_clobber
- ; NDD-ZU: liveins: $edi
- ; NDD-ZU-NEXT: {{ $}}
- ; NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
- ; NDD-ZU-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
- ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
- ; NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; NDD-ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 1, implicit $eflags
- ; NDD-ZU-NEXT: [[ADD32rr_ND:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
- ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr1]], [[SETZUCCr1]], implicit-def $eflags
- ; NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND]], 5, implicit killed $eflags
- ; NDD-ZU-NEXT: RET 0, $al
+ ; ZU-LABEL: name: test_mixed_clobber
+ ; ZU: liveins: $edi
+ ; ZU-NEXT: {{ $}}
+ ; ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; ZU-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
+ ; ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
+ ; ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 1, implicit $eflags
+ ; ZU-NEXT: [[ADD32rr_ND:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
+ ; ZU-NEXT: TEST8rr [[SETZUCCr1]], [[SETZUCCr1]], implicit-def $eflags
+ ; ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND]], 5, implicit killed $eflags
+ ; ZU-NEXT: RET 0, $al
;
- ; O0-NDD-ZU-LABEL: name: test_mixed_clobber
- ; O0-NDD-ZU: liveins: $edi
- ; O0-NDD-ZU-NEXT: {{ $}}
- ; O0-NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; O0-NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
- ; O0-NDD-ZU-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
- ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; O0-NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
- ; O0-NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; O0-NDD-ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 1, implicit $eflags
- ; O0-NDD-ZU-NEXT: [[ADD32rr_ND:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
- ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr1]], [[SETZUCCr1]], implicit-def $eflags
- ; O0-NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND]], 5, implicit killed $eflags
- ; O0-NDD-ZU-NEXT: RET 0, $al
+ ; O0-ZU-LABEL: name: test_mixed_clobber
+ ; O0-ZU: liveins: $edi
+ ; O0-ZU-NEXT: {{ $}}
+ ; O0-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; O0-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; O0-ZU-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
+ ; O0-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; O0-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
+ ; O0-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; O0-ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 1, implicit $eflags
+ ; O0-ZU-NEXT: [[ADD32rr_ND:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
+ ; O0-ZU-NEXT: TEST8rr [[SETZUCCr1]], [[SETZUCCr1]], implicit-def $eflags
+ ; O0-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND]], 5, implicit killed $eflags
+ ; O0-ZU-NEXT: RET 0, $al
;
; NDD-NF-LABEL: name: test_mixed_clobber
; NDD-NF: liveins: $edi
@@ -808,43 +808,43 @@ body: |
; NDD-NEXT: $eax = ADC32rr_ND $eax, $edi, implicit-def dead $eflags, implicit killed $eflags
; NDD-NEXT: RET 0, $al
;
- ; NDD-ZU-LABEL: name: test_evitable_clobber_crossbb
- ; NDD-ZU: bb.0:
- ; NDD-ZU-NEXT: successors: %bb.1(0x80000000)
- ; NDD-ZU-NEXT: liveins: $edi
- ; NDD-ZU-NEXT: {{ $}}
- ; NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
- ; NDD-ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
- ; NDD-ZU-NEXT: [[ADD32rr_ND:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
- ; NDD-ZU-NEXT: JCC_1 %bb.1, 4, implicit $eflags
- ; NDD-ZU-NEXT: RET 0, $al
- ; NDD-ZU-NEXT: {{ $}}
- ; NDD-ZU-NEXT: bb.1:
- ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND]], 5, implicit killed $eflags
- ; NDD-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr1]], 255, implicit-def $eflags
- ; NDD-ZU-NEXT: $eax = ADC32rr_ND $eax, $edi, implicit-def dead $eflags, implicit killed $eflags
- ; NDD-ZU-NEXT: RET 0, $al
+ ; ZU-LABEL: name: test_evitable_clobber_crossbb
+ ; ZU: bb.0:
+ ; ZU-NEXT: successors: %bb.1(0x80000000)
+ ; ZU-NEXT: liveins: $edi
+ ; ZU-NEXT: {{ $}}
+ ; ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; ZU-NEXT: [[ADD32rr_ND:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
+ ; ZU-NEXT: JCC_1 %bb.1, 4, implicit $eflags
+ ; ZU-NEXT: RET 0, $al
+ ; ZU-NEXT: {{ $}}
+ ; ZU-NEXT: bb.1:
+ ; ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND]], 5, implicit killed $eflags
+ ; ZU-NEXT: dead [[ADD8ri:%[0-9]+]]:gr8 = ADD8ri [[SETZUCCr1]], 255, implicit-def $eflags
+ ; ZU-NEXT: $eax = ADC32rr_ND $eax, $edi, implicit-def dead $eflags, implicit killed $eflags
+ ; ZU-NEXT: RET 0, $al
;
- ; O0-NDD-ZU-LABEL: name: test_evitable_clobber_crossbb
- ; O0-NDD-ZU: bb.0:
- ; O0-NDD-ZU-NEXT: successors: %bb.1(0x80000000)
- ; O0-NDD-ZU-NEXT: liveins: $edi
- ; O0-NDD-ZU-NEXT: {{ $}}
- ; O0-NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; O0-NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
- ; O0-NDD-ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
- ; O0-NDD-ZU-NEXT: [[ADD32rr_ND:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
- ; O0-NDD-ZU-NEXT: JCC_1 %bb.1, 4, implicit $eflags
- ; O0-NDD-ZU-NEXT: RET 0, $al
- ; O0-NDD-ZU-NEXT: {{ $}}
- ; O0-NDD-ZU-NEXT: bb.1:
- ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; O0-NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND]], 5, implicit killed $eflags
- ; O0-NDD-ZU-NEXT: dead [[ADD8ri_ND:%[0-9]+]]:gr8 = ADD8ri_ND [[SETZUCCr1]], 255, implicit-def $eflags
- ; O0-NDD-ZU-NEXT: $eax = ADC32rr_ND $eax, $edi, implicit-def dead $eflags, implicit killed $eflags
- ; O0-NDD-ZU-NEXT: RET 0, $al
+ ; O0-ZU-LABEL: name: test_evitable_clobber_crossbb
+ ; O0-ZU: bb.0:
+ ; O0-ZU-NEXT: successors: %bb.1(0x80000000)
+ ; O0-ZU-NEXT: liveins: $edi
+ ; O0-ZU-NEXT: {{ $}}
+ ; O0-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; O0-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; O0-ZU-NEXT: [[SETZUCCr1:%[0-9]+]]:gr8 = SETZUCCr 2, implicit $eflags
+ ; O0-ZU-NEXT: [[ADD32rr_ND:%[0-9]+]]:gr32 = ADD32rr_ND $edi, $edi, implicit-def dead $eflags
+ ; O0-ZU-NEXT: JCC_1 %bb.1, 4, implicit $eflags
+ ; O0-ZU-NEXT: RET 0, $al
+ ; O0-ZU-NEXT: {{ $}}
+ ; O0-ZU-NEXT: bb.1:
+ ; O0-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; O0-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADD32rr_ND]], 5, implicit killed $eflags
+ ; O0-ZU-NEXT: dead [[ADD8ri:%[0-9]+]]:gr8 = ADD8ri [[SETZUCCr1]], 255, implicit-def $eflags
+ ; O0-ZU-NEXT: $eax = ADC32rr_ND $eax, $edi, implicit-def dead $eflags, implicit killed $eflags
+ ; O0-ZU-NEXT: RET 0, $al
;
; NDD-NF-LABEL: name: test_evitable_clobber_crossbb
; NDD-NF: bb.0:
@@ -897,37 +897,37 @@ body: |
; CHECK-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
; CHECK-NEXT: RET 0, $al
;
- ; NDD-ZU-LABEL: name: test_inevitable_clobber_crossbb
- ; NDD-ZU: bb.0:
- ; NDD-ZU-NEXT: successors: %bb.1(0x80000000)
- ; NDD-ZU-NEXT: liveins: $edi
- ; NDD-ZU-NEXT: {{ $}}
- ; NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
- ; NDD-ZU-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
- ; NDD-ZU-NEXT: JCC_1 %bb.1, 4, implicit $eflags
- ; NDD-ZU-NEXT: RET 0, $al
- ; NDD-ZU-NEXT: {{ $}}
- ; NDD-ZU-NEXT: bb.1:
- ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
- ; NDD-ZU-NEXT: RET 0, $al
+ ; ZU-LABEL: name: test_inevitable_clobber_crossbb
+ ; ZU: bb.0:
+ ; ZU-NEXT: successors: %bb.1(0x80000000)
+ ; ZU-NEXT: liveins: $edi
+ ; ZU-NEXT: {{ $}}
+ ; ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; ZU-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
+ ; ZU-NEXT: JCC_1 %bb.1, 4, implicit $eflags
+ ; ZU-NEXT: RET 0, $al
+ ; ZU-NEXT: {{ $}}
+ ; ZU-NEXT: bb.1:
+ ; ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
+ ; ZU-NEXT: RET 0, $al
;
- ; O0-NDD-ZU-LABEL: name: test_inevitable_clobber_crossbb
- ; O0-NDD-ZU: bb.0:
- ; O0-NDD-ZU-NEXT: successors: %bb.1(0x80000000)
- ; O0-NDD-ZU-NEXT: liveins: $edi
- ; O0-NDD-ZU-NEXT: {{ $}}
- ; O0-NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; O0-NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
- ; O0-NDD-ZU-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
- ; O0-NDD-ZU-NEXT: JCC_1 %bb.1, 4, implicit $eflags
- ; O0-NDD-ZU-NEXT: RET 0, $al
- ; O0-NDD-ZU-NEXT: {{ $}}
- ; O0-NDD-ZU-NEXT: bb.1:
- ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; O0-NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
- ; O0-NDD-ZU-NEXT: RET 0, $al
+ ; O0-ZU-LABEL: name: test_inevitable_clobber_crossbb
+ ; O0-ZU: bb.0:
+ ; O0-ZU-NEXT: successors: %bb.1(0x80000000)
+ ; O0-ZU-NEXT: liveins: $edi
+ ; O0-ZU-NEXT: {{ $}}
+ ; O0-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; O0-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; O0-ZU-NEXT: [[ADC32rr_ND:%[0-9]+]]:gr32 = ADC32rr_ND $edi, $edi, implicit-def dead $eflags, implicit $eflags
+ ; O0-ZU-NEXT: JCC_1 %bb.1, 4, implicit $eflags
+ ; O0-ZU-NEXT: RET 0, $al
+ ; O0-ZU-NEXT: {{ $}}
+ ; O0-ZU-NEXT: bb.1:
+ ; O0-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; O0-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[ADC32rr_ND]], 5, implicit killed $eflags
+ ; O0-ZU-NEXT: RET 0, $al
bb.0:
liveins: $edi
@@ -973,59 +973,59 @@ body: |
; NDD-NEXT: $eax = CMOV32rr_ND $edi, [[SUB32rr_ND]], 5, implicit killed $eflags
; NDD-NEXT: RET 0, $al
;
- ; NDD-ZU-LABEL: name: test_evitable_clobber_crossbb_complex
- ; NDD-ZU: bb.0:
- ; NDD-ZU-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; NDD-ZU-NEXT: liveins: $edi
- ; NDD-ZU-NEXT: {{ $}}
- ; NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
- ; NDD-ZU-NEXT: [[SUB32rr_ND:%[0-9]+]]:gr32 = SUB32rr_ND $edi, $edi, implicit-def dead $eflags
- ; NDD-ZU-NEXT: JCC_1 %bb.2, 4, implicit $eflags
- ; NDD-ZU-NEXT: {{ $}}
- ; NDD-ZU-NEXT: bb.1:
- ; NDD-ZU-NEXT: successors: %bb.3(0x80000000)
- ; NDD-ZU-NEXT: {{ $}}
- ; NDD-ZU-NEXT: $eax = IMUL32rr_ND $eax, $edi, implicit-def dead $eflags
- ; NDD-ZU-NEXT: JMP_1 %bb.3
- ; NDD-ZU-NEXT: {{ $}}
- ; NDD-ZU-NEXT: bb.2:
- ; NDD-ZU-NEXT: successors: %bb.3(0x80000000)
- ; NDD-ZU-NEXT: {{ $}}
- ; NDD-ZU-NEXT: $eax = IMUL32rr $eax, $esi, implicit-def dead $eflags
- ; NDD-ZU-NEXT: JMP_1 %bb.3
- ; NDD-ZU-NEXT: {{ $}}
- ; NDD-ZU-NEXT: bb.3:
- ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[SUB32rr_ND]], 5, implicit killed $eflags
- ; NDD-ZU-NEXT: RET 0, $al
+ ; ZU-LABEL: name: test_evitable_clobber_crossbb_complex
+ ; ZU: bb.0:
+ ; ZU-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; ZU-NEXT: liveins: $edi
+ ; ZU-NEXT: {{ $}}
+ ; ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; ZU-NEXT: [[SUB32rr_ND:%[0-9]+]]:gr32 = SUB32rr_ND $edi, $edi, implicit-def dead $eflags
+ ; ZU-NEXT: JCC_1 %bb.2, 4, implicit $eflags
+ ; ZU-NEXT: {{ $}}
+ ; ZU-NEXT: bb.1:
+ ; ZU-NEXT: successors: %bb.3(0x80000000)
+ ; ZU-NEXT: {{ $}}
+ ; ZU-NEXT: $eax = IMUL32rr_ND $eax, $edi, implicit-def dead $eflags
+ ; ZU-NEXT: JMP_1 %bb.3
+ ; ZU-NEXT: {{ $}}
+ ; ZU-NEXT: bb.2:
+ ; ZU-NEXT: successors: %bb.3(0x80000000)
+ ; ZU-NEXT: {{ $}}
+ ; ZU-NEXT: $eax = IMUL32rr $eax, $esi, implicit-def dead $eflags
+ ; ZU-NEXT: JMP_1 %bb.3
+ ; ZU-NEXT: {{ $}}
+ ; ZU-NEXT: bb.3:
+ ; ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; ZU-NEXT: $eax = CMOV32rr_ND $edi, [[SUB32rr_ND]], 5, implicit killed $eflags
+ ; ZU-NEXT: RET 0, $al
;
- ; O0-NDD-ZU-LABEL: name: test_evitable_clobber_crossbb_complex
- ; O0-NDD-ZU: bb.0:
- ; O0-NDD-ZU-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; O0-NDD-ZU-NEXT: liveins: $edi
- ; O0-NDD-ZU-NEXT: {{ $}}
- ; O0-NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; O0-NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
- ; O0-NDD-ZU-NEXT: [[SUB32rr_ND:%[0-9]+]]:gr32 = SUB32rr_ND $edi, $edi, implicit-def dead $eflags
- ; O0-NDD-ZU-NEXT: JCC_1 %bb.2, 4, implicit $eflags
- ; O0-NDD-ZU-NEXT: {{ $}}
- ; O0-NDD-ZU-NEXT: bb.1:
- ; O0-NDD-ZU-NEXT: successors: %bb.3(0x80000000)
- ; O0-NDD-ZU-NEXT: {{ $}}
- ; O0-NDD-ZU-NEXT: $eax = IMUL32rr_ND $eax, $edi, implicit-def dead $eflags
- ; O0-NDD-ZU-NEXT: JMP_1 %bb.3
- ; O0-NDD-ZU-NEXT: {{ $}}
- ; O0-NDD-ZU-NEXT: bb.2:
- ; O0-NDD-ZU-NEXT: successors: %bb.3(0x80000000)
- ; O0-NDD-ZU-NEXT: {{ $}}
- ; O0-NDD-ZU-NEXT: $eax = IMUL32rr $eax, $esi, implicit-def dead $eflags
- ; O0-NDD-ZU-NEXT: JMP_1 %bb.3
- ; O0-NDD-ZU-NEXT: {{ $}}
- ; O0-NDD-ZU-NEXT: bb.3:
- ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; O0-NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[SUB32rr_ND]], 5, implicit killed $eflags
- ; O0-NDD-ZU-NEXT: RET 0, $al
+ ; O0-ZU-LABEL: name: test_evitable_clobber_crossbb_complex
+ ; O0-ZU: bb.0:
+ ; O0-ZU-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; O0-ZU-NEXT: liveins: $edi
+ ; O0-ZU-NEXT: {{ $}}
+ ; O0-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; O0-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; O0-ZU-NEXT: [[SUB32rr_ND:%[0-9]+]]:gr32 = SUB32rr_ND $edi, $edi, implicit-def dead $eflags
+ ; O0-ZU-NEXT: JCC_1 %bb.2, 4, implicit $eflags
+ ; O0-ZU-NEXT: {{ $}}
+ ; O0-ZU-NEXT: bb.1:
+ ; O0-ZU-NEXT: successors: %bb.3(0x80000000)
+ ; O0-ZU-NEXT: {{ $}}
+ ; O0-ZU-NEXT: $eax = IMUL32rr_ND $eax, $edi, implicit-def dead $eflags
+ ; O0-ZU-NEXT: JMP_1 %bb.3
+ ; O0-ZU-NEXT: {{ $}}
+ ; O0-ZU-NEXT: bb.2:
+ ; O0-ZU-NEXT: successors: %bb.3(0x80000000)
+ ; O0-ZU-NEXT: {{ $}}
+ ; O0-ZU-NEXT: $eax = IMUL32rr $eax, $esi, implicit-def dead $eflags
+ ; O0-ZU-NEXT: JMP_1 %bb.3
+ ; O0-ZU-NEXT: {{ $}}
+ ; O0-ZU-NEXT: bb.3:
+ ; O0-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; O0-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[SUB32rr_ND]], 5, implicit killed $eflags
+ ; O0-ZU-NEXT: RET 0, $al
;
; NDD-NF-LABEL: name: test_evitable_clobber_crossbb_complex
; NDD-NF: bb.0:
@@ -1107,60 +1107,59 @@ body: |
; CHECK-NEXT: $eax = CMOV32rr_ND $edi, [[SUB32rr_ND]], 5, implicit killed $eflags
; CHECK-NEXT: RET 0, $al
;
- ; NDD-ZU-LABEL: name: test_inevitable_clobber_crossbb_complex
- ; NDD-ZU: bb.0:
- ; NDD-ZU-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; NDD-ZU-NEXT: liveins: $edi
- ; NDD-ZU-NEXT: {{ $}}
- ; NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
- ; NDD-ZU-NEXT: [[SUB32rr_ND:%[0-9]+]]:gr32 = SUB32rr_ND $edi, $edi, implicit-def dead $eflags
- ; NDD-ZU-NEXT: JCC_1 %bb.2, 4, implicit $eflags
- ; NDD-ZU-NEXT: {{ $}}
- ; NDD-ZU-NEXT: bb.1:
- ; NDD-ZU-NEXT: successors: %bb.3(0x80000000)
- ; NDD-ZU-NEXT: {{ $}}
- ; NDD-ZU-NEXT: $eax = IMUL32rr_ND $eax, $edi, implicit-def dead $eflags
- ; NDD-ZU-NEXT: JMP_1 %bb.3
- ; NDD-ZU-NEXT: {{ $}}
- ; NDD-ZU-NEXT: bb.2:
- ; NDD-ZU-NEXT: successors: %bb.3(0x80000000)
- ; NDD-ZU-NEXT: {{ $}}
- ; NDD-ZU-NEXT: $eax = SBB32rr $eax, $esi, implicit-def dead $eflags, implicit $eflags
- ; NDD-ZU-NEXT: JMP_1 %bb.3
- ; NDD-ZU-NEXT: {{ $}}
- ; NDD-ZU-NEXT: bb.3:
- ; NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[SUB32rr_ND]], 5, implicit killed $eflags
- ; NDD-ZU-NEXT: RET 0, $al
+ ; ZU-LABEL: name: test_inevitable_clobber_crossbb_complex
+ ; ZU: bb.0:
+ ; ZU-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; ZU-NEXT: liveins: $edi
+ ; ZU-NEXT: {{ $}}
+ ; ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; ZU-NEXT: [[SUB32rr_ND:%[0-9]+]]:gr32 = SUB32rr_ND $edi, $edi, implicit-def dead $eflags
+ ; ZU-NEXT: JCC_1 %bb.2, 4, implicit $eflags
+ ; ZU-NEXT: {{ $}}
+ ; ZU-NEXT: bb.1:
+ ; ZU-NEXT: successors: %bb.3(0x80000000)
+ ; ZU-NEXT: {{ $}}
+ ; ZU-NEXT: $eax = IMUL32rr_ND $eax, $edi, implicit-def dead $eflags
+ ; ZU-NEXT: JMP_1 %bb.3
+ ; ZU-NEXT: {{ $}}
+ ; ZU-NEXT: bb.2:
+ ; ZU-NEXT: successors: %bb.3(0x80000000)
+ ; ZU-NEXT: {{ $}}
+ ; ZU-NEXT: $eax = SBB32rr $eax, $esi, implicit-def dead $eflags, implicit $eflags
+ ; ZU-NEXT: JMP_1 %bb.3
+ ; ZU-NEXT: {{ $}}
+ ; ZU-NEXT: bb.3:
+ ; ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; ZU-NEXT: $eax = CMOV32rr_ND $edi, [[SUB32rr_ND]], 5, implicit killed $eflags
+ ; ZU-NEXT: RET 0, $al
;
- ; O0-NDD-ZU-LABEL: name: test_inevitable_clobber_crossbb_complex
- ; O0-NDD-ZU: bb.0:
- ; O0-NDD-ZU-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; O0-NDD-ZU-NEXT: liveins: $edi
- ; O0-NDD-ZU-NEXT: {{ $}}
- ; O0-NDD-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
- ; O0-NDD-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
- ; O0-NDD-ZU-NEXT: [[SUB32rr_ND:%[0-9]+]]:gr32 = SUB32rr_ND $edi, $edi, implicit-def dead $eflags
- ; O0-NDD-ZU-NEXT: JCC_1 %bb.2, 4, implicit $eflags
- ; O0-NDD-ZU-NEXT: {{ $}}
- ; O0-NDD-ZU-NEXT: bb.1:
- ; O0-NDD-ZU-NEXT: successors: %bb.3(0x80000000)
- ; O0-NDD-ZU-NEXT: {{ $}}
- ; O0-NDD-ZU-NEXT: $eax = IMUL32rr_ND $eax, $edi, implicit-def dead $eflags
- ; O0-NDD-ZU-NEXT: JMP_1 %bb.3
- ; O0-NDD-ZU-NEXT: {{ $}}
- ; O0-NDD-ZU-NEXT: bb.2:
- ; O0-NDD-ZU-NEXT: successors: %bb.3(0x80000000)
- ; O0-NDD-ZU-NEXT: {{ $}}
- ; O0-NDD-ZU-NEXT: $eax = SBB32rr $eax, $esi, implicit-def dead $eflags, implicit $eflags
- ; O0-NDD-ZU-NEXT: JMP_1 %bb.3
- ; O0-NDD-ZU-NEXT: {{ $}}
- ; O0-NDD-ZU-NEXT: bb.3:
- ; O0-NDD-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
- ; O0-NDD-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[SUB32rr_ND]], 5, implicit killed $eflags
- ; O0-NDD-ZU-NEXT: RET 0, $al
-
+ ; O0-ZU-LABEL: name: test_inevitable_clobber_crossbb_complex
+ ; O0-ZU: bb.0:
+ ; O0-ZU-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; O0-ZU-NEXT: liveins: $edi
+ ; O0-ZU-NEXT: {{ $}}
+ ; O0-ZU-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
+ ; O0-ZU-NEXT: [[SETZUCCr:%[0-9]+]]:gr8 = SETZUCCr 7, implicit $eflags
+ ; O0-ZU-NEXT: [[SUB32rr_ND:%[0-9]+]]:gr32 = SUB32rr_ND $edi, $edi, implicit-def dead $eflags
+ ; O0-ZU-NEXT: JCC_1 %bb.2, 4, implicit $eflags
+ ; O0-ZU-NEXT: {{ $}}
+ ; O0-ZU-NEXT: bb.1:
+ ; O0-ZU-NEXT: successors: %bb.3(0x80000000)
+ ; O0-ZU-NEXT: {{ $}}
+ ; O0-ZU-NEXT: $eax = IMUL32rr_ND $eax, $edi, implicit-def dead $eflags
+ ; O0-ZU-NEXT: JMP_1 %bb.3
+ ; O0-ZU-NEXT: {{ $}}
+ ; O0-ZU-NEXT: bb.2:
+ ; O0-ZU-NEXT: successors: %bb.3(0x80000000)
+ ; O0-ZU-NEXT: {{ $}}
+ ; O0-ZU-NEXT: $eax = SBB32rr $eax, $esi, implicit-def dead $eflags, implicit $eflags
+ ; O0-ZU-NEXT: JMP_1 %bb.3
+ ; O0-ZU-NEXT: {{ $}}
+ ; O0-ZU-NEXT: bb.3:
+ ; O0-ZU-NEXT: TEST8rr [[SETZUCCr]], [[SETZUCCr]], implicit-def $eflags
+ ; O0-ZU-NEXT: $eax = CMOV32rr_ND $edi, [[SUB32rr_ND]], 5, implicit killed $eflags
+ ; O0-ZU-NEXT: RET 0, $al
bb.0:
liveins: $edi
diff --git a/llvm/test/CodeGen/X86/apx/mul-i1024.ll b/llvm/test/CodeGen/X86/apx/mul-i1024.ll
index a5feaeb28cfe7..a29a92176f432 100644
--- a/llvm/test/CodeGen/X86/apx/mul-i1024.ll
+++ b/llvm/test/CodeGen/X86/apx/mul-i1024.ll
@@ -1069,7 +1069,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r23
; EGPR-NDD-NEXT: addq %r27, %rax, %rsi
; EGPR-NDD-NEXT: adcq %rdx, %rcx
-; EGPR-NDD-NEXT: setzub %al
+; EGPR-NDD-NEXT: setb %al
; EGPR-NDD-NEXT: movzbl %al, %r8d
; EGPR-NDD-NEXT: movq %r18, %rax
; EGPR-NDD-NEXT: mulq %r23
@@ -1087,7 +1087,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r23
; EGPR-NDD-NEXT: addq %rax, %rcx
; EGPR-NDD-NEXT: adcq %rdx, %r30
-; EGPR-NDD-NEXT: setzub %al
+; EGPR-NDD-NEXT: setb %al
; EGPR-NDD-NEXT: movzbl %al, %r20d
; EGPR-NDD-NEXT: movq %rdi, %rax
; EGPR-NDD-NEXT: mulq %r23
@@ -1111,7 +1111,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r14
; EGPR-NDD-NEXT: addq %rax, %r19
; EGPR-NDD-NEXT: adcq %rdx, %rsi
-; EGPR-NDD-NEXT: setzub %al
+; EGPR-NDD-NEXT: setb %al
; EGPR-NDD-NEXT: movzbl %al, %r28d
; EGPR-NDD-NEXT: movq %rdi, %rax
; EGPR-NDD-NEXT: mulq %r14
@@ -1123,7 +1123,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: adcq $0, %rdx
; EGPR-NDD-NEXT: addq %rax, %r31
; EGPR-NDD-NEXT: adcq %rdx, %r8
-; EGPR-NDD-NEXT: setzub %al
+; EGPR-NDD-NEXT: setb %al
; EGPR-NDD-NEXT: movzbl %al, %r29d
; EGPR-NDD-NEXT: movq %r25, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; EGPR-NDD-NEXT: movq %r25, %rax
@@ -1139,7 +1139,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r14
; EGPR-NDD-NEXT: addq %rax, %r19
; EGPR-NDD-NEXT: adcq %rdx, %r21
-; EGPR-NDD-NEXT: setzub %al
+; EGPR-NDD-NEXT: setb %al
; EGPR-NDD-NEXT: movzbl %al, %r28d
; EGPR-NDD-NEXT: movq %r18, %rax
; EGPR-NDD-NEXT: mulq %r14
@@ -1161,7 +1161,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r23
; EGPR-NDD-NEXT: addq %rax, %r19
; EGPR-NDD-NEXT: adcq %rdx, %r8
-; EGPR-NDD-NEXT: setzub %al
+; EGPR-NDD-NEXT: setb %al
; EGPR-NDD-NEXT: movzbl %al, %r31d
; EGPR-NDD-NEXT: movq %r9, %rax
; EGPR-NDD-NEXT: mulq %r23
@@ -1180,7 +1180,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: addq %r31, %rax
; EGPR-NDD-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; EGPR-NDD-NEXT: adcq %rdx, %r12
-; EGPR-NDD-NEXT: setzub %r31b
+; EGPR-NDD-NEXT: setb %r31b
; EGPR-NDD-NEXT: movq %r11, %rax
; EGPR-NDD-NEXT: mulq %r23
; EGPR-NDD-NEXT: addq %r12, %rax
@@ -1202,7 +1202,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r14
; EGPR-NDD-NEXT: addq %rax, %r30
; EGPR-NDD-NEXT: adcq %rdx, %r13
-; EGPR-NDD-NEXT: setzub %bpl
+; EGPR-NDD-NEXT: setb %bpl
; EGPR-NDD-NEXT: movq %r11, %rax
; EGPR-NDD-NEXT: mulq %r14
; EGPR-NDD-NEXT: addq %r13, %rax
@@ -1216,7 +1216,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: adcq $0, %rdx
; EGPR-NDD-NEXT: addq %rax, %r8
; EGPR-NDD-NEXT: adcq %rdx, %rbx
-; EGPR-NDD-NEXT: setzub %r19b
+; EGPR-NDD-NEXT: setb %r19b
; EGPR-NDD-NEXT: movq %r10, %r16
; EGPR-NDD-NEXT: movq %r10, %rax
; EGPR-NDD-NEXT: mulq %r26
@@ -1230,7 +1230,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r14
; EGPR-NDD-NEXT: addq %rax, %r30
; EGPR-NDD-NEXT: adcq %rdx, %r12
-; EGPR-NDD-NEXT: setzub %bpl
+; EGPR-NDD-NEXT: setb %bpl
; EGPR-NDD-NEXT: movq %r9, %rax
; EGPR-NDD-NEXT: mulq %r14
; EGPR-NDD-NEXT: addq %r12, %rax
@@ -1266,7 +1266,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r18
; EGPR-NDD-NEXT: addq %r27, %rax, %r21
; EGPR-NDD-NEXT: adcq %rdx, %rcx
-; EGPR-NDD-NEXT: setzub %r8b
+; EGPR-NDD-NEXT: setb %r8b
; EGPR-NDD-NEXT: movq %r9, %rax
; EGPR-NDD-NEXT: mulq %r18
; EGPR-NDD-NEXT: addq %rcx, %rax, %rdi
@@ -1285,7 +1285,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r18
; EGPR-NDD-NEXT: addq %r8, %rax, %r25
; EGPR-NDD-NEXT: adcq %rdx, %r20
-; EGPR-NDD-NEXT: setzub %cl
+; EGPR-NDD-NEXT: setb %cl
; EGPR-NDD-NEXT: movq %r11, %rax
; EGPR-NDD-NEXT: mulq %r18
; EGPR-NDD-NEXT: addq %r20, %rax
@@ -1312,7 +1312,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r17
; EGPR-NDD-NEXT: addq %rax, %r20
; EGPR-NDD-NEXT: adcq %rdx, %rcx
-; EGPR-NDD-NEXT: setzub %sil
+; EGPR-NDD-NEXT: setb %sil
; EGPR-NDD-NEXT: movq %r10, %rax
; EGPR-NDD-NEXT: mulq %r17
; EGPR-NDD-NEXT: addq %rcx, %rax
@@ -1324,7 +1324,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: adcq $0, %rcx
; EGPR-NDD-NEXT: addq %rax, %rdi
; EGPR-NDD-NEXT: adcq %rcx, %r9, %r8
-; EGPR-NDD-NEXT: setzub %sil
+; EGPR-NDD-NEXT: setb %sil
; EGPR-NDD-NEXT: movq %r16, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; EGPR-NDD-NEXT: movq %r16, %rax
; EGPR-NDD-NEXT: mulq %r11
@@ -1339,7 +1339,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r17
; EGPR-NDD-NEXT: addq %rax, %r20
; EGPR-NDD-NEXT: adcq %rdx, %r9
-; EGPR-NDD-NEXT: setzub %cl
+; EGPR-NDD-NEXT: setb %cl
; EGPR-NDD-NEXT: movq %r19, %rax
; EGPR-NDD-NEXT: mulq %r17
; EGPR-NDD-NEXT: addq %r9, %rax
@@ -1366,7 +1366,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: adcq %r8, %r28
; EGPR-NDD-NEXT: adcq %rax, %r29
; EGPR-NDD-NEXT: adcq %rcx, {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Folded Reload
-; EGPR-NDD-NEXT: setzub %r8b
+; EGPR-NDD-NEXT: setb %r8b
; EGPR-NDD-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r13 # 8-byte Reload
; EGPR-NDD-NEXT: movq %r13, %rax
; EGPR-NDD-NEXT: mulq %r30
@@ -1381,7 +1381,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r18
; EGPR-NDD-NEXT: addq %r27, %rax, %rdi
; EGPR-NDD-NEXT: adcq %rdx, %rsi
-; EGPR-NDD-NEXT: setzub %r9b
+; EGPR-NDD-NEXT: setb %r9b
; EGPR-NDD-NEXT: movq %r10, %rax
; EGPR-NDD-NEXT: movq %r10, %r16
; EGPR-NDD-NEXT: mulq %r18
@@ -1402,7 +1402,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r18
; EGPR-NDD-NEXT: addq %r21, %rax, %rbx
; EGPR-NDD-NEXT: adcq %rdx, %r10
-; EGPR-NDD-NEXT: setzub %r31b
+; EGPR-NDD-NEXT: setb %r31b
; EGPR-NDD-NEXT: movq %r12, %rax
; EGPR-NDD-NEXT: mulq %r18
; EGPR-NDD-NEXT: addq %r10, %rax
@@ -1424,7 +1424,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r17
; EGPR-NDD-NEXT: addq %rax, %r20
; EGPR-NDD-NEXT: adcq %rdx, %r31
-; EGPR-NDD-NEXT: setzub %bpl
+; EGPR-NDD-NEXT: setb %bpl
; EGPR-NDD-NEXT: movq %r12, %rax
; EGPR-NDD-NEXT: mulq %r17
; EGPR-NDD-NEXT: addq %r31, %rax
@@ -1436,7 +1436,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: adcq $0, %rdx
; EGPR-NDD-NEXT: addq %rax, %rsi
; EGPR-NDD-NEXT: adcq %rdx, %r9
-; EGPR-NDD-NEXT: setzub %r31b
+; EGPR-NDD-NEXT: setb %r31b
; EGPR-NDD-NEXT: movq %r13, %rax
; EGPR-NDD-NEXT: mulq %r11
; EGPR-NDD-NEXT: movq %rdx, %r20
@@ -1449,7 +1449,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r17
; EGPR-NDD-NEXT: addq %rax, %r20
; EGPR-NDD-NEXT: adcq %rdx, %r12
-; EGPR-NDD-NEXT: setzub %bpl
+; EGPR-NDD-NEXT: setb %bpl
; EGPR-NDD-NEXT: movq %r16, %rax
; EGPR-NDD-NEXT: mulq %r17
; EGPR-NDD-NEXT: addq %r12, %rax
@@ -1491,7 +1491,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r21
; EGPR-NDD-NEXT: addq %rax, %r27
; EGPR-NDD-NEXT: adcq %rdx, %rcx
-; EGPR-NDD-NEXT: setzub %sil
+; EGPR-NDD-NEXT: setb %sil
; EGPR-NDD-NEXT: movq %r14, %rax
; EGPR-NDD-NEXT: mulq %r21
; EGPR-NDD-NEXT: addq %rax, %rcx
@@ -1510,7 +1510,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: addq %r29, %rax
; EGPR-NDD-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; EGPR-NDD-NEXT: adcq %rdx, %rdi
-; EGPR-NDD-NEXT: setzub %r8b
+; EGPR-NDD-NEXT: setb %r8b
; EGPR-NDD-NEXT: movq %r23, %rax
; EGPR-NDD-NEXT: mulq %r21
; EGPR-NDD-NEXT: addq %rdi, %rax
@@ -1534,7 +1534,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %rbx
; EGPR-NDD-NEXT: addq %rax, %r28
; EGPR-NDD-NEXT: adcq %rdx, %r9
-; EGPR-NDD-NEXT: setzub %r10b
+; EGPR-NDD-NEXT: setb %r10b
; EGPR-NDD-NEXT: movq %r23, %rax
; EGPR-NDD-NEXT: mulq %rbx
; EGPR-NDD-NEXT: addq %r9, %rax
@@ -1547,7 +1547,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: adcq $0, %rdx
; EGPR-NDD-NEXT: addq %rax, %rcx
; EGPR-NDD-NEXT: adcq %rdx, %rsi
-; EGPR-NDD-NEXT: setzub %dil
+; EGPR-NDD-NEXT: setb %dil
; EGPR-NDD-NEXT: movq %r26, %rax
; EGPR-NDD-NEXT: mulq %r8
; EGPR-NDD-NEXT: movq %rdx, %r28
@@ -1560,7 +1560,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %rbx
; EGPR-NDD-NEXT: addq %rax, %r28
; EGPR-NDD-NEXT: adcq %rdx, %r9
-; EGPR-NDD-NEXT: setzub %r10b
+; EGPR-NDD-NEXT: setb %r10b
; EGPR-NDD-NEXT: movq %r14, %rax
; EGPR-NDD-NEXT: mulq %rbx
; EGPR-NDD-NEXT: addq %r9, %rax
@@ -1598,7 +1598,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r18
; EGPR-NDD-NEXT: addq %rax, %rcx
; EGPR-NDD-NEXT: adcq %rdx, %rdi
-; EGPR-NDD-NEXT: setzub %r9b
+; EGPR-NDD-NEXT: setb %r9b
; EGPR-NDD-NEXT: movq %r21, %rax
; EGPR-NDD-NEXT: mulq %r18
; EGPR-NDD-NEXT: addq %rdi, %rax
@@ -1636,7 +1636,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r23
; EGPR-NDD-NEXT: addq %rax, %r25
; EGPR-NDD-NEXT: adcq %rdx, %r10
-; EGPR-NDD-NEXT: setzub %r11b
+; EGPR-NDD-NEXT: setb %r11b
; EGPR-NDD-NEXT: movq %rdi, %rax
; EGPR-NDD-NEXT: mulq %r23
; EGPR-NDD-NEXT: addq %r10, %rax
@@ -1668,7 +1668,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r23
; EGPR-NDD-NEXT: addq %rax, %rdi
; EGPR-NDD-NEXT: adcq %rdx, %rcx
-; EGPR-NDD-NEXT: setzub %sil
+; EGPR-NDD-NEXT: setb %sil
; EGPR-NDD-NEXT: movq %r22, %rax
; EGPR-NDD-NEXT: mulq %r23
; EGPR-NDD-NEXT: addq %rax, %rcx
@@ -1688,7 +1688,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r23
; EGPR-NDD-NEXT: addq %r31, %rax, %r29
; EGPR-NDD-NEXT: adcq %rdx, %r8
-; EGPR-NDD-NEXT: setzub %r9b
+; EGPR-NDD-NEXT: setb %r9b
; EGPR-NDD-NEXT: movq %r25, %rax
; EGPR-NDD-NEXT: mulq %r23
; EGPR-NDD-NEXT: addq %r8, %rax
@@ -1712,7 +1712,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r11
; EGPR-NDD-NEXT: addq %r30, %rax, %r27
; EGPR-NDD-NEXT: adcq %rdx, %r8
-; EGPR-NDD-NEXT: setzub %r9b
+; EGPR-NDD-NEXT: setb %r9b
; EGPR-NDD-NEXT: movq %r25, %rax
; EGPR-NDD-NEXT: mulq %r11
; EGPR-NDD-NEXT: addq %r8, %rax
@@ -1724,7 +1724,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: adcq $0, %rdx
; EGPR-NDD-NEXT: addq %rax, %rcx
; EGPR-NDD-NEXT: adcq %rdx, %rsi
-; EGPR-NDD-NEXT: setzub %dil
+; EGPR-NDD-NEXT: setb %dil
; EGPR-NDD-NEXT: movq %r24, %rax
; EGPR-NDD-NEXT: mulq %r10
; EGPR-NDD-NEXT: movq %rdx, %r30
@@ -1737,7 +1737,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r11
; EGPR-NDD-NEXT: addq %r30, %rax, %r19
; EGPR-NDD-NEXT: adcq %rdx, %r8
-; EGPR-NDD-NEXT: setzub %r9b
+; EGPR-NDD-NEXT: setb %r9b
; EGPR-NDD-NEXT: movq %r22, %rax
; EGPR-NDD-NEXT: mulq %r11
; EGPR-NDD-NEXT: addq %r8, %rax
@@ -1778,7 +1778,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r8
; EGPR-NDD-NEXT: addq %rax, %r11
; EGPR-NDD-NEXT: adcq %rdx, %r16
-; EGPR-NDD-NEXT: setzub %r17b
+; EGPR-NDD-NEXT: setb %r17b
; EGPR-NDD-NEXT: movq %r23, %rax
; EGPR-NDD-NEXT: mulq %r8
; EGPR-NDD-NEXT: addq %r16, %rax
@@ -1817,7 +1817,7 @@ define void @test_1024(ptr %a, ptr %b, ptr %out) nounwind {
; EGPR-NDD-NEXT: mulq %r25
; EGPR-NDD-NEXT: addq %rax, %r8
; EGPR-NDD-NEXT: adcq %rdx, %r22
-; EGPR-NDD-NEXT: setzub %r23b
+; EGPR-NDD-NEXT: setb %r23b
; EGPR-NDD-NEXT: movq %r24, %rax
; EGPR-NDD-NEXT: mulq %r25
; EGPR-NDD-NEXT: addq %r22, %rax
diff --git a/llvm/test/CodeGen/X86/apx/or.ll b/llvm/test/CodeGen/X86/apx/or.ll
index a2242eadeff69..12ee5fc3404db 100644
--- a/llvm/test/CodeGen/X86/apx/or.ll
+++ b/llvm/test/CodeGen/X86/apx/or.ll
@@ -431,7 +431,7 @@ define i1 @orflag8rr(i8 %a, i8 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: notb %sil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xf6,0xd6]
; CHECK-NEXT: orb %al, %dil, %cl # encoding: [0x62,0xf4,0x74,0x18,0x08,0xc7]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -440,7 +440,7 @@ define i1 @orflag8rr(i8 %a, i8 %b) {
; NF: # %bb.0:
; NF-NEXT: notb %sil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xf6,0xd6]
; NF-NEXT: orb %al, %dil, %cl # encoding: [0x62,0xf4,0x74,0x18,0x08,0xc7]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -456,7 +456,7 @@ define i1 @orflag16rr(i16 %a, i16 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: notw %si, %ax # encoding: [0x62,0xf4,0x7d,0x18,0xf7,0xd6]
; CHECK-NEXT: orw %ax, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x09,0xc7]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -465,7 +465,7 @@ define i1 @orflag16rr(i16 %a, i16 %b) {
; NF: # %bb.0:
; NF-NEXT: notw %si, %ax # encoding: [0x62,0xf4,0x7d,0x18,0xf7,0xd6]
; NF-NEXT: orw %ax, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x09,0xc7]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -480,7 +480,7 @@ define i1 @orflag32rr(i32 %a, i32 %b) {
; CHECK-LABEL: orflag32rr:
; CHECK: # %bb.0:
; CHECK-NEXT: orl %edi, %esi # EVEX TO LEGACY Compression encoding: [0x09,0xfe]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movl %esi, d64(%rip) # encoding: [0x89,0x35,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -488,7 +488,7 @@ define i1 @orflag32rr(i32 %a, i32 %b) {
; NF-LABEL: orflag32rr:
; NF: # %bb.0:
; NF-NEXT: orl %edi, %esi # EVEX TO LEGACY Compression encoding: [0x09,0xfe]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movl %esi, d64(%rip) # encoding: [0x89,0x35,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -502,7 +502,7 @@ define i1 @orflag64rr(i64 %a, i64 %b) {
; CHECK-LABEL: orflag64rr:
; CHECK: # %bb.0:
; CHECK-NEXT: orq %rdi, %rsi # EVEX TO LEGACY Compression encoding: [0x48,0x09,0xfe]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movq %rsi, d64(%rip) # encoding: [0x48,0x89,0x35,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -510,7 +510,7 @@ define i1 @orflag64rr(i64 %a, i64 %b) {
; NF-LABEL: orflag64rr:
; NF: # %bb.0:
; NF-NEXT: orq %rdi, %rsi # EVEX TO LEGACY Compression encoding: [0x48,0x09,0xfe]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movq %rsi, d64(%rip) # encoding: [0x48,0x89,0x35,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -525,7 +525,7 @@ define i1 @orflag8rm(ptr %ptr, i8 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: notb %sil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xf6,0xd6]
; CHECK-NEXT: orb (%rdi), %al, %cl # encoding: [0x62,0xf4,0x74,0x18,0x0a,0x07]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -534,7 +534,7 @@ define i1 @orflag8rm(ptr %ptr, i8 %b) {
; NF: # %bb.0:
; NF-NEXT: notb %sil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xf6,0xd6]
; NF-NEXT: orb (%rdi), %al, %cl # encoding: [0x62,0xf4,0x74,0x18,0x0a,0x07]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -551,7 +551,7 @@ define i1 @orflag16rm(ptr %ptr, i16 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: notw %si, %ax # encoding: [0x62,0xf4,0x7d,0x18,0xf7,0xd6]
; CHECK-NEXT: orw (%rdi), %ax, %cx # encoding: [0x62,0xf4,0x75,0x18,0x0b,0x07]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -560,7 +560,7 @@ define i1 @orflag16rm(ptr %ptr, i16 %b) {
; NF: # %bb.0:
; NF-NEXT: notw %si, %ax # encoding: [0x62,0xf4,0x7d,0x18,0xf7,0xd6]
; NF-NEXT: orw (%rdi), %ax, %cx # encoding: [0x62,0xf4,0x75,0x18,0x0b,0x07]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -576,7 +576,7 @@ define i1 @orflag32rm(ptr %ptr, i32 %b) {
; CHECK-LABEL: orflag32rm:
; CHECK: # %bb.0:
; CHECK-NEXT: orl (%rdi), %esi # EVEX TO LEGACY Compression encoding: [0x0b,0x37]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movl %esi, d64(%rip) # encoding: [0x89,0x35,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -584,7 +584,7 @@ define i1 @orflag32rm(ptr %ptr, i32 %b) {
; NF-LABEL: orflag32rm:
; NF: # %bb.0:
; NF-NEXT: orl (%rdi), %esi # EVEX TO LEGACY Compression encoding: [0x0b,0x37]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movl %esi, d64(%rip) # encoding: [0x89,0x35,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -599,7 +599,7 @@ define i1 @orflag64rm(ptr %ptr, i64 %b) {
; CHECK-LABEL: orflag64rm:
; CHECK: # %bb.0:
; CHECK-NEXT: orq (%rdi), %rsi # EVEX TO LEGACY Compression encoding: [0x48,0x0b,0x37]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movq %rsi, d64(%rip) # encoding: [0x48,0x89,0x35,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -607,7 +607,7 @@ define i1 @orflag64rm(ptr %ptr, i64 %b) {
; NF-LABEL: orflag64rm:
; NF: # %bb.0:
; NF-NEXT: orq (%rdi), %rsi # EVEX TO LEGACY Compression encoding: [0x48,0x0b,0x37]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movq %rsi, d64(%rip) # encoding: [0x48,0x89,0x35,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -622,7 +622,7 @@ define i1 @orflag8ri(i8 %a) {
; CHECK-LABEL: orflag8ri:
; CHECK: # %bb.0:
; CHECK-NEXT: orb $-124, %dil, %cl # encoding: [0x62,0xf4,0x74,0x18,0x80,0xcf,0x84]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -630,7 +630,7 @@ define i1 @orflag8ri(i8 %a) {
; NF-LABEL: orflag8ri:
; NF: # %bb.0:
; NF-NEXT: orb $-124, %dil, %cl # encoding: [0x62,0xf4,0x74,0x18,0x80,0xcf,0x84]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -646,7 +646,7 @@ define i1 @orflag16ri(i16 %a) {
; CHECK: # %bb.0:
; CHECK-NEXT: orw $-1235, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x81,0xcf,0x2d,0xfb]
; CHECK-NEXT: # imm = 0xFB2D
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -655,7 +655,7 @@ define i1 @orflag16ri(i16 %a) {
; NF: # %bb.0:
; NF-NEXT: orw $-1235, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x81,0xcf,0x2d,0xfb]
; NF-NEXT: # imm = 0xFB2D
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -671,7 +671,7 @@ define i1 @orflag32ri(i32 %a) {
; CHECK: # %bb.0:
; CHECK-NEXT: orl $123456, %edi # EVEX TO LEGACY Compression encoding: [0x81,0xcf,0x40,0xe2,0x01,0x00]
; CHECK-NEXT: # imm = 0x1E240
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movl %edi, d64(%rip) # encoding: [0x89,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -680,7 +680,7 @@ define i1 @orflag32ri(i32 %a) {
; NF: # %bb.0:
; NF-NEXT: orl $123456, %edi # EVEX TO LEGACY Compression encoding: [0x81,0xcf,0x40,0xe2,0x01,0x00]
; NF-NEXT: # imm = 0x1E240
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movl %edi, d64(%rip) # encoding: [0x89,0x3d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -695,7 +695,7 @@ define i1 @orflag64ri(i64 %a) {
; CHECK: # %bb.0:
; CHECK-NEXT: orq $123456, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x81,0xcf,0x40,0xe2,0x01,0x00]
; CHECK-NEXT: # imm = 0x1E240
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -704,7 +704,7 @@ define i1 @orflag64ri(i64 %a) {
; NF: # %bb.0:
; NF-NEXT: orq $123456, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x81,0xcf,0x40,0xe2,0x01,0x00]
; NF-NEXT: # imm = 0x1E240
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -718,7 +718,7 @@ define i1 @orflag16ri8(i16 %a) {
; CHECK-LABEL: orflag16ri8:
; CHECK: # %bb.0:
; CHECK-NEXT: orw $-124, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x83,0xcf,0x84]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -726,7 +726,7 @@ define i1 @orflag16ri8(i16 %a) {
; NF-LABEL: orflag16ri8:
; NF: # %bb.0:
; NF-NEXT: orw $-124, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x83,0xcf,0x84]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -741,7 +741,7 @@ define i1 @orflag32ri8(i32 %a) {
; CHECK-LABEL: orflag32ri8:
; CHECK: # %bb.0:
; CHECK-NEXT: orl $123, %edi # EVEX TO LEGACY Compression encoding: [0x83,0xcf,0x7b]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movl %edi, d64(%rip) # encoding: [0x89,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -749,7 +749,7 @@ define i1 @orflag32ri8(i32 %a) {
; NF-LABEL: orflag32ri8:
; NF: # %bb.0:
; NF-NEXT: orl $123, %edi # EVEX TO LEGACY Compression encoding: [0x83,0xcf,0x7b]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movl %edi, d64(%rip) # encoding: [0x89,0x3d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -763,7 +763,7 @@ define i1 @orflag64ri8(i64 %a) {
; CHECK-LABEL: orflag64ri8:
; CHECK: # %bb.0:
; CHECK-NEXT: orq $123, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x83,0xcf,0x7b]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -771,7 +771,7 @@ define i1 @orflag64ri8(i64 %a) {
; NF-LABEL: orflag64ri8:
; NF: # %bb.0:
; NF-NEXT: orq $123, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x83,0xcf,0x7b]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
diff --git a/llvm/test/CodeGen/X86/apx/xor.ll b/llvm/test/CodeGen/X86/apx/xor.ll
index cf85d18318da4..e083c6580398c 100644
--- a/llvm/test/CodeGen/X86/apx/xor.ll
+++ b/llvm/test/CodeGen/X86/apx/xor.ll
@@ -431,7 +431,7 @@ define i1 @xorflag8rr(i8 %a, i8 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %edi, %esi # EVEX TO LEGACY Compression encoding: [0x31,0xfe]
; CHECK-NEXT: xorb $-1, %sil, %cl # encoding: [0x62,0xf4,0x74,0x18,0x80,0xf6,0xff]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -440,7 +440,7 @@ define i1 @xorflag8rr(i8 %a, i8 %b) {
; NF: # %bb.0:
; NF-NEXT: xorl %edi, %esi # EVEX TO LEGACY Compression encoding: [0x31,0xfe]
; NF-NEXT: xorb $-1, %sil, %cl # encoding: [0x62,0xf4,0x74,0x18,0x80,0xf6,0xff]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -456,7 +456,7 @@ define i1 @xorflag16rr(i16 %a, i16 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %edi, %esi # EVEX TO LEGACY Compression encoding: [0x31,0xfe]
; CHECK-NEXT: xorw $-1, %si, %cx # encoding: [0x62,0xf4,0x75,0x18,0x83,0xf6,0xff]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -465,7 +465,7 @@ define i1 @xorflag16rr(i16 %a, i16 %b) {
; NF: # %bb.0:
; NF-NEXT: xorl %edi, %esi # EVEX TO LEGACY Compression encoding: [0x31,0xfe]
; NF-NEXT: xorw $-1, %si, %cx # encoding: [0x62,0xf4,0x75,0x18,0x83,0xf6,0xff]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -480,7 +480,7 @@ define i1 @xorflag32rr(i32 %a, i32 %b) {
; CHECK-LABEL: xorflag32rr:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %edi, %esi # EVEX TO LEGACY Compression encoding: [0x31,0xfe]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movl %esi, d64(%rip) # encoding: [0x89,0x35,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -488,7 +488,7 @@ define i1 @xorflag32rr(i32 %a, i32 %b) {
; NF-LABEL: xorflag32rr:
; NF: # %bb.0:
; NF-NEXT: xorl %edi, %esi # EVEX TO LEGACY Compression encoding: [0x31,0xfe]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movl %esi, d64(%rip) # encoding: [0x89,0x35,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -502,7 +502,7 @@ define i1 @xorflag64rr(i64 %a, i64 %b) {
; CHECK-LABEL: xorflag64rr:
; CHECK: # %bb.0:
; CHECK-NEXT: xorq %rdi, %rsi # EVEX TO LEGACY Compression encoding: [0x48,0x31,0xfe]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movq %rsi, d64(%rip) # encoding: [0x48,0x89,0x35,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -510,7 +510,7 @@ define i1 @xorflag64rr(i64 %a, i64 %b) {
; NF-LABEL: xorflag64rr:
; NF: # %bb.0:
; NF-NEXT: xorq %rdi, %rsi # EVEX TO LEGACY Compression encoding: [0x48,0x31,0xfe]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movq %rsi, d64(%rip) # encoding: [0x48,0x89,0x35,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -525,7 +525,7 @@ define i1 @xorflag8rm(ptr %ptr, i8 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: xorb (%rdi), %sil, %al # encoding: [0x62,0xf4,0x7c,0x18,0x32,0x37]
; CHECK-NEXT: xorb $-1, %al, %cl # encoding: [0x62,0xf4,0x74,0x18,0x80,0xf0,0xff]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -534,7 +534,7 @@ define i1 @xorflag8rm(ptr %ptr, i8 %b) {
; NF: # %bb.0:
; NF-NEXT: {nf} xorb (%rdi), %sil, %al # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x32,0x37]
; NF-NEXT: xorb $-1, %al, %cl # encoding: [0x62,0xf4,0x74,0x18,0x80,0xf0,0xff]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -551,7 +551,7 @@ define i1 @xorflag16rm(ptr %ptr, i16 %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: xorw (%rdi), %si, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x33,0x37]
; CHECK-NEXT: xorw $-1, %ax, %cx # encoding: [0x62,0xf4,0x75,0x18,0x83,0xf0,0xff]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -560,7 +560,7 @@ define i1 @xorflag16rm(ptr %ptr, i16 %b) {
; NF: # %bb.0:
; NF-NEXT: {nf} xorw (%rdi), %si, %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0x33,0x37]
; NF-NEXT: xorw $-1, %ax, %cx # encoding: [0x62,0xf4,0x75,0x18,0x83,0xf0,0xff]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -576,7 +576,7 @@ define i1 @xorflag32rm(ptr %ptr, i32 %b) {
; CHECK-LABEL: xorflag32rm:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl (%rdi), %esi # EVEX TO LEGACY Compression encoding: [0x33,0x37]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movl %esi, d64(%rip) # encoding: [0x89,0x35,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -584,7 +584,7 @@ define i1 @xorflag32rm(ptr %ptr, i32 %b) {
; NF-LABEL: xorflag32rm:
; NF: # %bb.0:
; NF-NEXT: xorl (%rdi), %esi # EVEX TO LEGACY Compression encoding: [0x33,0x37]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movl %esi, d64(%rip) # encoding: [0x89,0x35,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -599,7 +599,7 @@ define i1 @xorflag64rm(ptr %ptr, i64 %b) {
; CHECK-LABEL: xorflag64rm:
; CHECK: # %bb.0:
; CHECK-NEXT: xorq (%rdi), %rsi # EVEX TO LEGACY Compression encoding: [0x48,0x33,0x37]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movq %rsi, d64(%rip) # encoding: [0x48,0x89,0x35,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -607,7 +607,7 @@ define i1 @xorflag64rm(ptr %ptr, i64 %b) {
; NF-LABEL: xorflag64rm:
; NF: # %bb.0:
; NF-NEXT: xorq (%rdi), %rsi # EVEX TO LEGACY Compression encoding: [0x48,0x33,0x37]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movq %rsi, d64(%rip) # encoding: [0x48,0x89,0x35,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -622,7 +622,7 @@ define i1 @xorflag8ri(i8 %a) {
; CHECK-LABEL: xorflag8ri:
; CHECK: # %bb.0:
; CHECK-NEXT: xorb $-124, %dil, %cl # encoding: [0x62,0xf4,0x74,0x18,0x80,0xf7,0x84]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -630,7 +630,7 @@ define i1 @xorflag8ri(i8 %a) {
; NF-LABEL: xorflag8ri:
; NF: # %bb.0:
; NF-NEXT: xorb $-124, %dil, %cl # encoding: [0x62,0xf4,0x74,0x18,0x80,0xf7,0x84]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movb %cl, d64(%rip) # encoding: [0x88,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -646,7 +646,7 @@ define i1 @xorflag16ri(i16 %a) {
; CHECK: # %bb.0:
; CHECK-NEXT: xorw $-1235, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x81,0xf7,0x2d,0xfb]
; CHECK-NEXT: # imm = 0xFB2D
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -655,7 +655,7 @@ define i1 @xorflag16ri(i16 %a) {
; NF: # %bb.0:
; NF-NEXT: xorw $-1235, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x81,0xf7,0x2d,0xfb]
; NF-NEXT: # imm = 0xFB2D
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -671,7 +671,7 @@ define i1 @xorflag32ri(i32 %a) {
; CHECK: # %bb.0:
; CHECK-NEXT: xorl $123456, %edi # EVEX TO LEGACY Compression encoding: [0x81,0xf7,0x40,0xe2,0x01,0x00]
; CHECK-NEXT: # imm = 0x1E240
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movl %edi, d64(%rip) # encoding: [0x89,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -680,7 +680,7 @@ define i1 @xorflag32ri(i32 %a) {
; NF: # %bb.0:
; NF-NEXT: xorl $123456, %edi # EVEX TO LEGACY Compression encoding: [0x81,0xf7,0x40,0xe2,0x01,0x00]
; NF-NEXT: # imm = 0x1E240
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movl %edi, d64(%rip) # encoding: [0x89,0x3d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -695,7 +695,7 @@ define i1 @xorflag64ri(i64 %a) {
; CHECK: # %bb.0:
; CHECK-NEXT: xorq $123456, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x81,0xf7,0x40,0xe2,0x01,0x00]
; CHECK-NEXT: # imm = 0x1E240
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -704,7 +704,7 @@ define i1 @xorflag64ri(i64 %a) {
; NF: # %bb.0:
; NF-NEXT: xorq $123456, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x81,0xf7,0x40,0xe2,0x01,0x00]
; NF-NEXT: # imm = 0x1E240
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -718,7 +718,7 @@ define i1 @xorflag16ri8(i16 %a) {
; CHECK-LABEL: xorflag16ri8:
; CHECK: # %bb.0:
; CHECK-NEXT: xorw $-124, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x83,0xf7,0x84]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -726,7 +726,7 @@ define i1 @xorflag16ri8(i16 %a) {
; NF-LABEL: xorflag16ri8:
; NF: # %bb.0:
; NF-NEXT: xorw $-124, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x83,0xf7,0x84]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -741,7 +741,7 @@ define i1 @xorflag32ri8(i32 %a) {
; CHECK-LABEL: xorflag32ri8:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl $123, %edi # EVEX TO LEGACY Compression encoding: [0x83,0xf7,0x7b]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movl %edi, d64(%rip) # encoding: [0x89,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -749,7 +749,7 @@ define i1 @xorflag32ri8(i32 %a) {
; NF-LABEL: xorflag32ri8:
; NF: # %bb.0:
; NF-NEXT: xorl $123, %edi # EVEX TO LEGACY Compression encoding: [0x83,0xf7,0x7b]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movl %edi, d64(%rip) # encoding: [0x89,0x3d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
@@ -763,7 +763,7 @@ define i1 @xorflag64ri8(i64 %a) {
; CHECK-LABEL: xorflag64ri8:
; CHECK: # %bb.0:
; CHECK-NEXT: xorq $123, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x83,0xf7,0x7b]
-; CHECK-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; CHECK-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; CHECK-NEXT: retq # encoding: [0xc3]
@@ -771,7 +771,7 @@ define i1 @xorflag64ri8(i64 %a) {
; NF-LABEL: xorflag64ri8:
; NF: # %bb.0:
; NF-NEXT: xorq $123, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x83,0xf7,0x7b]
-; NF-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NF-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NF-NEXT: retq # encoding: [0xc3]
diff --git a/llvm/test/CodeGen/X86/cmp.ll b/llvm/test/CodeGen/X86/cmp.ll
index 4c0292ccc70ac..7fd1e20169d87 100644
--- a/llvm/test/CodeGen/X86/cmp.ll
+++ b/llvm/test/CodeGen/X86/cmp.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,NO-NDD
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ndd -show-mc-encoding | FileCheck --check-prefixes=CHECK,NDD %s
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ndd,+zu -show-mc-encoding | FileCheck --check-prefixes=CHECK,NDD-ZU %s
-; RUN: llc -O0 < %s -mtriple=x86_64-unknown-unknown -mattr=+ndd,+zu -show-mc-encoding | FileCheck --check-prefix=O0-NDD-ZU %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+zu -show-mc-encoding | FileCheck --check-prefixes=CHECK,ZU %s
+; RUN: llc -O0 < %s -mtriple=x86_64-unknown-unknown -mattr=+zu -show-mc-encoding | FileCheck --check-prefix=O0-ZU %s
@d = dso_local global i8 0, align 1
@d64 = dso_local global i64 0
@@ -20,17 +20,17 @@ define i32 @test1(i32 %X, ptr %y) nounwind {
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; CHECK-NEXT: retq # encoding: [0xc3]
;
-; O0-NDD-ZU-LABEL: test1:
-; O0-NDD-ZU: # %bb.0: # %entry
-; O0-NDD-ZU-NEXT: cmpl $0, (%rsi) # encoding: [0x83,0x3e,0x00]
-; O0-NDD-ZU-NEXT: je .LBB0_2 # encoding: [0x74,A]
-; O0-NDD-ZU-NEXT: # fixup A - offset: 1, value: .LBB0_2-1, kind: FK_PCRel_1
-; O0-NDD-ZU-NEXT: # %bb.1: # %cond_true
-; O0-NDD-ZU-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
-; O0-NDD-ZU-NEXT: .LBB0_2: # %ReturnBlock
-; O0-NDD-ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; O0-ZU-LABEL: test1:
+; O0-ZU: # %bb.0: # %entry
+; O0-ZU-NEXT: cmpl $0, (%rsi) # encoding: [0x83,0x3e,0x00]
+; O0-ZU-NEXT: je .LBB0_2 # encoding: [0x74,A]
+; O0-ZU-NEXT: # fixup A - offset: 1, value: .LBB0_2-1, kind: FK_PCRel_1
+; O0-ZU-NEXT: # %bb.1: # %cond_true
+; O0-ZU-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
+; O0-ZU-NEXT: .LBB0_2: # %ReturnBlock
+; O0-ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
entry:
%tmp = load i32, ptr %y
%tmp.upgrd.1 = icmp eq i32 %tmp, 0
@@ -57,18 +57,19 @@ define i32 @test2(i32 %X, ptr %y) nounwind {
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; CHECK-NEXT: retq # encoding: [0xc3]
;
-; O0-NDD-ZU-LABEL: test2:
-; O0-NDD-ZU: # %bb.0: # %entry
-; O0-NDD-ZU-NEXT: shll $3, (%rsi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0xc1,0x26,0x03]
-; O0-NDD-ZU-NEXT: cmpl $0, %eax # encoding: [0x83,0xf8,0x00]
-; O0-NDD-ZU-NEXT: je .LBB1_2 # encoding: [0x74,A]
-; O0-NDD-ZU-NEXT: # fixup A - offset: 1, value: .LBB1_2-1, kind: FK_PCRel_1
-; O0-NDD-ZU-NEXT: # %bb.1: # %cond_true
-; O0-NDD-ZU-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
-; O0-NDD-ZU-NEXT: .LBB1_2: # %ReturnBlock
-; O0-NDD-ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; O0-ZU-LABEL: test2:
+; O0-ZU: # %bb.0: # %entry
+; O0-ZU-NEXT: movl (%rsi), %eax # encoding: [0x8b,0x06]
+; O0-ZU-NEXT: shll $3, %eax # encoding: [0xc1,0xe0,0x03]
+; O0-ZU-NEXT: cmpl $0, %eax # encoding: [0x83,0xf8,0x00]
+; O0-ZU-NEXT: je .LBB1_2 # encoding: [0x74,A]
+; O0-ZU-NEXT: # fixup A - offset: 1, value: .LBB1_2-1, kind: FK_PCRel_1
+; O0-ZU-NEXT: # %bb.1: # %cond_true
+; O0-ZU-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
+; O0-ZU-NEXT: .LBB1_2: # %ReturnBlock
+; O0-ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
entry:
%tmp = load i32, ptr %y
%tmp1 = shl i32 %tmp, 3
@@ -95,19 +96,20 @@ define i8 @test2b(i8 %X, ptr %y) nounwind {
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; CHECK-NEXT: retq # encoding: [0xc3]
;
-; O0-NDD-ZU-LABEL: test2b:
-; O0-NDD-ZU: # %bb.0: # %entry
-; O0-NDD-ZU-NEXT: shlb $3, (%rsi), %al # encoding: [0x62,0xf4,0x7c,0x18,0xc0,0x26,0x03]
-; O0-NDD-ZU-NEXT: cmpb $0, %al # encoding: [0x3c,0x00]
-; O0-NDD-ZU-NEXT: je .LBB2_2 # encoding: [0x74,A]
-; O0-NDD-ZU-NEXT: # fixup A - offset: 1, value: .LBB2_2-1, kind: FK_PCRel_1
-; O0-NDD-ZU-NEXT: # %bb.1: # %cond_true
-; O0-NDD-ZU-NEXT: movb $1, %al # encoding: [0xb0,0x01]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
-; O0-NDD-ZU-NEXT: .LBB2_2: # %ReturnBlock
-; O0-NDD-ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; O0-NDD-ZU-NEXT: # kill: def $al killed $al killed $eax
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; O0-ZU-LABEL: test2b:
+; O0-ZU: # %bb.0: # %entry
+; O0-ZU-NEXT: movb (%rsi), %al # encoding: [0x8a,0x06]
+; O0-ZU-NEXT: shlb $3, %al # encoding: [0xc0,0xe0,0x03]
+; O0-ZU-NEXT: cmpb $0, %al # encoding: [0x3c,0x00]
+; O0-ZU-NEXT: je .LBB2_2 # encoding: [0x74,A]
+; O0-ZU-NEXT: # fixup A - offset: 1, value: .LBB2_2-1, kind: FK_PCRel_1
+; O0-ZU-NEXT: # %bb.1: # %cond_true
+; O0-ZU-NEXT: movb $1, %al # encoding: [0xb0,0x01]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
+; O0-ZU-NEXT: .LBB2_2: # %ReturnBlock
+; O0-ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; O0-ZU-NEXT: # kill: def $al killed $al killed $eax
+; O0-ZU-NEXT: retq # encoding: [0xc3]
entry:
%tmp = load i8, ptr %y
%tmp1 = shl i8 %tmp, 3
@@ -131,25 +133,30 @@ define i64 @test3(i64 %x) nounwind {
;
; NDD-LABEL: test3:
; NDD: # %bb.0: # %entry
+; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff]
-; NDD-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
;
+; ZU-LABEL: test3:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff]
+; ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: test3:
+; O0-ZU: # %bb.0: # %entry
+; O0-ZU-NEXT: cmpq $0, %rdi # encoding: [0x48,0x83,0xff,0x00]
+; O0-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; O0-ZU-NEXT: andb $1, %al # encoding: [0x24,0x01]
+; O0-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-ZU-NEXT: # kill: def $rax killed $eax
+; O0-ZU-NEXT: retq # encoding: [0xc3]
; NDD-ZU-LABEL: test3:
; NDD-ZU: # %bb.0: # %entry
; NDD-ZU-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff]
; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: test3:
-; O0-NDD-ZU: # %bb.0: # %entry
-; O0-NDD-ZU-NEXT: cmpq $0, %rdi # encoding: [0x48,0x83,0xff,0x00]
-; O0-NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
-; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
-; O0-NDD-ZU-NEXT: # kill: def $rax killed $eax
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
entry:
%t = icmp eq i64 %x, 0
%r = zext i1 %t to i64
@@ -166,25 +173,25 @@ define i64 @test4(i64 %x) nounwind {
;
; NDD-LABEL: test4:
; NDD: # %bb.0:
+; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff]
-; NDD-NEXT: setzule %al # encoding: [0x62,0xf4,0x7f,0x18,0x4e,0xc0]
-; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; NDD-NEXT: setle %al # encoding: [0x0f,0x9e,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: test4:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff]
-; NDD-ZU-NEXT: setzule %al # encoding: [0x62,0xf4,0x7f,0x18,0x4e,0xc0]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: test4:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: cmpq $1, %rdi # encoding: [0x48,0x83,0xff,0x01]
-; O0-NDD-ZU-NEXT: setzul %al # encoding: [0x62,0xf4,0x7f,0x18,0x4c,0xc0]
-; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
-; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
-; O0-NDD-ZU-NEXT: # kill: def $rax killed $eax
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: test4:
+; ZU: # %bb.0:
+; ZU-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff]
+; ZU-NEXT: setzule %al # encoding: [0x62,0xf4,0x7f,0x18,0x4e,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: test4:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: cmpq $1, %rdi # encoding: [0x48,0x83,0xff,0x01]
+; O0-ZU-NEXT: setzul %al # encoding: [0x62,0xf4,0x7f,0x18,0x4c,0xc0]
+; O0-ZU-NEXT: andb $1, %al # encoding: [0x24,0x01]
+; O0-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-ZU-NEXT: # kill: def $rax killed $eax
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%t = icmp slt i64 %x, 1
%r = zext i1 %t to i64
ret i64 %r
@@ -211,33 +218,33 @@ define i32 @test5(double %A) nounwind {
; CHECK-NEXT: # encoding: [0xeb,A]
; CHECK-NEXT: # fixup A - offset: 1, value: foo at PLT-1, kind: FK_PCRel_1
;
-; O0-NDD-ZU-LABEL: test5:
-; O0-NDD-ZU: # %bb.0: # %entry
-; O0-NDD-ZU-NEXT: movsd {{.*#+}} xmm1 = [1.5E+2,0.0E+0]
-; O0-NDD-ZU-NEXT: # encoding: [0xf2,0x0f,0x10,0x0d,A,A,A,A]
-; O0-NDD-ZU-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; O0-NDD-ZU-NEXT: ucomisd %xmm1, %xmm0 # encoding: [0x66,0x0f,0x2e,0xc1]
-; O0-NDD-ZU-NEXT: setzua %al # encoding: [0x62,0xf4,0x7f,0x18,0x47,0xc0]
-; O0-NDD-ZU-NEXT: movsd {{.*#+}} xmm1 = [7.5E+1,0.0E+0]
-; O0-NDD-ZU-NEXT: # encoding: [0xf2,0x0f,0x10,0x0d,A,A,A,A]
-; O0-NDD-ZU-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
-; O0-NDD-ZU-NEXT: ucomisd %xmm1, %xmm0 # encoding: [0x66,0x0f,0x2e,0xc1]
-; O0-NDD-ZU-NEXT: setzub %cl # encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc1]
-; O0-NDD-ZU-NEXT: orb %cl, %al # EVEX TO LEGACY Compression encoding: [0x08,0xc8]
-; O0-NDD-ZU-NEXT: testb $1, %al # encoding: [0xa8,0x01]
-; O0-NDD-ZU-NEXT: jne .LBB5_1 # encoding: [0x75,A]
-; O0-NDD-ZU-NEXT: # fixup A - offset: 1, value: .LBB5_1-1, kind: FK_PCRel_1
-; O0-NDD-ZU-NEXT: jmp .LBB5_2 # encoding: [0xeb,A]
-; O0-NDD-ZU-NEXT: # fixup A - offset: 1, value: .LBB5_2-1, kind: FK_PCRel_1
-; O0-NDD-ZU-NEXT: .LBB5_1: # %bb8
-; O0-NDD-ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; O0-NDD-ZU-NEXT: # kill: def $al killed $al killed $eax
-; O0-NDD-ZU-NEXT: jmp foo at PLT # TAILCALL
-; O0-NDD-ZU-NEXT: # encoding: [0xeb,A]
-; O0-NDD-ZU-NEXT: # fixup A - offset: 1, value: foo at PLT-1, kind: FK_PCRel_1
-; O0-NDD-ZU-NEXT: .LBB5_2: # %bb12
-; O0-NDD-ZU-NEXT: movl $32, %eax # encoding: [0xb8,0x20,0x00,0x00,0x00]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; O0-ZU-LABEL: test5:
+; O0-ZU: # %bb.0: # %entry
+; O0-ZU-NEXT: movsd {{.*#+}} xmm1 = [1.5E+2,0.0E+0]
+; O0-ZU-NEXT: # encoding: [0xf2,0x0f,0x10,0x0d,A,A,A,A]
+; O0-ZU-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; O0-ZU-NEXT: ucomisd %xmm1, %xmm0 # encoding: [0x66,0x0f,0x2e,0xc1]
+; O0-ZU-NEXT: setzua %al # encoding: [0x62,0xf4,0x7f,0x18,0x47,0xc0]
+; O0-ZU-NEXT: movsd {{.*#+}} xmm1 = [7.5E+1,0.0E+0]
+; O0-ZU-NEXT: # encoding: [0xf2,0x0f,0x10,0x0d,A,A,A,A]
+; O0-ZU-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
+; O0-ZU-NEXT: ucomisd %xmm1, %xmm0 # encoding: [0x66,0x0f,0x2e,0xc1]
+; O0-ZU-NEXT: setzub %cl # encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc1]
+; O0-ZU-NEXT: orb %cl, %al # encoding: [0x08,0xc8]
+; O0-ZU-NEXT: testb $1, %al # encoding: [0xa8,0x01]
+; O0-ZU-NEXT: jne .LBB5_1 # encoding: [0x75,A]
+; O0-ZU-NEXT: # fixup A - offset: 1, value: .LBB5_1-1, kind: FK_PCRel_1
+; O0-ZU-NEXT: jmp .LBB5_2 # encoding: [0xeb,A]
+; O0-ZU-NEXT: # fixup A - offset: 1, value: .LBB5_2-1, kind: FK_PCRel_1
+; O0-ZU-NEXT: .LBB5_1: # %bb8
+; O0-ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; O0-ZU-NEXT: # kill: def $al killed $al killed $eax
+; O0-ZU-NEXT: jmp foo at PLT # TAILCALL
+; O0-ZU-NEXT: # encoding: [0xeb,A]
+; O0-ZU-NEXT: # fixup A - offset: 1, value: foo at PLT-1, kind: FK_PCRel_1
+; O0-ZU-NEXT: .LBB5_2: # %bb12
+; O0-ZU-NEXT: movl $32, %eax # encoding: [0xb8,0x20,0x00,0x00,0x00]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
entry:
%tmp2 = fcmp ogt double %A, 1.500000e+02
%tmp5 = fcmp ult double %A, 7.500000e+01
@@ -267,17 +274,17 @@ define i32 @test6() nounwind align 2 {
; CHECK-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
; CHECK-NEXT: retq # encoding: [0xc3]
;
-; O0-NDD-ZU-LABEL: test6:
-; O0-NDD-ZU: # %bb.0: # %entry
-; O0-NDD-ZU-NEXT: cmpq $0, -{{[0-9]+}}(%rsp) # encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00]
-; O0-NDD-ZU-NEXT: jne .LBB6_2 # encoding: [0x75,A]
-; O0-NDD-ZU-NEXT: # fixup A - offset: 1, value: .LBB6_2-1, kind: FK_PCRel_1
-; O0-NDD-ZU-NEXT: # %bb.1: # %T
-; O0-NDD-ZU-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
-; O0-NDD-ZU-NEXT: .LBB6_2: # %F
-; O0-NDD-ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; O0-ZU-LABEL: test6:
+; O0-ZU: # %bb.0: # %entry
+; O0-ZU-NEXT: cmpq $0, -{{[0-9]+}}(%rsp) # encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00]
+; O0-ZU-NEXT: jne .LBB6_2 # encoding: [0x75,A]
+; O0-ZU-NEXT: # fixup A - offset: 1, value: .LBB6_2-1, kind: FK_PCRel_1
+; O0-ZU-NEXT: # %bb.1: # %T
+; O0-ZU-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
+; O0-ZU-NEXT: .LBB6_2: # %F
+; O0-ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
entry:
%A = alloca { i64, i64 }, align 8
%B = getelementptr inbounds { i64, i64 }, ptr %A, i64 0, i32 1
@@ -302,26 +309,26 @@ define i32 @test7(i64 %res) nounwind {
;
; NDD-LABEL: test7:
; NDD: # %bb.0: # %entry
+; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: shrq $32, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x20]
-; NDD-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: test7:
-; NDD-ZU: # %bb.0: # %entry
-; NDD-ZU-NEXT: shrq $32, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x20]
-; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: test7:
-; O0-NDD-ZU: # %bb.0: # %entry
-; O0-NDD-ZU-NEXT: movabsq $4294967296, %rax # encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00]
-; O0-NDD-ZU-NEXT: # imm = 0x100000000
-; O0-NDD-ZU-NEXT: cmpq %rax, %rdi # encoding: [0x48,0x39,0xc7]
-; O0-NDD-ZU-NEXT: setzub %al # encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc0]
-; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
-; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: test7:
+; ZU: # %bb.0: # %entry
+; ZU-NEXT: shrq $32, %rdi # encoding: [0x48,0xc1,0xef,0x20]
+; ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: test7:
+; O0-ZU: # %bb.0: # %entry
+; O0-ZU-NEXT: movabsq $4294967296, %rax # encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00]
+; O0-ZU-NEXT: # imm = 0x100000000
+; O0-ZU-NEXT: cmpq %rax, %rdi # encoding: [0x48,0x39,0xc7]
+; O0-ZU-NEXT: setzub %al # encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc0]
+; O0-ZU-NEXT: andb $1, %al # encoding: [0x24,0x01]
+; O0-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
entry:
%lnot = icmp ult i64 %res, 4294967296
%lnot.ext = zext i1 %lnot to i32
@@ -340,27 +347,27 @@ define i32 @test8(i64 %res) nounwind {
; NDD-LABEL: test8:
; NDD: # %bb.0:
; NDD-NEXT: shrq $32, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x20]
+; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: cmpl $3, %edi # encoding: [0x83,0xff,0x03]
-; NDD-NEXT: setzub %al # encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc0]
-; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; NDD-NEXT: setb %al # encoding: [0x0f,0x92,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: test8:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: shrq $32, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x20]
-; NDD-ZU-NEXT: cmpl $3, %edi # encoding: [0x83,0xff,0x03]
-; NDD-ZU-NEXT: setzub %al # encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc0]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: test8:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: movabsq $12884901888, %rax # encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x03,0x00,0x00,0x00]
-; O0-NDD-ZU-NEXT: # imm = 0x300000000
-; O0-NDD-ZU-NEXT: cmpq %rax, %rdi # encoding: [0x48,0x39,0xc7]
-; O0-NDD-ZU-NEXT: setzub %al # encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc0]
-; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
-; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: test8:
+; ZU: # %bb.0:
+; ZU-NEXT: shrq $32, %rdi # encoding: [0x48,0xc1,0xef,0x20]
+; ZU-NEXT: cmpl $3, %edi # encoding: [0x83,0xff,0x03]
+; ZU-NEXT: setzub %al # encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: test8:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: movabsq $12884901888, %rax # encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x03,0x00,0x00,0x00]
+; O0-ZU-NEXT: # imm = 0x300000000
+; O0-ZU-NEXT: cmpq %rax, %rdi # encoding: [0x48,0x39,0xc7]
+; O0-ZU-NEXT: setzub %al # encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc0]
+; O0-ZU-NEXT: andb $1, %al # encoding: [0x24,0x01]
+; O0-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%lnot = icmp ult i64 %res, 12884901888
%lnot.ext = zext i1 %lnot to i32
ret i32 %lnot.ext
@@ -376,26 +383,26 @@ define i32 @test9(i64 %res) nounwind {
;
; NDD-LABEL: test9:
; NDD: # %bb.0:
+; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: shrq $33, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x21]
-; NDD-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: test9:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: shrq $33, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x21]
-; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: test9:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: movabsq $8589934592, %rax # encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00]
-; O0-NDD-ZU-NEXT: # imm = 0x200000000
-; O0-NDD-ZU-NEXT: cmpq %rax, %rdi # encoding: [0x48,0x39,0xc7]
-; O0-NDD-ZU-NEXT: setzub %al # encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc0]
-; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
-; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: test9:
+; ZU: # %bb.0:
+; ZU-NEXT: shrq $33, %rdi # encoding: [0x48,0xc1,0xef,0x21]
+; ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: test9:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: movabsq $8589934592, %rax # encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00]
+; O0-ZU-NEXT: # imm = 0x200000000
+; O0-ZU-NEXT: cmpq %rax, %rdi # encoding: [0x48,0x39,0xc7]
+; O0-ZU-NEXT: setzub %al # encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc0]
+; O0-ZU-NEXT: andb $1, %al # encoding: [0x24,0x01]
+; O0-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%lnot = icmp ult i64 %res, 8589934592
%lnot.ext = zext i1 %lnot to i32
ret i32 %lnot.ext
@@ -411,26 +418,26 @@ define i32 @test10(i64 %res) nounwind {
;
; NDD-LABEL: test10:
; NDD: # %bb.0:
+; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: shrq $32, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x20]
-; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: test10:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: shrq $32, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x20]
-; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: test10:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: movabsq $4294967296, %rax # encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00]
-; O0-NDD-ZU-NEXT: # imm = 0x100000000
-; O0-NDD-ZU-NEXT: cmpq %rax, %rdi # encoding: [0x48,0x39,0xc7]
-; O0-NDD-ZU-NEXT: setzuae %al # encoding: [0x62,0xf4,0x7f,0x18,0x43,0xc0]
-; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
-; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: test10:
+; ZU: # %bb.0:
+; ZU-NEXT: shrq $32, %rdi # encoding: [0x48,0xc1,0xef,0x20]
+; ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: test10:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: movabsq $4294967296, %rax # encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00]
+; O0-ZU-NEXT: # imm = 0x100000000
+; O0-ZU-NEXT: cmpq %rax, %rdi # encoding: [0x48,0x39,0xc7]
+; O0-ZU-NEXT: setzuae %al # encoding: [0x62,0xf4,0x7f,0x18,0x43,0xc0]
+; O0-ZU-NEXT: andb $1, %al # encoding: [0x24,0x01]
+; O0-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%lnot = icmp uge i64 %res, 4294967296
%lnot.ext = zext i1 %lnot to i32
ret i32 %lnot.ext
@@ -448,30 +455,30 @@ define i32 @test11(i64 %l) nounwind {
; NDD-LABEL: test11:
; NDD: # %bb.0:
; NDD-NEXT: shrq $47, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x2f]
+; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: cmpl $1, %edi # encoding: [0x83,0xff,0x01]
-; NDD-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: test11:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: shrq $47, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x2f]
-; NDD-ZU-NEXT: cmpl $1, %edi # encoding: [0x83,0xff,0x01]
-; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: test11:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: movabsq $-140737488355328, %rax # encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0x80,0xff,0xff]
-; O0-NDD-ZU-NEXT: # imm = 0xFFFF800000000000
-; O0-NDD-ZU-NEXT: andq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x21,0xf8]
-; O0-NDD-ZU-NEXT: movabsq $140737488355328, %rcx # encoding: [0x48,0xb9,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00]
-; O0-NDD-ZU-NEXT: # imm = 0x800000000000
-; O0-NDD-ZU-NEXT: cmpq %rcx, %rax # encoding: [0x48,0x39,0xc8]
-; O0-NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
-; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: test11:
+; ZU: # %bb.0:
+; ZU-NEXT: shrq $47, %rdi # encoding: [0x48,0xc1,0xef,0x2f]
+; ZU-NEXT: cmpl $1, %edi # encoding: [0x83,0xff,0x01]
+; ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: test11:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: movabsq $-140737488355328, %rax # encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0x80,0xff,0xff]
+; O0-ZU-NEXT: # imm = 0xFFFF800000000000
+; O0-ZU-NEXT: andq %rax, %rdi # encoding: [0x48,0x21,0xc7]
+; O0-ZU-NEXT: movabsq $140737488355328, %rax # encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00]
+; O0-ZU-NEXT: # imm = 0x800000000000
+; O0-ZU-NEXT: cmpq %rax, %rdi # encoding: [0x48,0x39,0xc7]
+; O0-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; O0-ZU-NEXT: andb $1, %al # encoding: [0x24,0x01]
+; O0-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%shr.mask = and i64 %l, -140737488355328
%cmp = icmp eq i64 %shr.mask, 140737488355328
%conv = zext i1 %cmp to i32
@@ -500,28 +507,28 @@ define i32 @test12() ssp uwtable {
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq # encoding: [0xc3]
;
-; O0-NDD-ZU-LABEL: test12:
-; O0-NDD-ZU: # %bb.0: # %entry
-; O0-NDD-ZU-NEXT: pushq %rax # encoding: [0x50]
-; O0-NDD-ZU-NEXT: .cfi_def_cfa_offset 16
-; O0-NDD-ZU-NEXT: callq test12b at PLT # encoding: [0xe8,A,A,A,A]
-; O0-NDD-ZU-NEXT: # fixup A - offset: 1, value: test12b at PLT-4, kind: FK_PCRel_4
-; O0-NDD-ZU-NEXT: testb $1, %al # encoding: [0xa8,0x01]
-; O0-NDD-ZU-NEXT: jne .LBB12_1 # encoding: [0x75,A]
-; O0-NDD-ZU-NEXT: # fixup A - offset: 1, value: .LBB12_1-1, kind: FK_PCRel_1
-; O0-NDD-ZU-NEXT: jmp .LBB12_2 # encoding: [0xeb,A]
-; O0-NDD-ZU-NEXT: # fixup A - offset: 1, value: .LBB12_2-1, kind: FK_PCRel_1
-; O0-NDD-ZU-NEXT: .LBB12_1: # %T
-; O0-NDD-ZU-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
-; O0-NDD-ZU-NEXT: popq %rcx # encoding: [0x59]
-; O0-NDD-ZU-NEXT: .cfi_def_cfa_offset 8
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
-; O0-NDD-ZU-NEXT: .LBB12_2: # %F
-; O0-NDD-ZU-NEXT: .cfi_def_cfa_offset 16
-; O0-NDD-ZU-NEXT: movl $2, %eax # encoding: [0xb8,0x02,0x00,0x00,0x00]
-; O0-NDD-ZU-NEXT: popq %rcx # encoding: [0x59]
-; O0-NDD-ZU-NEXT: .cfi_def_cfa_offset 8
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; O0-ZU-LABEL: test12:
+; O0-ZU: # %bb.0: # %entry
+; O0-ZU-NEXT: pushq %rax # encoding: [0x50]
+; O0-ZU-NEXT: .cfi_def_cfa_offset 16
+; O0-ZU-NEXT: callq test12b at PLT # encoding: [0xe8,A,A,A,A]
+; O0-ZU-NEXT: # fixup A - offset: 1, value: test12b at PLT-4, kind: FK_PCRel_4
+; O0-ZU-NEXT: testb $1, %al # encoding: [0xa8,0x01]
+; O0-ZU-NEXT: jne .LBB12_1 # encoding: [0x75,A]
+; O0-ZU-NEXT: # fixup A - offset: 1, value: .LBB12_1-1, kind: FK_PCRel_1
+; O0-ZU-NEXT: jmp .LBB12_2 # encoding: [0xeb,A]
+; O0-ZU-NEXT: # fixup A - offset: 1, value: .LBB12_2-1, kind: FK_PCRel_1
+; O0-ZU-NEXT: .LBB12_1: # %T
+; O0-ZU-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00]
+; O0-ZU-NEXT: popq %rcx # encoding: [0x59]
+; O0-ZU-NEXT: .cfi_def_cfa_offset 8
+; O0-ZU-NEXT: retq # encoding: [0xc3]
+; O0-ZU-NEXT: .LBB12_2: # %F
+; O0-ZU-NEXT: .cfi_def_cfa_offset 16
+; O0-ZU-NEXT: movl $2, %eax # encoding: [0xb8,0x02,0x00,0x00,0x00]
+; O0-ZU-NEXT: popq %rcx # encoding: [0x59]
+; O0-ZU-NEXT: .cfi_def_cfa_offset 8
+; O0-ZU-NEXT: retq # encoding: [0xc3]
entry:
%tmp1 = call zeroext i1 @test12b()
br i1 %tmp1, label %T, label %F
@@ -549,18 +556,20 @@ define i32 @test13(i32 %mask, i32 %base, i32 %intra) {
; NDD-NEXT: cmovnel %edx, %esi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x45,0xf2]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: test13:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: testb $8, %dil # encoding: [0x40,0xf6,0xc7,0x08]
-; NDD-ZU-NEXT: cmovnel %edx, %esi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x45,0xf2]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: test13:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: andl $8, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xe7,0x08]
-; O0-NDD-ZU-NEXT: cmpl $0, %eax # encoding: [0x83,0xf8,0x00]
-; O0-NDD-ZU-NEXT: cmovnel %edx, %esi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x45,0xf2]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: test13:
+; ZU: # %bb.0:
+; ZU-NEXT: movl %esi, %eax # encoding: [0x89,0xf0]
+; ZU-NEXT: testb $8, %dil # encoding: [0x40,0xf6,0xc7,0x08]
+; ZU-NEXT: cmovnel %edx, %eax # encoding: [0x0f,0x45,0xc2]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: test13:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: movl %esi, %eax # encoding: [0x89,0xf0]
+; O0-ZU-NEXT: andl $8, %edi # encoding: [0x83,0xe7,0x08]
+; O0-ZU-NEXT: cmpl $0, %edi # encoding: [0x83,0xff,0x00]
+; O0-ZU-NEXT: cmovnel %edx, %eax # encoding: [0x0f,0x45,0xc2]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%and = and i32 %mask, 8
%tobool = icmp ne i32 %and, 0
%cond = select i1 %tobool, i32 %intra, i32 %base
@@ -581,18 +590,20 @@ define i32 @test14(i32 %mask, i32 %base, i32 %intra) {
; NDD-NEXT: cmovnsl %edx, %esi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x49,0xf2]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: test14:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: shrl $7, %edi # EVEX TO LEGACY Compression encoding: [0xc1,0xef,0x07]
-; NDD-ZU-NEXT: cmovnsl %edx, %esi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x49,0xf2]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: test14:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: shrl $7, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0xc1,0xef,0x07]
-; O0-NDD-ZU-NEXT: cmpl $-1, %eax # encoding: [0x83,0xf8,0xff]
-; O0-NDD-ZU-NEXT: cmovgl %edx, %esi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x4f,0xf2]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: test14:
+; ZU: # %bb.0:
+; ZU-NEXT: movl %esi, %eax # encoding: [0x89,0xf0]
+; ZU-NEXT: shrl $7, %edi # encoding: [0xc1,0xef,0x07]
+; ZU-NEXT: cmovnsl %edx, %eax # encoding: [0x0f,0x49,0xc2]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: test14:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: movl %esi, %eax # encoding: [0x89,0xf0]
+; O0-ZU-NEXT: shrl $7, %edi # encoding: [0xc1,0xef,0x07]
+; O0-ZU-NEXT: cmpl $-1, %edi # encoding: [0x83,0xff,0xff]
+; O0-ZU-NEXT: cmovgl %edx, %eax # encoding: [0x0f,0x4f,0xc2]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%s = lshr i32 %mask, 7
%tobool = icmp sgt i32 %s, -1
%cond = select i1 %tobool, i32 %intra, i32 %base
@@ -613,31 +624,31 @@ define zeroext i1 @test15(i32 %bf.load, i32 %n) {
; NDD-LABEL: test15:
; NDD: # %bb.0:
; NDD-NEXT: shrl $16, %edi # EVEX TO LEGACY Compression encoding: [0xc1,0xef,0x10]
-; NDD-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NDD-NEXT: cmpl %esi, %edi # encoding: [0x39,0xf7]
-; NDD-NEXT: setzuae %cl # encoding: [0x62,0xf4,0x7f,0x18,0x43,0xc1]
+; NDD-NEXT: setae %cl # encoding: [0x0f,0x93,0xc1]
; NDD-NEXT: orb %cl, %al # EVEX TO LEGACY Compression encoding: [0x08,0xc8]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: test15:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: shrl $16, %edi # EVEX TO LEGACY Compression encoding: [0xc1,0xef,0x10]
-; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; NDD-ZU-NEXT: cmpl %esi, %edi # encoding: [0x39,0xf7]
-; NDD-ZU-NEXT: setzuae %cl # encoding: [0x62,0xf4,0x7f,0x18,0x43,0xc1]
-; NDD-ZU-NEXT: orb %cl, %al # EVEX TO LEGACY Compression encoding: [0x08,0xc8]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: test15:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: shrl $16, %edi, %ecx # encoding: [0x62,0xf4,0x74,0x18,0xc1,0xef,0x10]
-; O0-NDD-ZU-NEXT: cmpl $0, %ecx # encoding: [0x83,0xf9,0x00]
-; O0-NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; O0-NDD-ZU-NEXT: cmpl %esi, %ecx # encoding: [0x39,0xf1]
-; O0-NDD-ZU-NEXT: setzuae %cl # encoding: [0x62,0xf4,0x7f,0x18,0x43,0xc1]
-; O0-NDD-ZU-NEXT: orb %cl, %al # EVEX TO LEGACY Compression encoding: [0x08,0xc8]
-; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: test15:
+; ZU: # %bb.0:
+; ZU-NEXT: shrl $16, %edi # encoding: [0xc1,0xef,0x10]
+; ZU-NEXT: setzue %cl # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc1]
+; ZU-NEXT: cmpl %esi, %edi # encoding: [0x39,0xf7]
+; ZU-NEXT: setzuae %al # encoding: [0x62,0xf4,0x7f,0x18,0x43,0xc0]
+; ZU-NEXT: orb %cl, %al # encoding: [0x08,0xc8]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: test15:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: shrl $16, %edi # encoding: [0xc1,0xef,0x10]
+; O0-ZU-NEXT: cmpl $0, %edi # encoding: [0x83,0xff,0x00]
+; O0-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; O0-ZU-NEXT: cmpl %esi, %edi # encoding: [0x39,0xf7]
+; O0-ZU-NEXT: setzuae %cl # encoding: [0x62,0xf4,0x7f,0x18,0x43,0xc1]
+; O0-ZU-NEXT: orb %cl, %al # encoding: [0x08,0xc8]
+; O0-ZU-NEXT: andb $1, %al # encoding: [0x24,0x01]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%bf.lshr = lshr i32 %bf.load, 16
%cmp2 = icmp eq i32 %bf.lshr, 0
%cmp5 = icmp uge i32 %bf.lshr, %n
@@ -655,22 +666,22 @@ define i8 @signbit_i16(i16 signext %L) {
; NDD-LABEL: signbit_i16:
; NDD: # %bb.0:
; NDD-NEXT: testw %di, %di # encoding: [0x66,0x85,0xff]
-; NDD-NEXT: setzuns %al # encoding: [0x62,0xf4,0x7f,0x18,0x49,0xc0]
+; NDD-NEXT: setns %al # encoding: [0x0f,0x99,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: signbit_i16:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: testw %di, %di # encoding: [0x66,0x85,0xff]
-; NDD-ZU-NEXT: setzuns %al # encoding: [0x62,0xf4,0x7f,0x18,0x49,0xc0]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: signbit_i16:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: movw %di, %ax # encoding: [0x66,0x89,0xf8]
-; O0-NDD-ZU-NEXT: shrw $15, %ax # EVEX TO LEGACY Compression encoding: [0x66,0xc1,0xe8,0x0f]
-; O0-NDD-ZU-NEXT: # kill: def $al killed $al killed $ax
-; O0-NDD-ZU-NEXT: xorb $1, %al # EVEX TO LEGACY Compression encoding: [0x34,0x01]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: signbit_i16:
+; ZU: # %bb.0:
+; ZU-NEXT: testw %di, %di # encoding: [0x66,0x85,0xff]
+; ZU-NEXT: setzuns %al # encoding: [0x62,0xf4,0x7f,0x18,0x49,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: signbit_i16:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: movw %di, %ax # encoding: [0x66,0x89,0xf8]
+; O0-ZU-NEXT: shrw $15, %ax # encoding: [0x66,0xc1,0xe8,0x0f]
+; O0-ZU-NEXT: # kill: def $al killed $al killed $ax
+; O0-ZU-NEXT: xorb $1, %al # encoding: [0x34,0x01]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%lshr = lshr i16 %L, 15
%trunc = trunc i16 %lshr to i8
%not = xor i8 %trunc, 1
@@ -687,21 +698,21 @@ define i8 @signbit_i32(i32 %L) {
; NDD-LABEL: signbit_i32:
; NDD: # %bb.0:
; NDD-NEXT: testl %edi, %edi # encoding: [0x85,0xff]
-; NDD-NEXT: setzuns %al # encoding: [0x62,0xf4,0x7f,0x18,0x49,0xc0]
+; NDD-NEXT: setns %al # encoding: [0x0f,0x99,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: signbit_i32:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: testl %edi, %edi # encoding: [0x85,0xff]
-; NDD-ZU-NEXT: setzuns %al # encoding: [0x62,0xf4,0x7f,0x18,0x49,0xc0]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: signbit_i32:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: shrl $31, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0xc1,0xef,0x1f]
-; O0-NDD-ZU-NEXT: # kill: def $al killed $al killed $eax
-; O0-NDD-ZU-NEXT: xorb $1, %al # EVEX TO LEGACY Compression encoding: [0x34,0x01]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: signbit_i32:
+; ZU: # %bb.0:
+; ZU-NEXT: testl %edi, %edi # encoding: [0x85,0xff]
+; ZU-NEXT: setzuns %al # encoding: [0x62,0xf4,0x7f,0x18,0x49,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: signbit_i32:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: shrl $31, %edi # encoding: [0xc1,0xef,0x1f]
+; O0-ZU-NEXT: movb %dil, %al # encoding: [0x40,0x88,0xf8]
+; O0-ZU-NEXT: xorb $1, %al # encoding: [0x34,0x01]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%lshr = lshr i32 %L, 31
%trunc = trunc i32 %lshr to i8
%not = xor i8 %trunc, 1
@@ -718,21 +729,21 @@ define i8 @signbit_i64(i64 %L) {
; NDD-LABEL: signbit_i64:
; NDD: # %bb.0:
; NDD-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff]
-; NDD-NEXT: setzuns %al # encoding: [0x62,0xf4,0x7f,0x18,0x49,0xc0]
+; NDD-NEXT: setns %al # encoding: [0x0f,0x99,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: signbit_i64:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff]
-; NDD-ZU-NEXT: setzuns %al # encoding: [0x62,0xf4,0x7f,0x18,0x49,0xc0]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: signbit_i64:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: shrq $63, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xc1,0xef,0x3f]
-; O0-NDD-ZU-NEXT: # kill: def $al killed $al killed $rax
-; O0-NDD-ZU-NEXT: xorb $1, %al # EVEX TO LEGACY Compression encoding: [0x34,0x01]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: signbit_i64:
+; ZU: # %bb.0:
+; ZU-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff]
+; ZU-NEXT: setzuns %al # encoding: [0x62,0xf4,0x7f,0x18,0x49,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: signbit_i64:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: shrq $63, %rdi # encoding: [0x48,0xc1,0xef,0x3f]
+; O0-ZU-NEXT: movb %dil, %al # encoding: [0x40,0x88,0xf8]
+; O0-ZU-NEXT: xorb $1, %al # encoding: [0x34,0x01]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%lshr = lshr i64 %L, 63
%trunc = trunc i64 %lshr to i8
%not = xor i8 %trunc, 1
@@ -749,22 +760,22 @@ define zeroext i1 @signbit_i32_i1(i32 %L) {
; NDD-LABEL: signbit_i32_i1:
; NDD: # %bb.0:
; NDD-NEXT: testl %edi, %edi # encoding: [0x85,0xff]
-; NDD-NEXT: setzuns %al # encoding: [0x62,0xf4,0x7f,0x18,0x49,0xc0]
+; NDD-NEXT: setns %al # encoding: [0x0f,0x99,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: signbit_i32_i1:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: testl %edi, %edi # encoding: [0x85,0xff]
-; NDD-ZU-NEXT: setzuns %al # encoding: [0x62,0xf4,0x7f,0x18,0x49,0xc0]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: signbit_i32_i1:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: shrl $31, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0xc1,0xef,0x1f]
-; O0-NDD-ZU-NEXT: # kill: def $al killed $al killed $eax
-; O0-NDD-ZU-NEXT: xorb $-1, %al # EVEX TO LEGACY Compression encoding: [0x34,0xff]
-; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: signbit_i32_i1:
+; ZU: # %bb.0:
+; ZU-NEXT: testl %edi, %edi # encoding: [0x85,0xff]
+; ZU-NEXT: setzuns %al # encoding: [0x62,0xf4,0x7f,0x18,0x49,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: signbit_i32_i1:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: shrl $31, %edi # encoding: [0xc1,0xef,0x1f]
+; O0-ZU-NEXT: movb %dil, %al # encoding: [0x40,0x88,0xf8]
+; O0-ZU-NEXT: xorb $-1, %al # encoding: [0x34,0xff]
+; O0-ZU-NEXT: andb $1, %al # encoding: [0x24,0x01]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%lshr = lshr i32 %L, 31
%trunc = trunc i32 %lshr to i1
%not = xor i1 %trunc, true
@@ -790,10 +801,10 @@ define void @test20(i32 %bf.load, i8 %x1, ptr %b_addr) {
;
; NDD-LABEL: test20:
; NDD: # %bb.0:
+; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: testl $16777215, %edi # encoding: [0xf7,0xc7,0xff,0xff,0xff,0x00]
; NDD-NEXT: # imm = 0xFFFFFF
-; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
; NDD-NEXT: movzbl %sil, %ecx # encoding: [0x40,0x0f,0xb6,0xce]
; NDD-NEXT: addl %ecx, %eax # EVEX TO LEGACY Compression encoding: [0x01,0xc8]
; NDD-NEXT: setne (%rdx) # encoding: [0x0f,0x95,0x02]
@@ -803,41 +814,42 @@ define void @test20(i32 %bf.load, i8 %x1, ptr %b_addr) {
; NDD-NEXT: # fixup A - offset: 3, value: d-4, kind: reloc_riprel_4byte
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: test20:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: testl $16777215, %edi # encoding: [0xf7,0xc7,0xff,0xff,0xff,0x00]
-; NDD-ZU-NEXT: # imm = 0xFFFFFF
-; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; NDD-ZU-NEXT: movzbl %sil, %ecx # encoding: [0x40,0x0f,0xb6,0xce]
-; NDD-ZU-NEXT: addl %ecx, %eax # EVEX TO LEGACY Compression encoding: [0x01,0xc8]
-; NDD-ZU-NEXT: setne (%rdx) # encoding: [0x0f,0x95,0x02]
-; NDD-ZU-NEXT: testl $16777215, %edi # encoding: [0xf7,0xc7,0xff,0xff,0xff,0x00]
-; NDD-ZU-NEXT: # imm = 0xFFFFFF
-; NDD-ZU-NEXT: setne d(%rip) # encoding: [0x0f,0x95,0x05,A,A,A,A]
-; NDD-ZU-NEXT: # fixup A - offset: 3, value: d-4, kind: reloc_riprel_4byte
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: test20:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: # kill: def $sil killed $sil killed $esi
-; O0-NDD-ZU-NEXT: shll $8, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0xc1,0xe7,0x08]
-; O0-NDD-ZU-NEXT: sarl $8, %eax, %ecx # encoding: [0x62,0xf4,0x74,0x18,0xc1,0xf8,0x08]
-; O0-NDD-ZU-NEXT: cmpl $0, %ecx # encoding: [0x83,0xf9,0x00]
-; O0-NDD-ZU-NEXT: setzune %cl # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc1]
-; O0-NDD-ZU-NEXT: andb $1, %cl # EVEX TO LEGACY Compression encoding: [0x80,0xe1,0x01]
-; O0-NDD-ZU-NEXT: movzbl %cl, %ecx # encoding: [0x0f,0xb6,0xc9]
-; O0-NDD-ZU-NEXT: movzbl %sil, %esi # encoding: [0x40,0x0f,0xb6,0xf6]
-; O0-NDD-ZU-NEXT: addl %esi, %ecx # EVEX TO LEGACY Compression encoding: [0x01,0xf1]
-; O0-NDD-ZU-NEXT: cmpl $0, %ecx # encoding: [0x83,0xf9,0x00]
-; O0-NDD-ZU-NEXT: setzune %cl # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc1]
-; O0-NDD-ZU-NEXT: andb $1, %cl # EVEX TO LEGACY Compression encoding: [0x80,0xe1,0x01]
-; O0-NDD-ZU-NEXT: movb %cl, (%rdx) # encoding: [0x88,0x0a]
-; O0-NDD-ZU-NEXT: cmpl $0, %eax # encoding: [0x83,0xf8,0x00]
-; O0-NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
-; O0-NDD-ZU-NEXT: movb %al, d # encoding: [0x88,0x04,0x25,A,A,A,A]
-; O0-NDD-ZU-NEXT: # fixup A - offset: 3, value: d, kind: reloc_signed_4byte
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: test20:
+; ZU: # %bb.0:
+; ZU-NEXT: testl $16777215, %edi # encoding: [0xf7,0xc7,0xff,0xff,0xff,0x00]
+; ZU-NEXT: # imm = 0xFFFFFF
+; ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; ZU-NEXT: movzbl %sil, %ecx # encoding: [0x40,0x0f,0xb6,0xce]
+; ZU-NEXT: addl %eax, %ecx # encoding: [0x01,0xc1]
+; ZU-NEXT: setne (%rdx) # encoding: [0x0f,0x95,0x02]
+; ZU-NEXT: testl $16777215, %edi # encoding: [0xf7,0xc7,0xff,0xff,0xff,0x00]
+; ZU-NEXT: # imm = 0xFFFFFF
+; ZU-NEXT: setne d(%rip) # encoding: [0x0f,0x95,0x05,A,A,A,A]
+; ZU-NEXT: # fixup A - offset: 3, value: d-4, kind: reloc_riprel_4byte
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: test20:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: movb %sil, %cl # encoding: [0x40,0x88,0xf1]
+; O0-ZU-NEXT: shll $8, %edi # encoding: [0xc1,0xe7,0x08]
+; O0-ZU-NEXT: movl %edi, %eax # encoding: [0x89,0xf8]
+; O0-ZU-NEXT: sarl $8, %eax # encoding: [0xc1,0xf8,0x08]
+; O0-ZU-NEXT: cmpl $0, %eax # encoding: [0x83,0xf8,0x00]
+; O0-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; O0-ZU-NEXT: andb $1, %al # encoding: [0x24,0x01]
+; O0-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-ZU-NEXT: movzbl %cl, %ecx # encoding: [0x0f,0xb6,0xc9]
+; O0-ZU-NEXT: addl %ecx, %eax # encoding: [0x01,0xc8]
+; O0-ZU-NEXT: cmpl $0, %eax # encoding: [0x83,0xf8,0x00]
+; O0-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; O0-ZU-NEXT: andb $1, %al # encoding: [0x24,0x01]
+; O0-ZU-NEXT: movb %al, (%rdx) # encoding: [0x88,0x02]
+; O0-ZU-NEXT: cmpl $0, %edi # encoding: [0x83,0xff,0x00]
+; O0-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; O0-ZU-NEXT: andb $1, %al # encoding: [0x24,0x01]
+; O0-ZU-NEXT: movb %al, d # encoding: [0x88,0x04,0x25,A,A,A,A]
+; O0-ZU-NEXT: # fixup A - offset: 3, value: d, kind: reloc_signed_4byte
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%bf.shl = shl i32 %bf.load, 8
%bf.ashr = ashr exact i32 %bf.shl, 8
%tobool4 = icmp ne i32 %bf.ashr, 0
@@ -859,16 +871,16 @@ define i32 @highmask_i64_simplify(i64 %val) {
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; CHECK-NEXT: retq # encoding: [0xc3]
;
-; O0-NDD-ZU-LABEL: highmask_i64_simplify:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: movabsq $-2199023255552, %rax # encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0xfe,0xff,0xff]
-; O0-NDD-ZU-NEXT: # imm = 0xFFFFFE0000000000
-; O0-NDD-ZU-NEXT: andq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x21,0xf8]
-; O0-NDD-ZU-NEXT: cmpq $0, %rax # encoding: [0x48,0x83,0xf8,0x00]
-; O0-NDD-ZU-NEXT: setzub %al # encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc0]
-; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
-; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; O0-ZU-LABEL: highmask_i64_simplify:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: movabsq $-2199023255552, %rax # encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0xfe,0xff,0xff]
+; O0-ZU-NEXT: # imm = 0xFFFFFE0000000000
+; O0-ZU-NEXT: andq %rax, %rdi # encoding: [0x48,0x21,0xc7]
+; O0-ZU-NEXT: cmpq $0, %rdi # encoding: [0x48,0x83,0xff,0x00]
+; O0-ZU-NEXT: setzub %al # encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc0]
+; O0-ZU-NEXT: andb $1, %al # encoding: [0x24,0x01]
+; O0-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%and = and i64 %val, -2199023255552
%cmp = icmp ult i64 %and, 0
%ret = zext i1 %cmp to i32
@@ -885,27 +897,27 @@ define i32 @highmask_i64_mask64(i64 %val) {
;
; NDD-LABEL: highmask_i64_mask64:
; NDD: # %bb.0:
+; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: shrq $41, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x29]
-; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: highmask_i64_mask64:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: shrq $41, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x29]
-; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: highmask_i64_mask64:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: movabsq $-2199023255552, %rax # encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0xfe,0xff,0xff]
-; O0-NDD-ZU-NEXT: # imm = 0xFFFFFE0000000000
-; O0-NDD-ZU-NEXT: andq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x21,0xf8]
-; O0-NDD-ZU-NEXT: cmpq $0, %rax # encoding: [0x48,0x83,0xf8,0x00]
-; O0-NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
-; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: highmask_i64_mask64:
+; ZU: # %bb.0:
+; ZU-NEXT: shrq $41, %rdi # encoding: [0x48,0xc1,0xef,0x29]
+; ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: highmask_i64_mask64:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: movabsq $-2199023255552, %rax # encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0xfe,0xff,0xff]
+; O0-ZU-NEXT: # imm = 0xFFFFFE0000000000
+; O0-ZU-NEXT: andq %rax, %rdi # encoding: [0x48,0x21,0xc7]
+; O0-ZU-NEXT: cmpq $0, %rdi # encoding: [0x48,0x83,0xff,0x00]
+; O0-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; O0-ZU-NEXT: andb $1, %al # encoding: [0x24,0x01]
+; O0-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%and = and i64 %val, -2199023255552
%cmp = icmp ne i64 %and, 0
%ret = zext i1 %cmp to i32
@@ -924,31 +936,33 @@ define i64 @highmask_i64_mask64_extra_use(i64 %val) nounwind {
;
; NDD-LABEL: highmask_i64_mask64_extra_use:
; NDD: # %bb.0:
-; NDD-NEXT: shrq $41, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xc1,0xef,0x29]
-; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; NDD-NEXT: shrq $41, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0xc1,0xef,0x29]
+; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
; NDD-NEXT: imulq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0xaf,0xc7]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: highmask_i64_mask64_extra_use:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: shrq $41, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xc1,0xef,0x29]
-; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; NDD-ZU-NEXT: imulq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0xaf,0xc7]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: highmask_i64_mask64_extra_use:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: movabsq $-2199023255552, %rax # encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0xfe,0xff,0xff]
-; O0-NDD-ZU-NEXT: # imm = 0xFFFFFE0000000000
-; O0-NDD-ZU-NEXT: andq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x21,0xf8]
-; O0-NDD-ZU-NEXT: cmpq $0, %rax # encoding: [0x48,0x83,0xf8,0x00]
-; O0-NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
-; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
-; O0-NDD-ZU-NEXT: # kill: def $rax killed $eax
-; O0-NDD-ZU-NEXT: imulq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0xaf,0xc7]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: highmask_i64_mask64_extra_use:
+; ZU: # %bb.0:
+; ZU-NEXT: movq %rdi, %rax # encoding: [0x48,0x89,0xf8]
+; ZU-NEXT: shrq $41, %rax # encoding: [0x48,0xc1,0xe8,0x29]
+; ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; ZU-NEXT: imulq %rdi, %rax # encoding: [0x48,0x0f,0xaf,0xc7]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: highmask_i64_mask64_extra_use:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: movabsq $-2199023255552, %rcx # encoding: [0x48,0xb9,0x00,0x00,0x00,0x00,0x00,0xfe,0xff,0xff]
+; O0-ZU-NEXT: # imm = 0xFFFFFE0000000000
+; O0-ZU-NEXT: movq %rdi, %rax # encoding: [0x48,0x89,0xf8]
+; O0-ZU-NEXT: andq %rcx, %rax # encoding: [0x48,0x21,0xc8]
+; O0-ZU-NEXT: cmpq $0, %rax # encoding: [0x48,0x83,0xf8,0x00]
+; O0-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; O0-ZU-NEXT: andb $1, %al # encoding: [0x24,0x01]
+; O0-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-ZU-NEXT: # kill: def $rax killed $eax
+; O0-ZU-NEXT: imulq %rdi, %rax # encoding: [0x48,0x0f,0xaf,0xc7]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%and = and i64 %val, -2199023255552
%cmp = icmp ne i64 %and, 0
%z = zext i1 %cmp to i64
@@ -966,26 +980,26 @@ define i32 @highmask_i64_mask32(i64 %val) {
;
; NDD-LABEL: highmask_i64_mask32:
; NDD: # %bb.0:
+; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: shrq $20, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x14]
-; NDD-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: highmask_i64_mask32:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: shrq $20, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x14]
-; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: highmask_i64_mask32:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: andq $-1048576, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0xe7,0x00,0x00,0xf0,0xff]
-; O0-NDD-ZU-NEXT: # imm = 0xFFF00000
-; O0-NDD-ZU-NEXT: cmpq $0, %rax # encoding: [0x48,0x83,0xf8,0x00]
-; O0-NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
-; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: highmask_i64_mask32:
+; ZU: # %bb.0:
+; ZU-NEXT: shrq $20, %rdi # encoding: [0x48,0xc1,0xef,0x14]
+; ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: highmask_i64_mask32:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: andq $-1048576, %rdi # encoding: [0x48,0x81,0xe7,0x00,0x00,0xf0,0xff]
+; O0-ZU-NEXT: # imm = 0xFFF00000
+; O0-ZU-NEXT: cmpq $0, %rdi # encoding: [0x48,0x83,0xff,0x00]
+; O0-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; O0-ZU-NEXT: andb $1, %al # encoding: [0x24,0x01]
+; O0-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%and = and i64 %val, -1048576
%cmp = icmp eq i64 %and, 0
%ret = zext i1 %cmp to i32
@@ -1004,32 +1018,33 @@ define i64 @highmask_i64_mask32_extra_use(i64 %val) nounwind {
;
; NDD-LABEL: highmask_i64_mask32_extra_use:
; NDD: # %bb.0:
+; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: testq $-1048576, %rdi # encoding: [0x48,0xf7,0xc7,0x00,0x00,0xf0,0xff]
; NDD-NEXT: # imm = 0xFFF00000
-; NDD-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NDD-NEXT: imulq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0xaf,0xc7]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: highmask_i64_mask32_extra_use:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: testq $-1048576, %rdi # encoding: [0x48,0xf7,0xc7,0x00,0x00,0xf0,0xff]
-; NDD-ZU-NEXT: # imm = 0xFFF00000
-; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; NDD-ZU-NEXT: imulq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0xaf,0xc7]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: highmask_i64_mask32_extra_use:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: andq $-1048576, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0xe7,0x00,0x00,0xf0,0xff]
-; O0-NDD-ZU-NEXT: # imm = 0xFFF00000
-; O0-NDD-ZU-NEXT: cmpq $0, %rax # encoding: [0x48,0x83,0xf8,0x00]
-; O0-NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
-; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
-; O0-NDD-ZU-NEXT: # kill: def $rax killed $eax
-; O0-NDD-ZU-NEXT: imulq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0xaf,0xc7]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: highmask_i64_mask32_extra_use:
+; ZU: # %bb.0:
+; ZU-NEXT: testq $-1048576, %rdi # encoding: [0x48,0xf7,0xc7,0x00,0x00,0xf0,0xff]
+; ZU-NEXT: # imm = 0xFFF00000
+; ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; ZU-NEXT: imulq %rdi, %rax # encoding: [0x48,0x0f,0xaf,0xc7]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: highmask_i64_mask32_extra_use:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: movq %rdi, %rax # encoding: [0x48,0x89,0xf8]
+; O0-ZU-NEXT: andq $-1048576, %rax # encoding: [0x48,0x25,0x00,0x00,0xf0,0xff]
+; O0-ZU-NEXT: # imm = 0xFFF00000
+; O0-ZU-NEXT: cmpq $0, %rax # encoding: [0x48,0x83,0xf8,0x00]
+; O0-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; O0-ZU-NEXT: andb $1, %al # encoding: [0x24,0x01]
+; O0-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-ZU-NEXT: # kill: def $rax killed $eax
+; O0-ZU-NEXT: imulq %rdi, %rax # encoding: [0x48,0x0f,0xaf,0xc7]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%and = and i64 %val, -1048576
%cmp = icmp eq i64 %and, 0
%z = zext i1 %cmp to i64
@@ -1047,25 +1062,25 @@ define i32 @highmask_i64_mask8(i64 %val) {
;
; NDD-LABEL: highmask_i64_mask8:
; NDD: # %bb.0:
+; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: testq $-16, %rdi # encoding: [0x48,0xf7,0xc7,0xf0,0xff,0xff,0xff]
-; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: highmask_i64_mask8:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: testq $-16, %rdi # encoding: [0x48,0xf7,0xc7,0xf0,0xff,0xff,0xff]
-; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: highmask_i64_mask8:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: andq $-16, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0xe7,0xf0]
-; O0-NDD-ZU-NEXT: cmpq $0, %rax # encoding: [0x48,0x83,0xf8,0x00]
-; O0-NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
-; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: highmask_i64_mask8:
+; ZU: # %bb.0:
+; ZU-NEXT: testq $-16, %rdi # encoding: [0x48,0xf7,0xc7,0xf0,0xff,0xff,0xff]
+; ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: highmask_i64_mask8:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: andq $-16, %rdi # encoding: [0x48,0x83,0xe7,0xf0]
+; O0-ZU-NEXT: cmpq $0, %rdi # encoding: [0x48,0x83,0xff,0x00]
+; O0-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; O0-ZU-NEXT: andb $1, %al # encoding: [0x24,0x01]
+; O0-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%and = and i64 %val, -16
%cmp = icmp ne i64 %and, 0
%ret = zext i1 %cmp to i32
@@ -1082,27 +1097,27 @@ define i32 @lowmask_i64_mask64(i64 %val) {
;
; NDD-LABEL: lowmask_i64_mask64:
; NDD: # %bb.0:
+; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: shlq $16, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xe7,0x10]
-; NDD-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: lowmask_i64_mask64:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: shlq $16, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xe7,0x10]
-; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: lowmask_i64_mask64:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: movabsq $281474976710655, %rax # encoding: [0x48,0xb8,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00]
-; O0-NDD-ZU-NEXT: # imm = 0xFFFFFFFFFFFF
-; O0-NDD-ZU-NEXT: andq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x21,0xf8]
-; O0-NDD-ZU-NEXT: cmpq $0, %rax # encoding: [0x48,0x83,0xf8,0x00]
-; O0-NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
-; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: lowmask_i64_mask64:
+; ZU: # %bb.0:
+; ZU-NEXT: shlq $16, %rdi # encoding: [0x48,0xc1,0xe7,0x10]
+; ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: lowmask_i64_mask64:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: movabsq $281474976710655, %rax # encoding: [0x48,0xb8,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00]
+; O0-ZU-NEXT: # imm = 0xFFFFFFFFFFFF
+; O0-ZU-NEXT: andq %rax, %rdi # encoding: [0x48,0x21,0xc7]
+; O0-ZU-NEXT: cmpq $0, %rdi # encoding: [0x48,0x83,0xff,0x00]
+; O0-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; O0-ZU-NEXT: andb $1, %al # encoding: [0x24,0x01]
+; O0-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%and = and i64 %val, 281474976710655
%cmp = icmp eq i64 %and, 0
%ret = zext i1 %cmp to i32
@@ -1121,31 +1136,33 @@ define i64 @lowmask_i64_mask64_extra_use(i64 %val) nounwind {
;
; NDD-LABEL: lowmask_i64_mask64_extra_use:
; NDD: # %bb.0:
-; NDD-NEXT: shlq $16, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xc1,0xe7,0x10]
-; NDD-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; NDD-NEXT: shlq $16, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0xc1,0xe7,0x10]
+; NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NDD-NEXT: imulq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0xaf,0xc7]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: lowmask_i64_mask64_extra_use:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: shlq $16, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xc1,0xe7,0x10]
-; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; NDD-ZU-NEXT: imulq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0xaf,0xc7]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: lowmask_i64_mask64_extra_use:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: movabsq $281474976710655, %rax # encoding: [0x48,0xb8,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00]
-; O0-NDD-ZU-NEXT: # imm = 0xFFFFFFFFFFFF
-; O0-NDD-ZU-NEXT: andq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x21,0xf8]
-; O0-NDD-ZU-NEXT: cmpq $0, %rax # encoding: [0x48,0x83,0xf8,0x00]
-; O0-NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
-; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
-; O0-NDD-ZU-NEXT: # kill: def $rax killed $eax
-; O0-NDD-ZU-NEXT: imulq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0xaf,0xc7]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: lowmask_i64_mask64_extra_use:
+; ZU: # %bb.0:
+; ZU-NEXT: movq %rdi, %rax # encoding: [0x48,0x89,0xf8]
+; ZU-NEXT: shlq $16, %rax # encoding: [0x48,0xc1,0xe0,0x10]
+; ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; ZU-NEXT: imulq %rdi, %rax # encoding: [0x48,0x0f,0xaf,0xc7]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: lowmask_i64_mask64_extra_use:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: movabsq $281474976710655, %rcx # encoding: [0x48,0xb9,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00]
+; O0-ZU-NEXT: # imm = 0xFFFFFFFFFFFF
+; O0-ZU-NEXT: movq %rdi, %rax # encoding: [0x48,0x89,0xf8]
+; O0-ZU-NEXT: andq %rcx, %rax # encoding: [0x48,0x21,0xc8]
+; O0-ZU-NEXT: cmpq $0, %rax # encoding: [0x48,0x83,0xf8,0x00]
+; O0-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; O0-ZU-NEXT: andb $1, %al # encoding: [0x24,0x01]
+; O0-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-ZU-NEXT: # kill: def $rax killed $eax
+; O0-ZU-NEXT: imulq %rdi, %rax # encoding: [0x48,0x0f,0xaf,0xc7]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%and = and i64 %val, 281474976710655
%cmp = icmp eq i64 %and, 0
%z = zext i1 %cmp to i64
@@ -1163,26 +1180,26 @@ define i32 @lowmask_i64_mask32(i64 %val) {
;
; NDD-LABEL: lowmask_i64_mask32:
; NDD: # %bb.0:
+; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: shlq $44, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xe7,0x2c]
-; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: lowmask_i64_mask32:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: shlq $44, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xe7,0x2c]
-; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: lowmask_i64_mask32:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: andq $1048575, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0xe7,0xff,0xff,0x0f,0x00]
-; O0-NDD-ZU-NEXT: # imm = 0xFFFFF
-; O0-NDD-ZU-NEXT: cmpq $0, %rax # encoding: [0x48,0x83,0xf8,0x00]
-; O0-NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
-; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: lowmask_i64_mask32:
+; ZU: # %bb.0:
+; ZU-NEXT: shlq $44, %rdi # encoding: [0x48,0xc1,0xe7,0x2c]
+; ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: lowmask_i64_mask32:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: andq $1048575, %rdi # encoding: [0x48,0x81,0xe7,0xff,0xff,0x0f,0x00]
+; O0-ZU-NEXT: # imm = 0xFFFFF
+; O0-ZU-NEXT: cmpq $0, %rdi # encoding: [0x48,0x83,0xff,0x00]
+; O0-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; O0-ZU-NEXT: andb $1, %al # encoding: [0x24,0x01]
+; O0-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%and = and i64 %val, 1048575
%cmp = icmp ne i64 %and, 0
%ret = zext i1 %cmp to i32
@@ -1201,32 +1218,33 @@ define i64 @lowmask_i64_mask32_extra_use(i64 %val) nounwind {
;
; NDD-LABEL: lowmask_i64_mask32_extra_use:
; NDD: # %bb.0:
+; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: testl $1048575, %edi # encoding: [0xf7,0xc7,0xff,0xff,0x0f,0x00]
; NDD-NEXT: # imm = 0xFFFFF
-; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
; NDD-NEXT: imulq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0xaf,0xc7]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: lowmask_i64_mask32_extra_use:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: testl $1048575, %edi # encoding: [0xf7,0xc7,0xff,0xff,0x0f,0x00]
-; NDD-ZU-NEXT: # imm = 0xFFFFF
-; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; NDD-ZU-NEXT: imulq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0xaf,0xc7]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: lowmask_i64_mask32_extra_use:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: andq $1048575, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0xe7,0xff,0xff,0x0f,0x00]
-; O0-NDD-ZU-NEXT: # imm = 0xFFFFF
-; O0-NDD-ZU-NEXT: cmpq $0, %rax # encoding: [0x48,0x83,0xf8,0x00]
-; O0-NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
-; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
-; O0-NDD-ZU-NEXT: # kill: def $rax killed $eax
-; O0-NDD-ZU-NEXT: imulq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0xaf,0xc7]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: lowmask_i64_mask32_extra_use:
+; ZU: # %bb.0:
+; ZU-NEXT: testl $1048575, %edi # encoding: [0xf7,0xc7,0xff,0xff,0x0f,0x00]
+; ZU-NEXT: # imm = 0xFFFFF
+; ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; ZU-NEXT: imulq %rdi, %rax # encoding: [0x48,0x0f,0xaf,0xc7]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: lowmask_i64_mask32_extra_use:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: movq %rdi, %rax # encoding: [0x48,0x89,0xf8]
+; O0-ZU-NEXT: andq $1048575, %rax # encoding: [0x48,0x25,0xff,0xff,0x0f,0x00]
+; O0-ZU-NEXT: # imm = 0xFFFFF
+; O0-ZU-NEXT: cmpq $0, %rax # encoding: [0x48,0x83,0xf8,0x00]
+; O0-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; O0-ZU-NEXT: andb $1, %al # encoding: [0x24,0x01]
+; O0-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-ZU-NEXT: # kill: def $rax killed $eax
+; O0-ZU-NEXT: imulq %rdi, %rax # encoding: [0x48,0x0f,0xaf,0xc7]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%and = and i64 %val, 1048575
%cmp = icmp ne i64 %and, 0
%z = zext i1 %cmp to i64
@@ -1244,25 +1262,25 @@ define i32 @lowmask_i64_mask8(i64 %val) {
;
; NDD-LABEL: lowmask_i64_mask8:
; NDD: # %bb.0:
+; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: testb $31, %dil # encoding: [0x40,0xf6,0xc7,0x1f]
-; NDD-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: lowmask_i64_mask8:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: testb $31, %dil # encoding: [0x40,0xf6,0xc7,0x1f]
-; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: lowmask_i64_mask8:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: andq $31, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0xe7,0x1f]
-; O0-NDD-ZU-NEXT: cmpq $0, %rax # encoding: [0x48,0x83,0xf8,0x00]
-; O0-NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
-; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: lowmask_i64_mask8:
+; ZU: # %bb.0:
+; ZU-NEXT: testb $31, %dil # encoding: [0x40,0xf6,0xc7,0x1f]
+; ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: lowmask_i64_mask8:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: andq $31, %rdi # encoding: [0x48,0x83,0xe7,0x1f]
+; O0-ZU-NEXT: cmpq $0, %rdi # encoding: [0x48,0x83,0xff,0x00]
+; O0-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; O0-ZU-NEXT: andb $1, %al # encoding: [0x24,0x01]
+; O0-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%and = and i64 %val, 31
%cmp = icmp eq i64 %and, 0
%ret = zext i1 %cmp to i32
@@ -1280,28 +1298,28 @@ define i32 @highmask_i32_mask32(i32 %val) {
;
; NDD-LABEL: highmask_i32_mask32:
; NDD: # %bb.0:
+; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: testl $-1048576, %edi # encoding: [0xf7,0xc7,0x00,0x00,0xf0,0xff]
; NDD-NEXT: # imm = 0xFFF00000
-; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: highmask_i32_mask32:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: testl $-1048576, %edi # encoding: [0xf7,0xc7,0x00,0x00,0xf0,0xff]
-; NDD-ZU-NEXT: # imm = 0xFFF00000
-; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: highmask_i32_mask32:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: andl $-1048576, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xe7,0x00,0x00,0xf0,0xff]
-; O0-NDD-ZU-NEXT: # imm = 0xFFF00000
-; O0-NDD-ZU-NEXT: cmpl $0, %eax # encoding: [0x83,0xf8,0x00]
-; O0-NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
-; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: highmask_i32_mask32:
+; ZU: # %bb.0:
+; ZU-NEXT: testl $-1048576, %edi # encoding: [0xf7,0xc7,0x00,0x00,0xf0,0xff]
+; ZU-NEXT: # imm = 0xFFF00000
+; ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: highmask_i32_mask32:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: andl $-1048576, %edi # encoding: [0x81,0xe7,0x00,0x00,0xf0,0xff]
+; O0-ZU-NEXT: # imm = 0xFFF00000
+; O0-ZU-NEXT: cmpl $0, %edi # encoding: [0x83,0xff,0x00]
+; O0-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; O0-ZU-NEXT: andb $1, %al # encoding: [0x24,0x01]
+; O0-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%and = and i32 %val, -1048576
%cmp = icmp ne i32 %and, 0
%ret = zext i1 %cmp to i32
@@ -1318,25 +1336,25 @@ define i32 @highmask_i32_mask8(i32 %val) {
;
; NDD-LABEL: highmask_i32_mask8:
; NDD: # %bb.0:
+; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: testl $-16, %edi # encoding: [0xf7,0xc7,0xf0,0xff,0xff,0xff]
-; NDD-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: highmask_i32_mask8:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: testl $-16, %edi # encoding: [0xf7,0xc7,0xf0,0xff,0xff,0xff]
-; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: highmask_i32_mask8:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: andl $-16, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xe7,0xf0]
-; O0-NDD-ZU-NEXT: cmpl $0, %eax # encoding: [0x83,0xf8,0x00]
-; O0-NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
-; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: highmask_i32_mask8:
+; ZU: # %bb.0:
+; ZU-NEXT: testl $-16, %edi # encoding: [0xf7,0xc7,0xf0,0xff,0xff,0xff]
+; ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: highmask_i32_mask8:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: andl $-16, %edi # encoding: [0x83,0xe7,0xf0]
+; O0-ZU-NEXT: cmpl $0, %edi # encoding: [0x83,0xff,0x00]
+; O0-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; O0-ZU-NEXT: andb $1, %al # encoding: [0x24,0x01]
+; O0-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%and = and i32 %val, -16
%cmp = icmp eq i32 %and, 0
%ret = zext i1 %cmp to i32
@@ -1354,28 +1372,28 @@ define i32 @lowmask_i32_mask32(i32 %val) {
;
; NDD-LABEL: lowmask_i32_mask32:
; NDD: # %bb.0:
+; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: testl $1048575, %edi # encoding: [0xf7,0xc7,0xff,0xff,0x0f,0x00]
; NDD-NEXT: # imm = 0xFFFFF
-; NDD-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: lowmask_i32_mask32:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: testl $1048575, %edi # encoding: [0xf7,0xc7,0xff,0xff,0x0f,0x00]
-; NDD-ZU-NEXT: # imm = 0xFFFFF
-; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: lowmask_i32_mask32:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: andl $1048575, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xe7,0xff,0xff,0x0f,0x00]
-; O0-NDD-ZU-NEXT: # imm = 0xFFFFF
-; O0-NDD-ZU-NEXT: cmpl $0, %eax # encoding: [0x83,0xf8,0x00]
-; O0-NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
-; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: lowmask_i32_mask32:
+; ZU: # %bb.0:
+; ZU-NEXT: testl $1048575, %edi # encoding: [0xf7,0xc7,0xff,0xff,0x0f,0x00]
+; ZU-NEXT: # imm = 0xFFFFF
+; ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: lowmask_i32_mask32:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: andl $1048575, %edi # encoding: [0x81,0xe7,0xff,0xff,0x0f,0x00]
+; O0-ZU-NEXT: # imm = 0xFFFFF
+; O0-ZU-NEXT: cmpl $0, %edi # encoding: [0x83,0xff,0x00]
+; O0-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; O0-ZU-NEXT: andb $1, %al # encoding: [0x24,0x01]
+; O0-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%and = and i32 %val, 1048575
%cmp = icmp eq i32 %and, 0
%ret = zext i1 %cmp to i32
@@ -1392,25 +1410,25 @@ define i32 @lowmask_i32_mask8(i32 %val) {
;
; NDD-LABEL: lowmask_i32_mask8:
; NDD: # %bb.0:
+; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; NDD-NEXT: testb $31, %dil # encoding: [0x40,0xf6,0xc7,0x1f]
-; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: lowmask_i32_mask8:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: testb $31, %dil # encoding: [0x40,0xf6,0xc7,0x1f]
-; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: lowmask_i32_mask8:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: andl $31, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xe7,0x1f]
-; O0-NDD-ZU-NEXT: cmpl $0, %eax # encoding: [0x83,0xf8,0x00]
-; O0-NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; O0-NDD-ZU-NEXT: andb $1, %al # EVEX TO LEGACY Compression encoding: [0x24,0x01]
-; O0-NDD-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: lowmask_i32_mask8:
+; ZU: # %bb.0:
+; ZU-NEXT: testb $31, %dil # encoding: [0x40,0xf6,0xc7,0x1f]
+; ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: lowmask_i32_mask8:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: andl $31, %edi # encoding: [0x83,0xe7,0x1f]
+; O0-ZU-NEXT: cmpl $0, %edi # encoding: [0x83,0xff,0x00]
+; O0-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; O0-ZU-NEXT: andb $1, %al # encoding: [0x24,0x01]
+; O0-ZU-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%and = and i32 %val, 31
%cmp = icmp ne i32 %and, 0
%ret = zext i1 %cmp to i32
@@ -1429,23 +1447,23 @@ define i1 @shifted_mask64_testb(i64 %a) {
; NDD: # %bb.0:
; NDD-NEXT: shrq $50, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x32]
; NDD-NEXT: testb %dil, %dil # encoding: [0x40,0x84,0xff]
-; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: shifted_mask64_testb:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: shrq $50, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x32]
-; NDD-ZU-NEXT: testb %dil, %dil # encoding: [0x40,0x84,0xff]
-; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: shifted_mask64_testb:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: shrq $50, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xc1,0xef,0x32]
-; O0-NDD-ZU-NEXT: # kill: def $al killed $al killed $rax
-; O0-NDD-ZU-NEXT: testb %al, %al # encoding: [0x84,0xc0]
-; O0-NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: shifted_mask64_testb:
+; ZU: # %bb.0:
+; ZU-NEXT: shrq $50, %rdi # encoding: [0x48,0xc1,0xef,0x32]
+; ZU-NEXT: testb %dil, %dil # encoding: [0x40,0x84,0xff]
+; ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: shifted_mask64_testb:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: shrq $50, %rdi # encoding: [0x48,0xc1,0xef,0x32]
+; O0-ZU-NEXT: movb %dil, %al # encoding: [0x40,0x88,0xf8]
+; O0-ZU-NEXT: testb %al, %al # encoding: [0x84,0xc0]
+; O0-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%v0 = and i64 %a, 287104476244869120 ; 0xff << 50
%v1 = icmp ne i64 %v0, 0
ret i1 %v1
@@ -1463,23 +1481,23 @@ define i1 @shifted_mask64_testw(i64 %a) {
; NDD: # %bb.0:
; NDD-NEXT: shrq $33, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x21]
; NDD-NEXT: testw %di, %di # encoding: [0x66,0x85,0xff]
-; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: shifted_mask64_testw:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: shrq $33, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x21]
-; NDD-ZU-NEXT: testw %di, %di # encoding: [0x66,0x85,0xff]
-; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: shifted_mask64_testw:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: shrq $33, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xc1,0xef,0x21]
-; O0-NDD-ZU-NEXT: # kill: def $ax killed $ax killed $rax
-; O0-NDD-ZU-NEXT: testw %ax, %ax # encoding: [0x66,0x85,0xc0]
-; O0-NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: shifted_mask64_testw:
+; ZU: # %bb.0:
+; ZU-NEXT: shrq $33, %rdi # encoding: [0x48,0xc1,0xef,0x21]
+; ZU-NEXT: testw %di, %di # encoding: [0x66,0x85,0xff]
+; ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: shifted_mask64_testw:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: shrq $33, %rdi # encoding: [0x48,0xc1,0xef,0x21]
+; O0-ZU-NEXT: movw %di, %ax # encoding: [0x66,0x89,0xf8]
+; O0-ZU-NEXT: testw %ax, %ax # encoding: [0x66,0x85,0xc0]
+; O0-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%v0 = and i64 %a, 562941363486720 ; 0xffff << 33
%v1 = icmp ne i64 %v0, 0
ret i1 %v1
@@ -1497,23 +1515,23 @@ define i1 @shifted_mask64_testl(i64 %a) {
; NDD: # %bb.0:
; NDD-NEXT: shrq $7, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x07]
; NDD-NEXT: testl %edi, %edi # encoding: [0x85,0xff]
-; NDD-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: shifted_mask64_testl:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: shrq $7, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xef,0x07]
-; NDD-ZU-NEXT: testl %edi, %edi # encoding: [0x85,0xff]
-; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: shifted_mask64_testl:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: shrq $7, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xc1,0xef,0x07]
-; O0-NDD-ZU-NEXT: # kill: def $eax killed $eax killed $rax
-; O0-NDD-ZU-NEXT: testl %eax, %eax # encoding: [0x85,0xc0]
-; O0-NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: shifted_mask64_testl:
+; ZU: # %bb.0:
+; ZU-NEXT: shrq $7, %rdi # encoding: [0x48,0xc1,0xef,0x07]
+; ZU-NEXT: testl %edi, %edi # encoding: [0x85,0xff]
+; ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: shifted_mask64_testl:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: shrq $7, %rdi # encoding: [0x48,0xc1,0xef,0x07]
+; O0-ZU-NEXT: movl %edi, %eax # encoding: [0x89,0xf8]
+; O0-ZU-NEXT: testl %eax, %eax # encoding: [0x85,0xc0]
+; O0-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%v0 = and i64 %a, 549755813760 ; 0xffffffff << 7
%v1 = icmp eq i64 %v0, 0
ret i1 %v1
@@ -1535,31 +1553,31 @@ define i1 @shifted_mask64_extra_use_const(i64 %a) {
; NDD-NEXT: movabsq $287104476244869120, %rcx # encoding: [0x48,0xb9,0x00,0x00,0x00,0x00,0x00,0x00,0xfc,0x03]
; NDD-NEXT: # imm = 0x3FC000000000000
; NDD-NEXT: testq %rcx, %rdi # encoding: [0x48,0x85,0xcf]
-; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
; NDD-NEXT: movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A]
; NDD-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: shifted_mask64_extra_use_const:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: movabsq $287104476244869120, %rcx # encoding: [0x48,0xb9,0x00,0x00,0x00,0x00,0x00,0x00,0xfc,0x03]
-; NDD-ZU-NEXT: # imm = 0x3FC000000000000
-; NDD-ZU-NEXT: testq %rcx, %rdi # encoding: [0x48,0x85,0xcf]
-; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; NDD-ZU-NEXT: movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A]
-; NDD-ZU-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: shifted_mask64_extra_use_const:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: movabsq $287104476244869120, %rcx # encoding: [0x48,0xb9,0x00,0x00,0x00,0x00,0x00,0x00,0xfc,0x03]
-; O0-NDD-ZU-NEXT: # imm = 0x3FC000000000000
-; O0-NDD-ZU-NEXT: andq %rcx, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x21,0xcf]
-; O0-NDD-ZU-NEXT: testq %rax, %rax # encoding: [0x48,0x85,0xc0]
-; O0-NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; O0-NDD-ZU-NEXT: movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A]
-; O0-NDD-ZU-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: shifted_mask64_extra_use_const:
+; ZU: # %bb.0:
+; ZU-NEXT: movabsq $287104476244869120, %rcx # encoding: [0x48,0xb9,0x00,0x00,0x00,0x00,0x00,0x00,0xfc,0x03]
+; ZU-NEXT: # imm = 0x3FC000000000000
+; ZU-NEXT: testq %rcx, %rdi # encoding: [0x48,0x85,0xcf]
+; ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; ZU-NEXT: movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A]
+; ZU-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: shifted_mask64_extra_use_const:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: movabsq $287104476244869120, %rcx # encoding: [0x48,0xb9,0x00,0x00,0x00,0x00,0x00,0x00,0xfc,0x03]
+; O0-ZU-NEXT: # imm = 0x3FC000000000000
+; O0-ZU-NEXT: andq %rcx, %rdi # encoding: [0x48,0x21,0xcf]
+; O0-ZU-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff]
+; O0-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; O0-ZU-NEXT: movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A]
+; O0-ZU-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%v0 = and i64 %a, 287104476244869120 ; 0xff << 50
%v1 = icmp ne i64 %v0, 0
store i64 287104476244869120, ptr @d64
@@ -1582,30 +1600,30 @@ define i1 @shifted_mask64_extra_use_and(i64 %a) {
; NDD-NEXT: movabsq $287104476244869120, %rax # encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0x00,0xfc,0x03]
; NDD-NEXT: # imm = 0x3FC000000000000
; NDD-NEXT: andq %rax, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x21,0xc7]
-; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
; NDD-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
; NDD-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: shifted_mask64_extra_use_and:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: movabsq $287104476244869120, %rax # encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0x00,0xfc,0x03]
-; NDD-ZU-NEXT: # imm = 0x3FC000000000000
-; NDD-ZU-NEXT: andq %rax, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x21,0xc7]
-; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; NDD-ZU-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
-; NDD-ZU-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: shifted_mask64_extra_use_and:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: movabsq $287104476244869120, %rax # encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0x00,0xfc,0x03]
-; O0-NDD-ZU-NEXT: # imm = 0x3FC000000000000
-; O0-NDD-ZU-NEXT: andq %rax, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x21,0xc7]
-; O0-NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; O0-NDD-ZU-NEXT: movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A]
-; O0-NDD-ZU-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: shifted_mask64_extra_use_and:
+; ZU: # %bb.0:
+; ZU-NEXT: movabsq $287104476244869120, %rcx # encoding: [0x48,0xb9,0x00,0x00,0x00,0x00,0x00,0x00,0xfc,0x03]
+; ZU-NEXT: # imm = 0x3FC000000000000
+; ZU-NEXT: andq %rdi, %rcx # encoding: [0x48,0x21,0xf9]
+; ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; ZU-NEXT: movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A]
+; ZU-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: shifted_mask64_extra_use_and:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: movabsq $287104476244869120, %rax # encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0x00,0xfc,0x03]
+; O0-ZU-NEXT: # imm = 0x3FC000000000000
+; O0-ZU-NEXT: andq %rax, %rdi # encoding: [0x48,0x21,0xc7]
+; O0-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; O0-ZU-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
+; O0-ZU-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%v0 = and i64 %a, 287104476244869120 ; 0xff << 50
%v1 = icmp ne i64 %v0, 0
store i64 %v0, ptr @d64
@@ -1624,23 +1642,23 @@ define i1 @shifted_mask32_testl_immediate(i64 %a) {
; NDD: # %bb.0:
; NDD-NEXT: testl $66846720, %edi # encoding: [0xf7,0xc7,0x00,0x00,0xfc,0x03]
; NDD-NEXT: # imm = 0x3FC0000
-; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: shifted_mask32_testl_immediate:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: testl $66846720, %edi # encoding: [0xf7,0xc7,0x00,0x00,0xfc,0x03]
-; NDD-ZU-NEXT: # imm = 0x3FC0000
-; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: shifted_mask32_testl_immediate:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: movl %edi, %eax # encoding: [0x89,0xf8]
-; O0-NDD-ZU-NEXT: testl $66846720, %eax # encoding: [0xa9,0x00,0x00,0xfc,0x03]
-; O0-NDD-ZU-NEXT: # imm = 0x3FC0000
-; O0-NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: shifted_mask32_testl_immediate:
+; ZU: # %bb.0:
+; ZU-NEXT: testl $66846720, %edi # encoding: [0xf7,0xc7,0x00,0x00,0xfc,0x03]
+; ZU-NEXT: # imm = 0x3FC0000
+; ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: shifted_mask32_testl_immediate:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: movl %edi, %eax # encoding: [0x89,0xf8]
+; O0-ZU-NEXT: testl $66846720, %eax # encoding: [0xa9,0x00,0x00,0xfc,0x03]
+; O0-ZU-NEXT: # imm = 0x3FC0000
+; O0-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%v0 = and i64 %a, 66846720 ; 0xff << 18
%v1 = icmp ne i64 %v0, 0
ret i1 %v1
@@ -1661,32 +1679,32 @@ define i1 @shifted_mask32_extra_use_const(i64 %a) {
; NDD: # %bb.0:
; NDD-NEXT: testl $66846720, %edi # encoding: [0xf7,0xc7,0x00,0x00,0xfc,0x03]
; NDD-NEXT: # imm = 0x3FC0000
-; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
; NDD-NEXT: movq $66846720, d64(%rip) # encoding: [0x48,0xc7,0x05,A,A,A,A,0x00,0x00,0xfc,0x03]
; NDD-NEXT: # fixup A - offset: 3, value: d64-8, kind: reloc_riprel_4byte
; NDD-NEXT: # imm = 0x3FC0000
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: shifted_mask32_extra_use_const:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: testl $66846720, %edi # encoding: [0xf7,0xc7,0x00,0x00,0xfc,0x03]
-; NDD-ZU-NEXT: # imm = 0x3FC0000
-; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; NDD-ZU-NEXT: movq $66846720, d64(%rip) # encoding: [0x48,0xc7,0x05,A,A,A,A,0x00,0x00,0xfc,0x03]
-; NDD-ZU-NEXT: # fixup A - offset: 3, value: d64-8, kind: reloc_riprel_4byte
-; NDD-ZU-NEXT: # imm = 0x3FC0000
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: shifted_mask32_extra_use_const:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: movl %edi, %eax # encoding: [0x89,0xf8]
-; O0-NDD-ZU-NEXT: testl $66846720, %eax # encoding: [0xa9,0x00,0x00,0xfc,0x03]
-; O0-NDD-ZU-NEXT: # imm = 0x3FC0000
-; O0-NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; O0-NDD-ZU-NEXT: movq $66846720, d64(%rip) # encoding: [0x48,0xc7,0x05,A,A,A,A,0x00,0x00,0xfc,0x03]
-; O0-NDD-ZU-NEXT: # fixup A - offset: 3, value: d64-8, kind: reloc_riprel_4byte
-; O0-NDD-ZU-NEXT: # imm = 0x3FC0000
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: shifted_mask32_extra_use_const:
+; ZU: # %bb.0:
+; ZU-NEXT: testl $66846720, %edi # encoding: [0xf7,0xc7,0x00,0x00,0xfc,0x03]
+; ZU-NEXT: # imm = 0x3FC0000
+; ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; ZU-NEXT: movq $66846720, d64(%rip) # encoding: [0x48,0xc7,0x05,A,A,A,A,0x00,0x00,0xfc,0x03]
+; ZU-NEXT: # fixup A - offset: 3, value: d64-8, kind: reloc_riprel_4byte
+; ZU-NEXT: # imm = 0x3FC0000
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: shifted_mask32_extra_use_const:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: movl %edi, %eax # encoding: [0x89,0xf8]
+; O0-ZU-NEXT: testl $66846720, %eax # encoding: [0xa9,0x00,0x00,0xfc,0x03]
+; O0-ZU-NEXT: # imm = 0x3FC0000
+; O0-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; O0-ZU-NEXT: movq $66846720, d64(%rip) # encoding: [0x48,0xc7,0x05,A,A,A,A,0x00,0x00,0xfc,0x03]
+; O0-ZU-NEXT: # fixup A - offset: 3, value: d64-8, kind: reloc_riprel_4byte
+; O0-ZU-NEXT: # imm = 0x3FC0000
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%v0 = and i64 %a, 66846720 ; 0xff << 18
%v1 = icmp ne i64 %v0, 0
store i64 66846720, ptr @d64
@@ -1707,28 +1725,28 @@ define i1 @shifted_mask32_extra_use_and(i64 %a) {
; NDD: # %bb.0:
; NDD-NEXT: andq $66846720, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x81,0xe7,0x00,0x00,0xfc,0x03]
; NDD-NEXT: # imm = 0x3FC0000
-; NDD-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0]
; NDD-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
; NDD-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: shifted_mask32_extra_use_and:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: andq $66846720, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x81,0xe7,0x00,0x00,0xfc,0x03]
-; NDD-ZU-NEXT: # imm = 0x3FC0000
-; NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; NDD-ZU-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
-; NDD-ZU-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: shifted_mask32_extra_use_and:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: andq $66846720, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x81,0xe7,0x00,0x00,0xfc,0x03]
-; O0-NDD-ZU-NEXT: # imm = 0x3FC0000
-; O0-NDD-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
-; O0-NDD-ZU-NEXT: movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A]
-; O0-NDD-ZU-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: shifted_mask32_extra_use_and:
+; ZU: # %bb.0:
+; ZU-NEXT: andq $66846720, %rdi # encoding: [0x48,0x81,0xe7,0x00,0x00,0xfc,0x03]
+; ZU-NEXT: # imm = 0x3FC0000
+; ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; ZU-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
+; ZU-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: shifted_mask32_extra_use_and:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: andq $66846720, %rdi # encoding: [0x48,0x81,0xe7,0x00,0x00,0xfc,0x03]
+; O0-ZU-NEXT: # imm = 0x3FC0000
+; O0-ZU-NEXT: setzune %al # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0]
+; O0-ZU-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
+; O0-ZU-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%v0 = and i64 %a, 66846720 ; 0xff << 50
%v1 = icmp ne i64 %v0, 0
store i64 %v0, ptr @d64
@@ -1753,23 +1771,26 @@ define { i64, i64 } @pr39968(i64, i64, i32) {
; NDD-NEXT: cmovneq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0x45,0xc7]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: pr39968:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; NDD-ZU-NEXT: testb $64, %dl # encoding: [0xf6,0xc2,0x40]
-; NDD-ZU-NEXT: cmovneq %rdi, %rsi, %rdx # encoding: [0x62,0xf4,0xec,0x18,0x45,0xf7]
-; NDD-ZU-NEXT: cmovneq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0x45,0xc7]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: pr39968:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: movb %dl, %cl # encoding: [0x88,0xd1]
-; O0-NDD-ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; O0-NDD-ZU-NEXT: testb $64, %cl # encoding: [0xf6,0xc1,0x40]
-; O0-NDD-ZU-NEXT: cmovneq %rdi, %rsi, %rdx # encoding: [0x62,0xf4,0xec,0x18,0x45,0xf7]
-; O0-NDD-ZU-NEXT: # kill: def $rax killed $eax
-; O0-NDD-ZU-NEXT: cmovneq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0x45,0xc7]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: pr39968:
+; ZU: # %bb.0:
+; ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; ZU-NEXT: testb $64, %dl # encoding: [0xf6,0xc2,0x40]
+; ZU-NEXT: cmovneq %rdi, %rsi # encoding: [0x48,0x0f,0x45,0xf7]
+; ZU-NEXT: cmovneq %rdi, %rax # encoding: [0x48,0x0f,0x45,0xc7]
+; ZU-NEXT: movq %rsi, %rdx # encoding: [0x48,0x89,0xf2]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: pr39968:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: movl %edx, %eax # encoding: [0x89,0xd0]
+; O0-ZU-NEXT: movq %rsi, %rdx # encoding: [0x48,0x89,0xf2]
+; O0-ZU-NEXT: movb %al, %cl # encoding: [0x88,0xc1]
+; O0-ZU-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; O0-ZU-NEXT: testb $64, %cl # encoding: [0xf6,0xc1,0x40]
+; O0-ZU-NEXT: cmovneq %rdi, %rdx # encoding: [0x48,0x0f,0x45,0xd7]
+; O0-ZU-NEXT: # kill: def $rax killed $eax
+; O0-ZU-NEXT: cmovneq %rdi, %rax # encoding: [0x48,0x0f,0x45,0xc7]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%4 = and i32 %2, 64
%5 = icmp ne i32 %4, 0
%6 = select i1 %5, i64 %0, i64 %1
@@ -1794,33 +1815,33 @@ define i32 @pr42189(i16 signext %c) {
; CHECK-NEXT: # encoding: [0xeb,A]
; CHECK-NEXT: # fixup A - offset: 1, value: g at PLT-1, kind: FK_PCRel_1
;
-; O0-NDD-ZU-LABEL: pr42189:
-; O0-NDD-ZU: # %bb.0: # %entry
-; O0-NDD-ZU-NEXT: pushq %rax # encoding: [0x50]
-; O0-NDD-ZU-NEXT: .cfi_def_cfa_offset 16
-; O0-NDD-ZU-NEXT: movw %di, %ax # encoding: [0x66,0x89,0xf8]
-; O0-NDD-ZU-NEXT: cmpw $32767, %ax # encoding: [0x66,0x3d,0xff,0x7f]
-; O0-NDD-ZU-NEXT: # imm = 0x7FFF
-; O0-NDD-ZU-NEXT: jne .LBB45_2 # encoding: [0x75,A]
-; O0-NDD-ZU-NEXT: # fixup A - offset: 1, value: .LBB45_2-1, kind: FK_PCRel_1
-; O0-NDD-ZU-NEXT: # %bb.1: # %if.then
-; O0-NDD-ZU-NEXT: callq g at PLT # encoding: [0xe8,A,A,A,A]
-; O0-NDD-ZU-NEXT: # fixup A - offset: 1, value: g at PLT-4, kind: FK_PCRel_4
-; O0-NDD-ZU-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
-; O0-NDD-ZU-NEXT: # encoding: [0x89,0x44,0x24,0x04]
-; O0-NDD-ZU-NEXT: jmp .LBB45_3 # encoding: [0xeb,A]
-; O0-NDD-ZU-NEXT: # fixup A - offset: 1, value: .LBB45_3-1, kind: FK_PCRel_1
-; O0-NDD-ZU-NEXT: .LBB45_2: # %if.end
-; O0-NDD-ZU-NEXT: callq f at PLT # encoding: [0xe8,A,A,A,A]
-; O0-NDD-ZU-NEXT: # fixup A - offset: 1, value: f at PLT-4, kind: FK_PCRel_4
-; O0-NDD-ZU-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
-; O0-NDD-ZU-NEXT: # encoding: [0x89,0x44,0x24,0x04]
-; O0-NDD-ZU-NEXT: .LBB45_3: # %return
-; O0-NDD-ZU-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
-; O0-NDD-ZU-NEXT: # encoding: [0x8b,0x44,0x24,0x04]
-; O0-NDD-ZU-NEXT: popq %rcx # encoding: [0x59]
-; O0-NDD-ZU-NEXT: .cfi_def_cfa_offset 8
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; O0-ZU-LABEL: pr42189:
+; O0-ZU: # %bb.0: # %entry
+; O0-ZU-NEXT: pushq %rax # encoding: [0x50]
+; O0-ZU-NEXT: .cfi_def_cfa_offset 16
+; O0-ZU-NEXT: movw %di, %ax # encoding: [0x66,0x89,0xf8]
+; O0-ZU-NEXT: cmpw $32767, %ax # encoding: [0x66,0x3d,0xff,0x7f]
+; O0-ZU-NEXT: # imm = 0x7FFF
+; O0-ZU-NEXT: jne .LBB45_2 # encoding: [0x75,A]
+; O0-ZU-NEXT: # fixup A - offset: 1, value: .LBB45_2-1, kind: FK_PCRel_1
+; O0-ZU-NEXT: # %bb.1: # %if.then
+; O0-ZU-NEXT: callq g at PLT # encoding: [0xe8,A,A,A,A]
+; O0-ZU-NEXT: # fixup A - offset: 1, value: g at PLT-4, kind: FK_PCRel_4
+; O0-ZU-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; O0-ZU-NEXT: # encoding: [0x89,0x44,0x24,0x04]
+; O0-ZU-NEXT: jmp .LBB45_3 # encoding: [0xeb,A]
+; O0-ZU-NEXT: # fixup A - offset: 1, value: .LBB45_3-1, kind: FK_PCRel_1
+; O0-ZU-NEXT: .LBB45_2: # %if.end
+; O0-ZU-NEXT: callq f at PLT # encoding: [0xe8,A,A,A,A]
+; O0-ZU-NEXT: # fixup A - offset: 1, value: f at PLT-4, kind: FK_PCRel_4
+; O0-ZU-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; O0-ZU-NEXT: # encoding: [0x89,0x44,0x24,0x04]
+; O0-ZU-NEXT: .LBB45_3: # %return
+; O0-ZU-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
+; O0-ZU-NEXT: # encoding: [0x8b,0x44,0x24,0x04]
+; O0-ZU-NEXT: popq %rcx # encoding: [0x59]
+; O0-ZU-NEXT: .cfi_def_cfa_offset 8
+; O0-ZU-NEXT: retq # encoding: [0xc3]
entry:
%cmp = icmp eq i16 %c, 32767
br i1 %cmp, label %if.then, label %if.end
@@ -1855,25 +1876,26 @@ define i1 @fold_test_and_with_chain(ptr %x, ptr %y, i32 %z) {
; NDD-LABEL: fold_test_and_with_chain:
; NDD: # %bb.0:
; NDD-NEXT: testl %edx, (%rdi) # encoding: [0x85,0x17]
-; NDD-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; NDD-NEXT: movl %edx, (%rsi) # encoding: [0x89,0x16]
; NDD-NEXT: retq # encoding: [0xc3]
;
-; NDD-ZU-LABEL: fold_test_and_with_chain:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: testl %edx, (%rdi) # encoding: [0x85,0x17]
-; NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; NDD-ZU-NEXT: movl %edx, (%rsi) # encoding: [0x89,0x16]
-; NDD-ZU-NEXT: retq # encoding: [0xc3]
-;
-; O0-NDD-ZU-LABEL: fold_test_and_with_chain:
-; O0-NDD-ZU: # %bb.0:
-; O0-NDD-ZU-NEXT: movl (%rdi), %eax # encoding: [0x8b,0x07]
-; O0-NDD-ZU-NEXT: andl %edx, %eax # EVEX TO LEGACY Compression encoding: [0x21,0xd0]
-; O0-NDD-ZU-NEXT: testl %eax, %eax # encoding: [0x85,0xc0]
-; O0-NDD-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
-; O0-NDD-ZU-NEXT: movl %edx, (%rsi) # encoding: [0x89,0x16]
-; O0-NDD-ZU-NEXT: retq # encoding: [0xc3]
+; ZU-LABEL: fold_test_and_with_chain:
+; ZU: # %bb.0:
+; ZU-NEXT: testl %edx, (%rdi) # encoding: [0x85,0x17]
+; ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; ZU-NEXT: movl %edx, (%rsi) # encoding: [0x89,0x16]
+; ZU-NEXT: retq # encoding: [0xc3]
+;
+; O0-ZU-LABEL: fold_test_and_with_chain:
+; O0-ZU: # %bb.0:
+; O0-ZU-NEXT: movl (%rdi), %ecx # encoding: [0x8b,0x0f]
+; O0-ZU-NEXT: movl %edx, %eax # encoding: [0x89,0xd0]
+; O0-ZU-NEXT: andl %ecx, %eax # encoding: [0x21,0xc8]
+; O0-ZU-NEXT: testl %eax, %eax # encoding: [0x85,0xc0]
+; O0-ZU-NEXT: setzue %al # encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0]
+; O0-ZU-NEXT: movl %edx, (%rsi) # encoding: [0x89,0x16]
+; O0-ZU-NEXT: retq # encoding: [0xc3]
%a = load i32, ptr %x
%b = and i32 %z, %a
%c = icmp eq i32 %b, 0
diff --git a/llvm/test/CodeGen/X86/is_fpclass.ll b/llvm/test/CodeGen/X86/is_fpclass.ll
index 75506d37dea93..5957c202b498b 100644
--- a/llvm/test/CodeGen/X86/is_fpclass.ll
+++ b/llvm/test/CodeGen/X86/is_fpclass.ll
@@ -1,7 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-linux | FileCheck %s -check-prefixes=X86
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefixes=X64,X64-GENERIC
-; RUN: llc < %s -mtriple=x86_64-linux -mattr=+ndd | FileCheck %s -check-prefix=X64-NDD
+; RUN: llc < %s -mtriple=x86_64-linux -mattr=+ndd | FileCheck %s -check-prefixes=X64,X64-NDD
+; RUN: llc < %s -mtriple=x86_64-linux -mattr=+zu | FileCheck %s -check-prefix=X64-ZU
define i1 @isnan_f(float %x) {
; X86-LABEL: isnan_f:
@@ -20,11 +21,11 @@ define i1 @isnan_f(float %x) {
; X64-NEXT: setp %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: isnan_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: ucomiss %xmm0, %xmm0
-; X64-NDD-NEXT: setzup %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: isnan_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: ucomiss %xmm0, %xmm0
+; X64-ZU-NEXT: setzup %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 3) ; "nan"
ret i1 %0
@@ -47,11 +48,11 @@ define i1 @isnot_nan_f(float %x) {
; X64-NEXT: setnp %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: isnot_nan_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: ucomiss %xmm0, %xmm0
-; X64-NDD-NEXT: setzunp %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: isnot_nan_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: ucomiss %xmm0, %xmm0
+; X64-ZU-NEXT: setzunp %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1020) ; 0x3fc = "zero|subnormal|normal|inf"
ret i1 %0
@@ -80,16 +81,16 @@ define i1 @issignaling_f(float %x) {
; X64-NEXT: andb %cl, %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: issignaling_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NDD-NEXT: setzul %cl
-; X64-NDD-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-NDD-NEXT: setzuge %al
-; X64-NDD-NEXT: andb %cl, %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: issignaling_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-ZU-NEXT: setzul %cl
+; X64-ZU-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-ZU-NEXT: setzuge %al
+; X64-ZU-NEXT: andb %cl, %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1) ; "snan"
ret i1 %0
@@ -118,16 +119,16 @@ define i1 @not_issignaling_f(float %x) {
; X64-NEXT: orb %cl, %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: not_issignaling_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NDD-NEXT: setzuge %cl
-; X64-NDD-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-NDD-NEXT: setzul %al
-; X64-NDD-NEXT: orb %cl, %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: not_issignaling_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-ZU-NEXT: setzuge %cl
+; X64-ZU-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-ZU-NEXT: setzul %al
+; X64-ZU-NEXT: orb %cl, %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1022) ; ~"snan"
ret i1 %0
@@ -150,13 +151,13 @@ define i1 @isquiet_f(float %x) {
; X64-NEXT: setge %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: isquiet_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NDD-NEXT: setzuge %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: isquiet_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-ZU-NEXT: setzuge %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 2) ; "qnan"
ret i1 %0
@@ -179,13 +180,13 @@ define i1 @not_isquiet_f(float %x) {
; X64-NEXT: setl %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: not_isquiet_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NDD-NEXT: setzul %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: not_isquiet_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-ZU-NEXT: setzul %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1021) ; ~"qnan"
ret i1 %0
@@ -208,13 +209,13 @@ define i1 @isinf_f(float %x) {
; X64-NEXT: sete %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: isinf_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzue %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: isinf_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzue %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 516) ; 0x204 = "inf"
ret i1 %0
@@ -237,13 +238,13 @@ define i1 @not_isinf_f(float %x) {
; X64-NEXT: setne %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: not_isinf_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzune %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: not_isinf_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzune %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 507) ; ~0x204 = "~inf"
ret i1 %0
@@ -263,12 +264,12 @@ define i1 @is_plus_inf_f(float %x) {
; X64-NEXT: sete %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: is_plus_inf_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzue %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: is_plus_inf_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzue %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 512) ; 0x200 = "+inf"
ret i1 %0
@@ -288,12 +289,12 @@ define i1 @is_minus_inf_f(float %x) {
; X64-NEXT: sete %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: is_minus_inf_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
-; X64-NDD-NEXT: setzue %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: is_minus_inf_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
+; X64-ZU-NEXT: setzue %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 4) ; "-inf"
ret i1 %0
@@ -313,12 +314,12 @@ define i1 @not_is_minus_inf_f(float %x) {
; X64-NEXT: setne %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: not_is_minus_inf_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
-; X64-NDD-NEXT: setzune %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: not_is_minus_inf_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
+; X64-ZU-NEXT: setzune %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1019) ; ~"-inf"
ret i1 %0
@@ -341,13 +342,13 @@ define i1 @isfinite_f(float %x) {
; X64-NEXT: setl %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: isfinite_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzul %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: isfinite_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzul %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 504) ; 0x1f8 = "finite"
ret i1 %0
@@ -370,13 +371,13 @@ define i1 @not_isfinite_f(float %x) {
; X64-NEXT: setge %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: not_isfinite_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzuge %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: not_isfinite_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzuge %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 519) ; ~0x1f8 = "~finite"
ret i1 %0
@@ -396,12 +397,12 @@ define i1 @is_plus_finite_f(float %x) {
; X64-NEXT: setb %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: is_plus_finite_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzub %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: is_plus_finite_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzub %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 448) ; 0x1c0 = "+finite"
ret i1 %0
@@ -421,12 +422,12 @@ define i1 @not_is_plus_finite_f(float %x) {
; X64-NEXT: setae %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: not_is_plus_finite_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzuae %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: not_is_plus_finite_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzuae %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 575) ; ~0x1c0 = ~"+finite"
ret i1 %0
@@ -455,16 +456,16 @@ define i1 @is_minus_finite_f(float %x) {
; X64-NEXT: andb %cl, %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: is_minus_finite_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: testl %eax, %eax
-; X64-NDD-NEXT: setzus %cl
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzul %al
-; X64-NDD-NEXT: andb %cl, %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: is_minus_finite_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: testl %eax, %eax
+; X64-ZU-NEXT: setzus %cl
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzul %al
+; X64-ZU-NEXT: andb %cl, %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 56) ; 0x38 = "-finite"
ret i1 %0
@@ -493,16 +494,16 @@ define i1 @not_is_minus_finite_f(float %x) {
; X64-NEXT: orb %cl, %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: not_is_minus_finite_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: testl %eax, %eax
-; X64-NDD-NEXT: setzuns %cl
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzuge %al
-; X64-NDD-NEXT: orb %cl, %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: not_is_minus_finite_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: testl %eax, %eax
+; X64-ZU-NEXT: setzuns %cl
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzuge %al
+; X64-ZU-NEXT: orb %cl, %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 967) ; ~0x38 = ~"-finite"
ret i1 %0
@@ -527,14 +528,14 @@ define i1 @isnormal_f(float %x) #1 {
; X64-NEXT: setb %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: isnormal_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: addl $-8388608, %eax # imm = 0xFF800000
-; X64-NDD-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; X64-NDD-NEXT: setzub %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: isnormal_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: addl $-8388608, %eax # imm = 0xFF800000
+; X64-ZU-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
+; X64-ZU-NEXT: setzub %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 264) ; 0x108 = "normal"
ret i1 %0
@@ -559,14 +560,14 @@ define i1 @not_isnormal_f(float %x) #1 {
; X64-NEXT: setae %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: not_isnormal_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: addl $-8388608, %eax # imm = 0xFF800000
-; X64-NDD-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; X64-NDD-NEXT: setzuae %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: not_isnormal_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: addl $-8388608, %eax # imm = 0xFF800000
+; X64-ZU-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
+; X64-ZU-NEXT: setzuae %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 759) ; ~0x108 = "~normal"
ret i1 %0
@@ -597,17 +598,17 @@ define i1 @is_plus_normal_f(float %x) {
; X64-NEXT: andb %cl, %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: is_plus_normal_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: testl %eax, %eax
-; X64-NDD-NEXT: setzuns %cl
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: addl $-8388608, %eax # imm = 0xFF800000
-; X64-NDD-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; X64-NDD-NEXT: setzub %al
-; X64-NDD-NEXT: andb %cl, %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: is_plus_normal_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: testl %eax, %eax
+; X64-ZU-NEXT: setzuns %cl
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: addl $-8388608, %eax # imm = 0xFF800000
+; X64-ZU-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
+; X64-ZU-NEXT: setzub %al
+; X64-ZU-NEXT: andb %cl, %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 256) ; 0x100 = "+normal"
ret i1 %0
@@ -632,14 +633,14 @@ define i1 @issubnormal_f(float %x) {
; X64-NEXT: setb %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: issubnormal_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: decl %eax
-; X64-NDD-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
-; X64-NDD-NEXT: setzub %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: issubnormal_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: decl %eax
+; X64-ZU-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-ZU-NEXT: setzub %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 144) ; 0x90 = "subnormal"
ret i1 %0
@@ -664,14 +665,14 @@ define i1 @issubnormal_f_daz(float %x) #0 {
; X64-NEXT: setb %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: issubnormal_f_daz:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: decl %eax
-; X64-NDD-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
-; X64-NDD-NEXT: setzub %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: issubnormal_f_daz:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: decl %eax
+; X64-ZU-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-ZU-NEXT: setzub %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 144) ; 0x90 = "subnormal"
ret i1 %0
@@ -696,14 +697,14 @@ define i1 @issubnormal_f_maybe_daz(float %x) #1 {
; X64-NEXT: setb %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: issubnormal_f_maybe_daz:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: decl %eax
-; X64-NDD-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
-; X64-NDD-NEXT: setzub %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: issubnormal_f_maybe_daz:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: decl %eax
+; X64-ZU-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-ZU-NEXT: setzub %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 144) ; 0x90 = "subnormal"
ret i1 %0
@@ -728,14 +729,14 @@ define i1 @not_issubnormal_f(float %x) {
; X64-NEXT: setae %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: not_issubnormal_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: decl %eax
-; X64-NDD-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
-; X64-NDD-NEXT: setzuae %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: not_issubnormal_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: decl %eax
+; X64-ZU-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-ZU-NEXT: setzuae %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 879) ; ~0x90 = "~subnormal"
ret i1 %0
@@ -760,14 +761,14 @@ define i1 @not_issubnormal_f_daz(float %x) #0 {
; X64-NEXT: setae %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: not_issubnormal_f_daz:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: decl %eax
-; X64-NDD-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
-; X64-NDD-NEXT: setzuae %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: not_issubnormal_f_daz:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: decl %eax
+; X64-ZU-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-ZU-NEXT: setzuae %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 879) ; ~0x90 = "~subnormal"
ret i1 %0
@@ -792,14 +793,14 @@ define i1 @not_issubnormal_f_maybe_daz(float %x) #1 {
; X64-NEXT: setae %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: not_issubnormal_f_maybe_daz:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: decl %eax
-; X64-NDD-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
-; X64-NDD-NEXT: setzuae %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: not_issubnormal_f_maybe_daz:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: decl %eax
+; X64-ZU-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-ZU-NEXT: setzuae %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 879) ; ~0x90 = "~subnormal"
ret i1 %0
@@ -822,13 +823,13 @@ define i1 @is_plus_subnormal_f(float %x) {
; X64-NEXT: setb %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: is_plus_subnormal_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: decl %eax
-; X64-NDD-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
-; X64-NDD-NEXT: setzub %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: is_plus_subnormal_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: decl %eax
+; X64-ZU-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-ZU-NEXT: setzub %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 128) ; 0x80 = "+subnormal"
ret i1 %0
@@ -851,13 +852,13 @@ define i1 @not_is_plus_subnormal_f(float %x) {
; X64-NEXT: setae %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: not_is_plus_subnormal_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: decl %eax
-; X64-NDD-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
-; X64-NDD-NEXT: setzuae %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: not_is_plus_subnormal_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: decl %eax
+; X64-ZU-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-ZU-NEXT: setzuae %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 895) ; ~0x80 = ~"+subnormal"
ret i1 %0
@@ -888,17 +889,17 @@ define i1 @is_minus_subnormal_f(float %x) {
; X64-NEXT: andb %cl, %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: is_minus_subnormal_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: testl %eax, %eax
-; X64-NDD-NEXT: setzus %cl
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: decl %eax
-; X64-NDD-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
-; X64-NDD-NEXT: setzub %al
-; X64-NDD-NEXT: andb %cl, %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: is_minus_subnormal_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: testl %eax, %eax
+; X64-ZU-NEXT: setzus %cl
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: decl %eax
+; X64-ZU-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-ZU-NEXT: setzub %al
+; X64-ZU-NEXT: andb %cl, %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 16) ; 0x10 = "-subnormal"
ret i1 %0
@@ -929,17 +930,17 @@ define i1 @not_is_minus_subnormal_f(float %x) {
; X64-NEXT: orb %cl, %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: not_is_minus_subnormal_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: testl %eax, %eax
-; X64-NDD-NEXT: setzuns %cl
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: decl %eax
-; X64-NDD-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
-; X64-NDD-NEXT: setzuae %al
-; X64-NDD-NEXT: orb %cl, %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: not_is_minus_subnormal_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: testl %eax, %eax
+; X64-ZU-NEXT: setzuns %cl
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: decl %eax
+; X64-ZU-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-ZU-NEXT: setzuae %al
+; X64-ZU-NEXT: orb %cl, %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1007) ; ~0x10 = ~"-subnormal"
ret i1 %0
@@ -959,12 +960,12 @@ define i1 @iszero_f(float %x) {
; X64-NEXT: sete %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: iszero_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: setzue %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: iszero_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: setzue %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 96) ; 0x60 = "zero"
ret i1 %0
@@ -984,12 +985,12 @@ define i1 @iszero_f_daz(float %x) #0 {
; X64-NEXT: sete %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: iszero_f_daz:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: setzue %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: iszero_f_daz:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: setzue %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 96) ; 0x60 = "zero"
ret i1 %0
@@ -1009,12 +1010,12 @@ define i1 @iszero_f_maybe_daz(float %x) #1 {
; X64-NEXT: sete %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: iszero_f_maybe_daz:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: setzue %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: iszero_f_maybe_daz:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: setzue %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 96) ; 0x60 = "zero"
ret i1 %0
@@ -1034,12 +1035,12 @@ define i1 @not_iszero_f(float %x) {
; X64-NEXT: setne %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: not_iszero_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: setzune %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: not_iszero_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: setzune %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 927) ; ~0x60 = "~zero"
ret i1 %0
@@ -1059,12 +1060,12 @@ define i1 @not_iszero_f_daz(float %x) #0 {
; X64-NEXT: setne %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: not_iszero_f_daz:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: setzune %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: not_iszero_f_daz:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: setzune %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 927) ; ~0x60 = "~zero"
ret i1 %0
@@ -1084,12 +1085,12 @@ define i1 @not_iszero_f_maybe_daz(float %x) #1 {
; X64-NEXT: setne %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: not_iszero_f_maybe_daz:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: setzune %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: not_iszero_f_maybe_daz:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: setzune %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 927) ; ~0x60 = "~zero"
ret i1 %0
@@ -1109,12 +1110,12 @@ define i1 @issubnormal_or_zero_f(float %x) {
; X64-NEXT: sete %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: issubnormal_or_zero_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: testl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzue %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: issubnormal_or_zero_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzue %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 240) ; 0xf0 = "subnormal|zero"
ret i1 %0
@@ -1134,12 +1135,12 @@ define i1 @issubnormal_or_zero_f_daz(float %x) #0 {
; X64-NEXT: sete %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: issubnormal_or_zero_f_daz:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: testl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzue %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: issubnormal_or_zero_f_daz:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzue %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 240) ; 0xf0 = "subnormal|zero"
ret i1 %0
@@ -1159,12 +1160,12 @@ define i1 @issubnormal_or_zero_f_maybe_daz(float %x) #1 {
; X64-NEXT: sete %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: issubnormal_or_zero_f_maybe_daz:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: testl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzue %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: issubnormal_or_zero_f_maybe_daz:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzue %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 240) ; 0xf0 = "subnormal|zero"
ret i1 %0
@@ -1184,12 +1185,12 @@ define i1 @not_issubnormal_or_zero_f(float %x) {
; X64-NEXT: setne %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: not_issubnormal_or_zero_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: testl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzune %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: not_issubnormal_or_zero_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzune %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 783) ; ~0xf0 = "~(subnormal|zero)"
ret i1 %0
@@ -1209,12 +1210,12 @@ define i1 @not_issubnormal_or_zero_f_daz(float %x) #0 {
; X64-NEXT: setne %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: not_issubnormal_or_zero_f_daz:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: testl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzune %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: not_issubnormal_or_zero_f_daz:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzune %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 783) ; ~0xf0 = "~(subnormal|zero)"
ret i1 %0
@@ -1234,12 +1235,12 @@ define i1 @not_issubnormal_or_zero_f_maybe_daz(float %x) #1 {
; X64-NEXT: setne %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: not_issubnormal_or_zero_f_maybe_daz:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: testl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzune %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: not_issubnormal_or_zero_f_maybe_daz:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzune %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 783) ; ~0xf0 = "~(subnormal|zero)"
ret i1 %0
@@ -1259,12 +1260,12 @@ define i1 @is_plus_zero_f(float %x) {
; X64-NEXT: sete %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: is_plus_zero_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: testl %eax, %eax
-; X64-NDD-NEXT: setzue %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: is_plus_zero_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: testl %eax, %eax
+; X64-ZU-NEXT: setzue %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 64) ; 0x40 = "+zero"
ret i1 %0
@@ -1284,12 +1285,12 @@ define i1 @not_is_plus_zero_f(float %x) {
; X64-NEXT: setne %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: not_is_plus_zero_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: testl %eax, %eax
-; X64-NDD-NEXT: setzune %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: not_is_plus_zero_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: testl %eax, %eax
+; X64-ZU-NEXT: setzune %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 959) ; ~0x40 = ~"+zero"
ret i1 %0
@@ -1310,12 +1311,12 @@ define i1 @is_minus_zero_f(float %x) {
; X64-NEXT: seto %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: is_minus_zero_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: negl %eax
-; X64-NDD-NEXT: setzuo %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: is_minus_zero_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: negl %eax
+; X64-ZU-NEXT: setzuo %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 32) ; 0x20 = "-zero"
ret i1 %0
@@ -1336,12 +1337,12 @@ define i1 @not_is_minus_zero_f(float %x) {
; X64-NEXT: setno %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: not_is_minus_zero_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: negl %eax
-; X64-NDD-NEXT: setzuno %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: not_is_minus_zero_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: negl %eax
+; X64-ZU-NEXT: setzuno %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 991) ; ~0x20 = ~"-zero"
ret i1 %0
@@ -1364,13 +1365,13 @@ define i1 @isnan_f_strictfp(float %x) strictfp {
; X64-NEXT: setge %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: isnan_f_strictfp:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-NDD-NEXT: setzuge %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: isnan_f_strictfp:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-ZU-NEXT: setzuge %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 3) strictfp ; "nan"
ret i1 %0
@@ -1393,13 +1394,13 @@ define i1 @not_isnan_f_strictfp(float %x) strictfp {
; X64-NEXT: setl %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: not_isnan_f_strictfp:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-NDD-NEXT: setzul %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: not_isnan_f_strictfp:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-ZU-NEXT: setzul %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1020) strictfp ; ~"nan"
ret i1 %0
@@ -1422,13 +1423,13 @@ define i1 @isfinite_f_strictfp(float %x) strictfp {
; X64-NEXT: setl %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: isfinite_f_strictfp:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzul %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: isfinite_f_strictfp:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzul %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 504) strictfp ; 0x1f8 = "finite"
ret i1 %0
@@ -1451,13 +1452,13 @@ define i1 @not_isfinite_f_strictfp(float %x) strictfp {
; X64-NEXT: setge %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: not_isfinite_f_strictfp:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzuge %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: not_isfinite_f_strictfp:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzuge %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 519) strictfp ; ~0x1f8 = ~"finite"
ret i1 %0
@@ -1477,12 +1478,12 @@ define i1 @iszero_f_strictfp(float %x) strictfp {
; X64-NEXT: sete %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: iszero_f_strictfp:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: setzue %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: iszero_f_strictfp:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: setzue %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 96) strictfp ; 0x60 = "zero"
ret i1 %0
@@ -1502,12 +1503,12 @@ define i1 @not_iszero_f_strictfp(float %x) strictfp {
; X64-NEXT: setne %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: not_iszero_f_strictfp:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: setzune %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: not_iszero_f_strictfp:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: testl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: setzune %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 927) strictfp ; ~0x60 = ~"zero"
ret i1 %0
@@ -1530,11 +1531,11 @@ define i1 @isnan_d(double %x) {
; X64-NEXT: setp %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: isnan_d:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: ucomisd %xmm0, %xmm0
-; X64-NDD-NEXT: setzup %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: isnan_d:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: ucomisd %xmm0, %xmm0
+; X64-ZU-NEXT: setzup %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 3) ; "nan"
ret i1 %0
@@ -1550,15 +1551,15 @@ define i1 @isinf_d(double %x) {
; X86-NEXT: sete %al
; X86-NEXT: retl
;
-; X64-LABEL: isinf_d:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movq %xmm0, %rax
-; X64-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
-; X64-NEXT: andq %rax, %rcx
-; X64-NEXT: movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000
-; X64-NEXT: cmpq %rax, %rcx
-; X64-NEXT: sete %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: isinf_d:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movq %xmm0, %rax
+; X64-GENERIC-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; X64-GENERIC-NEXT: andq %rax, %rcx
+; X64-GENERIC-NEXT: movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000
+; X64-GENERIC-NEXT: cmpq %rax, %rcx
+; X64-GENERIC-NEXT: sete %al
+; X64-GENERIC-NEXT: retq
;
; X64-NDD-LABEL: isinf_d:
; X64-NDD: # %bb.0: # %entry
@@ -1567,8 +1568,18 @@ define i1 @isinf_d(double %x) {
; X64-NDD-NEXT: andq %rcx, %rax
; X64-NDD-NEXT: movabsq $9218868437227405312, %rcx # imm = 0x7FF0000000000000
; X64-NDD-NEXT: cmpq %rcx, %rax
-; X64-NDD-NEXT: setzue %al
+; X64-NDD-NEXT: sete %al
; X64-NDD-NEXT: retq
+;
+; X64-ZU-LABEL: isinf_d:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movq %xmm0, %rax
+; X64-ZU-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; X64-ZU-NEXT: andq %rax, %rcx
+; X64-ZU-NEXT: movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000
+; X64-ZU-NEXT: cmpq %rax, %rcx
+; X64-ZU-NEXT: setzue %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 516) ; 0x204 = "inf"
ret i1 %0
@@ -1583,15 +1594,15 @@ define i1 @isfinite_d(double %x) {
; X86-NEXT: setl %al
; X86-NEXT: retl
;
-; X64-LABEL: isfinite_d:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movq %xmm0, %rax
-; X64-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
-; X64-NEXT: andq %rax, %rcx
-; X64-NEXT: movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000
-; X64-NEXT: cmpq %rax, %rcx
-; X64-NEXT: setl %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: isfinite_d:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movq %xmm0, %rax
+; X64-GENERIC-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; X64-GENERIC-NEXT: andq %rax, %rcx
+; X64-GENERIC-NEXT: movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000
+; X64-GENERIC-NEXT: cmpq %rax, %rcx
+; X64-GENERIC-NEXT: setl %al
+; X64-GENERIC-NEXT: retq
;
; X64-NDD-LABEL: isfinite_d:
; X64-NDD: # %bb.0: # %entry
@@ -1600,8 +1611,18 @@ define i1 @isfinite_d(double %x) {
; X64-NDD-NEXT: andq %rcx, %rax
; X64-NDD-NEXT: movabsq $9218868437227405312, %rcx # imm = 0x7FF0000000000000
; X64-NDD-NEXT: cmpq %rcx, %rax
-; X64-NDD-NEXT: setzul %al
+; X64-NDD-NEXT: setl %al
; X64-NDD-NEXT: retq
+;
+; X64-ZU-LABEL: isfinite_d:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movq %xmm0, %rax
+; X64-ZU-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; X64-ZU-NEXT: andq %rax, %rcx
+; X64-ZU-NEXT: movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000
+; X64-ZU-NEXT: cmpq %rax, %rcx
+; X64-ZU-NEXT: setzul %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 504) ; 0x1f8 = "finite"
ret i1 %0
@@ -1618,17 +1639,17 @@ define i1 @isnormal_d(double %x) {
; X86-NEXT: setb %al
; X86-NEXT: retl
;
-; X64-LABEL: isnormal_d:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movq %xmm0, %rax
-; X64-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
-; X64-NEXT: andq %rax, %rcx
-; X64-NEXT: movabsq $-4503599627370496, %rax # imm = 0xFFF0000000000000
-; X64-NEXT: addq %rcx, %rax
-; X64-NEXT: shrq $53, %rax
-; X64-NEXT: cmpl $1023, %eax # imm = 0x3FF
-; X64-NEXT: setb %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: isnormal_d:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movq %xmm0, %rax
+; X64-GENERIC-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; X64-GENERIC-NEXT: andq %rax, %rcx
+; X64-GENERIC-NEXT: movabsq $-4503599627370496, %rax # imm = 0xFFF0000000000000
+; X64-GENERIC-NEXT: addq %rcx, %rax
+; X64-GENERIC-NEXT: shrq $53, %rax
+; X64-GENERIC-NEXT: cmpl $1023, %eax # imm = 0x3FF
+; X64-GENERIC-NEXT: setb %al
+; X64-GENERIC-NEXT: retq
;
; X64-NDD-LABEL: isnormal_d:
; X64-NDD: # %bb.0: # %entry
@@ -1639,8 +1660,20 @@ define i1 @isnormal_d(double %x) {
; X64-NDD-NEXT: addq %rcx, %rax
; X64-NDD-NEXT: shrq $53, %rax
; X64-NDD-NEXT: cmpl $1023, %eax # imm = 0x3FF
-; X64-NDD-NEXT: setzub %al
+; X64-NDD-NEXT: setb %al
; X64-NDD-NEXT: retq
+;
+; X64-ZU-LABEL: isnormal_d:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movq %xmm0, %rax
+; X64-ZU-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; X64-ZU-NEXT: andq %rax, %rcx
+; X64-ZU-NEXT: movabsq $-4503599627370496, %rax # imm = 0xFFF0000000000000
+; X64-ZU-NEXT: addq %rcx, %rax
+; X64-ZU-NEXT: shrq $53, %rax
+; X64-ZU-NEXT: cmpl $1023, %eax # imm = 0x3FF
+; X64-ZU-NEXT: setzub %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 264) ; 0x108 = "normal"
ret i1 %0
@@ -1659,16 +1692,16 @@ define i1 @issubnormal_d(double %x) {
; X86-NEXT: setb %al
; X86-NEXT: retl
;
-; X64-LABEL: issubnormal_d:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movq %xmm0, %rax
-; X64-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
-; X64-NEXT: andq %rax, %rcx
-; X64-NEXT: decq %rcx
-; X64-NEXT: movabsq $4503599627370495, %rax # imm = 0xFFFFFFFFFFFFF
-; X64-NEXT: cmpq %rax, %rcx
-; X64-NEXT: setb %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: issubnormal_d:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movq %xmm0, %rax
+; X64-GENERIC-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; X64-GENERIC-NEXT: andq %rax, %rcx
+; X64-GENERIC-NEXT: decq %rcx
+; X64-GENERIC-NEXT: movabsq $4503599627370495, %rax # imm = 0xFFFFFFFFFFFFF
+; X64-GENERIC-NEXT: cmpq %rax, %rcx
+; X64-GENERIC-NEXT: setb %al
+; X64-GENERIC-NEXT: retq
;
; X64-NDD-LABEL: issubnormal_d:
; X64-NDD: # %bb.0: # %entry
@@ -1678,8 +1711,19 @@ define i1 @issubnormal_d(double %x) {
; X64-NDD-NEXT: decq %rax
; X64-NDD-NEXT: movabsq $4503599627370495, %rcx # imm = 0xFFFFFFFFFFFFF
; X64-NDD-NEXT: cmpq %rcx, %rax
-; X64-NDD-NEXT: setzub %al
+; X64-NDD-NEXT: setb %al
; X64-NDD-NEXT: retq
+;
+; X64-ZU-LABEL: issubnormal_d:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movq %xmm0, %rax
+; X64-ZU-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; X64-ZU-NEXT: andq %rax, %rcx
+; X64-ZU-NEXT: decq %rcx
+; X64-ZU-NEXT: movabsq $4503599627370495, %rax # imm = 0xFFFFFFFFFFFFF
+; X64-ZU-NEXT: cmpq %rax, %rcx
+; X64-ZU-NEXT: setzub %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 144) ; 0x90 = "subnormal"
ret i1 %0
@@ -1702,13 +1746,13 @@ define i1 @iszero_d(double %x) {
; X64-NEXT: sete %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: iszero_d:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movq %xmm0, %rax
-; X64-NDD-NEXT: shlq %rax
-; X64-NDD-NEXT: testq %rax, %rax
-; X64-NDD-NEXT: setzue %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: iszero_d:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movq %xmm0, %rax
+; X64-ZU-NEXT: shlq %rax
+; X64-ZU-NEXT: testq %rax, %rax
+; X64-ZU-NEXT: setzue %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 96) ; 0x60 = "zero"
ret i1 %0
@@ -1729,19 +1773,19 @@ define i1 @issignaling_d(double %x) {
; X86-NEXT: andb %cl, %al
; X86-NEXT: retl
;
-; X64-LABEL: issignaling_d:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movq %xmm0, %rax
-; X64-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
-; X64-NEXT: andq %rax, %rcx
-; X64-NEXT: movabsq $9221120237041090560, %rax # imm = 0x7FF8000000000000
-; X64-NEXT: cmpq %rax, %rcx
-; X64-NEXT: setl %dl
-; X64-NEXT: movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000
-; X64-NEXT: cmpq %rax, %rcx
-; X64-NEXT: setg %al
-; X64-NEXT: andb %dl, %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: issignaling_d:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movq %xmm0, %rax
+; X64-GENERIC-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; X64-GENERIC-NEXT: andq %rax, %rcx
+; X64-GENERIC-NEXT: movabsq $9221120237041090560, %rax # imm = 0x7FF8000000000000
+; X64-GENERIC-NEXT: cmpq %rax, %rcx
+; X64-GENERIC-NEXT: setl %dl
+; X64-GENERIC-NEXT: movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000
+; X64-GENERIC-NEXT: cmpq %rax, %rcx
+; X64-GENERIC-NEXT: setg %al
+; X64-GENERIC-NEXT: andb %dl, %al
+; X64-GENERIC-NEXT: retq
;
; X64-NDD-LABEL: issignaling_d:
; X64-NDD: # %bb.0: # %entry
@@ -1750,12 +1794,26 @@ define i1 @issignaling_d(double %x) {
; X64-NDD-NEXT: andq %rcx, %rax
; X64-NDD-NEXT: movabsq $9221120237041090560, %rcx # imm = 0x7FF8000000000000
; X64-NDD-NEXT: cmpq %rcx, %rax
-; X64-NDD-NEXT: setzul %cl
+; X64-NDD-NEXT: setl %cl
; X64-NDD-NEXT: movabsq $9218868437227405312, %rdx # imm = 0x7FF0000000000000
; X64-NDD-NEXT: cmpq %rdx, %rax
-; X64-NDD-NEXT: setzug %al
+; X64-NDD-NEXT: setg %al
; X64-NDD-NEXT: andb %cl, %al
; X64-NDD-NEXT: retq
+;
+; X64-ZU-LABEL: issignaling_d:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movq %xmm0, %rax
+; X64-ZU-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; X64-ZU-NEXT: andq %rax, %rcx
+; X64-ZU-NEXT: movabsq $9221120237041090560, %rax # imm = 0x7FF8000000000000
+; X64-ZU-NEXT: cmpq %rax, %rcx
+; X64-ZU-NEXT: setzul %dl
+; X64-ZU-NEXT: movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000
+; X64-ZU-NEXT: cmpq %rax, %rcx
+; X64-ZU-NEXT: setzug %al
+; X64-ZU-NEXT: andb %dl, %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 1) ; "snan"
ret i1 %0
@@ -1770,15 +1828,15 @@ define i1 @isquiet_d(double %x) {
; X86-NEXT: setge %al
; X86-NEXT: retl
;
-; X64-LABEL: isquiet_d:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movq %xmm0, %rax
-; X64-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
-; X64-NEXT: andq %rax, %rcx
-; X64-NEXT: movabsq $9221120237041090559, %rax # imm = 0x7FF7FFFFFFFFFFFF
-; X64-NEXT: cmpq %rax, %rcx
-; X64-NEXT: setg %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: isquiet_d:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movq %xmm0, %rax
+; X64-GENERIC-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; X64-GENERIC-NEXT: andq %rax, %rcx
+; X64-GENERIC-NEXT: movabsq $9221120237041090559, %rax # imm = 0x7FF7FFFFFFFFFFFF
+; X64-GENERIC-NEXT: cmpq %rax, %rcx
+; X64-GENERIC-NEXT: setg %al
+; X64-GENERIC-NEXT: retq
;
; X64-NDD-LABEL: isquiet_d:
; X64-NDD: # %bb.0: # %entry
@@ -1787,8 +1845,18 @@ define i1 @isquiet_d(double %x) {
; X64-NDD-NEXT: andq %rcx, %rax
; X64-NDD-NEXT: movabsq $9221120237041090559, %rcx # imm = 0x7FF7FFFFFFFFFFFF
; X64-NDD-NEXT: cmpq %rcx, %rax
-; X64-NDD-NEXT: setzug %al
+; X64-NDD-NEXT: setg %al
; X64-NDD-NEXT: retq
+;
+; X64-ZU-LABEL: isquiet_d:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movq %xmm0, %rax
+; X64-ZU-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; X64-ZU-NEXT: andq %rax, %rcx
+; X64-ZU-NEXT: movabsq $9221120237041090559, %rax # imm = 0x7FF7FFFFFFFFFFFF
+; X64-ZU-NEXT: cmpq %rax, %rcx
+; X64-ZU-NEXT: setzug %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 2) ; "qnan"
ret i1 %0
@@ -1806,15 +1874,15 @@ define i1 @isnan_d_strictfp(double %x) strictfp {
; X86-NEXT: setl %al
; X86-NEXT: retl
;
-; X64-LABEL: isnan_d_strictfp:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movq %xmm0, %rax
-; X64-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
-; X64-NEXT: andq %rax, %rcx
-; X64-NEXT: movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000
-; X64-NEXT: cmpq %rax, %rcx
-; X64-NEXT: setg %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: isnan_d_strictfp:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movq %xmm0, %rax
+; X64-GENERIC-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; X64-GENERIC-NEXT: andq %rax, %rcx
+; X64-GENERIC-NEXT: movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000
+; X64-GENERIC-NEXT: cmpq %rax, %rcx
+; X64-GENERIC-NEXT: setg %al
+; X64-GENERIC-NEXT: retq
;
; X64-NDD-LABEL: isnan_d_strictfp:
; X64-NDD: # %bb.0: # %entry
@@ -1823,8 +1891,18 @@ define i1 @isnan_d_strictfp(double %x) strictfp {
; X64-NDD-NEXT: andq %rcx, %rax
; X64-NDD-NEXT: movabsq $9218868437227405312, %rcx # imm = 0x7FF0000000000000
; X64-NDD-NEXT: cmpq %rcx, %rax
-; X64-NDD-NEXT: setzug %al
+; X64-NDD-NEXT: setg %al
; X64-NDD-NEXT: retq
+;
+; X64-ZU-LABEL: isnan_d_strictfp:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movq %xmm0, %rax
+; X64-ZU-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
+; X64-ZU-NEXT: andq %rax, %rcx
+; X64-ZU-NEXT: movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000
+; X64-ZU-NEXT: cmpq %rax, %rcx
+; X64-ZU-NEXT: setzug %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 3) strictfp ; "nan"
ret i1 %0
@@ -1847,13 +1925,13 @@ define i1 @iszero_d_strictfp(double %x) strictfp {
; X64-NEXT: sete %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: iszero_d_strictfp:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movq %xmm0, %rax
-; X64-NDD-NEXT: shlq %rax
-; X64-NDD-NEXT: testq %rax, %rax
-; X64-NDD-NEXT: setzue %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: iszero_d_strictfp:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movq %xmm0, %rax
+; X64-ZU-NEXT: shlq %rax
+; X64-ZU-NEXT: testq %rax, %rax
+; X64-ZU-NEXT: setzue %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 96) strictfp ; 0x60 = "zero"
ret i1 %0
@@ -1878,11 +1956,11 @@ define <1 x i1> @isnan_v1f(<1 x float> %x) {
; X64-NEXT: setp %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: isnan_v1f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: ucomiss %xmm0, %xmm0
-; X64-NDD-NEXT: setzup %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: isnan_v1f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: ucomiss %xmm0, %xmm0
+; X64-ZU-NEXT: setzup %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call <1 x i1> @llvm.is.fpclass.v1f32(<1 x float> %x, i32 3) ; "nan"
ret <1 x i1> %0
@@ -1905,13 +1983,13 @@ define <1 x i1> @isnan_v1f_strictfp(<1 x float> %x) strictfp {
; X64-NEXT: setge %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: isnan_v1f_strictfp:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-NDD-NEXT: setzuge %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: isnan_v1f_strictfp:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-ZU-NEXT: setzuge %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call <1 x i1> @llvm.is.fpclass.v1f32(<1 x float> %x, i32 3) strictfp ; "nan"
ret <1 x i1> %0
@@ -1941,11 +2019,11 @@ define <2 x i1> @isnan_v2f(<2 x float> %x) {
; X64-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1,1,3]
; X64-NEXT: retq
;
-; X64-NDD-LABEL: isnan_v2f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: cmpunordps %xmm0, %xmm0
-; X64-NDD-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1,1,3]
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: isnan_v2f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: cmpunordps %xmm0, %xmm0
+; X64-ZU-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1,1,3]
+; X64-ZU-NEXT: retq
entry:
%0 = tail call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, i32 3) ; "nan"
ret <2 x i1> %0
@@ -1976,11 +2054,11 @@ define <2 x i1> @isnot_nan_v2f(<2 x float> %x) {
; X64-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1,1,3]
; X64-NEXT: retq
;
-; X64-NDD-LABEL: isnot_nan_v2f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: cmpordps %xmm0, %xmm0
-; X64-NDD-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1,1,3]
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: isnot_nan_v2f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: cmpordps %xmm0, %xmm0
+; X64-ZU-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1,1,3]
+; X64-ZU-NEXT: retq
entry:
%0 = tail call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, i32 1020) ; 0x3fc = "zero|subnormal|normal|inf"
ret <2 x i1> %0
@@ -2006,12 +2084,12 @@ define <2 x i1> @isnan_v2f_strictfp(<2 x float> %x) strictfp {
; X64-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
;
-; X64-NDD-LABEL: isnan_v2f_strictfp:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1,1,3]
-; X64-NDD-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; X64-NDD-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: isnan_v2f_strictfp:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1,1,3]
+; X64-ZU-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-ZU-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-ZU-NEXT: retq
entry:
%0 = tail call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, i32 3) strictfp ; "nan"
ret <2 x i1> %0
@@ -2060,10 +2138,10 @@ define <4 x i1> @isnan_v4f(<4 x float> %x) {
; X64-NEXT: cmpunordps %xmm0, %xmm0
; X64-NEXT: retq
;
-; X64-NDD-LABEL: isnan_v4f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: cmpunordps %xmm0, %xmm0
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: isnan_v4f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: cmpunordps %xmm0, %xmm0
+; X64-ZU-NEXT: retq
entry:
%0 = tail call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> %x, i32 3) ; "nan"
ret <4 x i1> %0
@@ -2109,11 +2187,11 @@ define <4 x i1> @isnan_v4f_strictfp(<4 x float> %x) strictfp {
; X64-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
;
-; X64-NDD-LABEL: isnan_v4f_strictfp:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; X64-NDD-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: isnan_v4f_strictfp:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-ZU-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-ZU-NEXT: retq
entry:
%0 = tail call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> %x, i32 3) strictfp ; "nan"
ret <4 x i1> %0
@@ -2130,10 +2208,10 @@ define i1 @isnone_f(float %x) {
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: retq
;
-; X64-NDD-LABEL: isnone_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: xorl %eax, %eax
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: isnone_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: xorl %eax, %eax
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 0)
ret i1 %0
@@ -2150,10 +2228,10 @@ define i1 @isany_f(float %x) {
; X64-NEXT: movb $1, %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: isany_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movb $1, %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: isany_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movb $1, %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1023)
ret i1 %0
@@ -2179,12 +2257,12 @@ define i1 @iszero_or_nan_f(float %x) {
; X64-NEXT: sete %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: iszero_or_nan_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: xorps %xmm1, %xmm1
-; X64-NDD-NEXT: ucomiss %xmm1, %xmm0
-; X64-NDD-NEXT: setzue %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: iszero_or_nan_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: xorps %xmm1, %xmm1
+; X64-ZU-NEXT: ucomiss %xmm1, %xmm0
+; X64-ZU-NEXT: setzue %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 99) ; 0x60|0x3 = "zero|nan"
ret i1 %0
@@ -2213,16 +2291,16 @@ define i1 @iszero_or_nan_f_daz(float %x) #0 {
; X64-NEXT: orb %cl, %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: iszero_or_nan_f_daz:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-NDD-NEXT: setzuge %cl
-; X64-NDD-NEXT: testl %eax, %eax
-; X64-NDD-NEXT: setzue %al
-; X64-NDD-NEXT: orb %cl, %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: iszero_or_nan_f_daz:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-ZU-NEXT: setzuge %cl
+; X64-ZU-NEXT: testl %eax, %eax
+; X64-ZU-NEXT: setzue %al
+; X64-ZU-NEXT: orb %cl, %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 99) ; 0x60|0x3 = "zero|nan"
ret i1 %0
@@ -2251,16 +2329,16 @@ define i1 @iszero_or_nan_f_maybe_daz(float %x) #1 {
; X64-NEXT: orb %cl, %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: iszero_or_nan_f_maybe_daz:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-NDD-NEXT: setzuge %cl
-; X64-NDD-NEXT: testl %eax, %eax
-; X64-NDD-NEXT: setzue %al
-; X64-NDD-NEXT: orb %cl, %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: iszero_or_nan_f_maybe_daz:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-ZU-NEXT: setzuge %cl
+; X64-ZU-NEXT: testl %eax, %eax
+; X64-ZU-NEXT: setzue %al
+; X64-ZU-NEXT: orb %cl, %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 99) ; 0x60|0x3 = "zero|nan"
ret i1 %0
@@ -2285,12 +2363,12 @@ define i1 @not_iszero_or_nan_f(float %x) {
; X64-NEXT: setne %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: not_iszero_or_nan_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: xorps %xmm1, %xmm1
-; X64-NDD-NEXT: ucomiss %xmm1, %xmm0
-; X64-NDD-NEXT: setzune %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: not_iszero_or_nan_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: xorps %xmm1, %xmm1
+; X64-ZU-NEXT: ucomiss %xmm1, %xmm0
+; X64-ZU-NEXT: setzune %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 924) ; ~0x60 = "~(zero|nan)"
ret i1 %0
@@ -2319,16 +2397,16 @@ define i1 @not_iszero_or_nan_f_daz(float %x) #0 {
; X64-NEXT: andb %cl, %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: not_iszero_or_nan_f_daz:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-NDD-NEXT: setzul %cl
-; X64-NDD-NEXT: testl %eax, %eax
-; X64-NDD-NEXT: setzune %al
-; X64-NDD-NEXT: andb %cl, %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: not_iszero_or_nan_f_daz:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-ZU-NEXT: setzul %cl
+; X64-ZU-NEXT: testl %eax, %eax
+; X64-ZU-NEXT: setzune %al
+; X64-ZU-NEXT: andb %cl, %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 924) ; ~(0x60|0x3) = "~(zero|nan)"
ret i1 %0
@@ -2357,16 +2435,16 @@ define i1 @not_iszero_or_nan_f_maybe_daz(float %x) #1 {
; X64-NEXT: andb %cl, %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: not_iszero_or_nan_f_maybe_daz:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-NDD-NEXT: setzul %cl
-; X64-NDD-NEXT: testl %eax, %eax
-; X64-NDD-NEXT: setzune %al
-; X64-NDD-NEXT: andb %cl, %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: not_iszero_or_nan_f_maybe_daz:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-ZU-NEXT: setzul %cl
+; X64-ZU-NEXT: testl %eax, %eax
+; X64-ZU-NEXT: setzune %al
+; X64-ZU-NEXT: andb %cl, %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 924) ; ~(0x60|0x3) = "~(zero|nan)"
ret i1 %0
@@ -2395,16 +2473,16 @@ define i1 @iszero_or_qnan_f(float %x) {
; X64-NEXT: orb %cl, %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: iszero_or_qnan_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NDD-NEXT: setzuge %cl
-; X64-NDD-NEXT: testl %eax, %eax
-; X64-NDD-NEXT: setzue %al
-; X64-NDD-NEXT: orb %cl, %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: iszero_or_qnan_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-ZU-NEXT: setzuge %cl
+; X64-ZU-NEXT: testl %eax, %eax
+; X64-ZU-NEXT: setzue %al
+; X64-ZU-NEXT: orb %cl, %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 98) ; 0x60|0x2 = "zero|qnan"
ret i1 %0
@@ -2425,33 +2503,47 @@ define i1 @iszero_or_snan_f(float %x) {
; X86-NEXT: orb %dl, %al
; X86-NEXT: retl
;
-; X64-LABEL: iszero_or_snan_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NEXT: setl %cl
-; X64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-NEXT: setge %dl
-; X64-NEXT: andb %cl, %dl
-; X64-NEXT: testl %eax, %eax
-; X64-NEXT: sete %al
-; X64-NEXT: orb %dl, %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: iszero_or_snan_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-GENERIC-NEXT: setl %cl
+; X64-GENERIC-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-GENERIC-NEXT: setge %dl
+; X64-GENERIC-NEXT: andb %cl, %dl
+; X64-GENERIC-NEXT: testl %eax, %eax
+; X64-GENERIC-NEXT: sete %al
+; X64-GENERIC-NEXT: orb %dl, %al
+; X64-GENERIC-NEXT: retq
;
; X64-NDD-LABEL: iszero_or_snan_f:
; X64-NDD: # %bb.0: # %entry
; X64-NDD-NEXT: movd %xmm0, %eax
; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
; X64-NDD-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NDD-NEXT: setzul %cl
+; X64-NDD-NEXT: setl %cl
; X64-NDD-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-NDD-NEXT: setzuge %dl
+; X64-NDD-NEXT: setge %dl
; X64-NDD-NEXT: andb %dl, %cl
; X64-NDD-NEXT: testl %eax, %eax
-; X64-NDD-NEXT: setzue %al
+; X64-NDD-NEXT: sete %al
; X64-NDD-NEXT: orb %cl, %al
; X64-NDD-NEXT: retq
+;
+; X64-ZU-LABEL: iszero_or_snan_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-ZU-NEXT: setzul %cl
+; X64-ZU-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-ZU-NEXT: setzuge %dl
+; X64-ZU-NEXT: andb %cl, %dl
+; X64-ZU-NEXT: testl %eax, %eax
+; X64-ZU-NEXT: setzue %al
+; X64-ZU-NEXT: orb %dl, %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 97) ; 0x60|0x1 = "zero|snan"
ret i1 %0
@@ -2485,49 +2577,71 @@ define i1 @not_iszero_or_qnan_f(float %x) {
; X86-NEXT: .cfi_def_cfa_offset 4
; X86-NEXT: retl
;
-; X64-LABEL: not_iszero_or_qnan_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NEXT: setl %cl
-; X64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-NEXT: setge %dl
-; X64-NEXT: andb %cl, %dl
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: sete %cl
-; X64-NEXT: leal -1(%rax), %esi
-; X64-NEXT: cmpl $8388607, %esi # imm = 0x7FFFFF
-; X64-NEXT: setb %sil
-; X64-NEXT: orb %cl, %sil
-; X64-NEXT: addl $-8388608, %eax # imm = 0xFF800000
-; X64-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; X64-NEXT: setb %al
-; X64-NEXT: orb %dl, %al
-; X64-NEXT: orb %sil, %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_iszero_or_qnan_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-GENERIC-NEXT: setl %cl
+; X64-GENERIC-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-GENERIC-NEXT: setge %dl
+; X64-GENERIC-NEXT: andb %cl, %dl
+; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: sete %cl
+; X64-GENERIC-NEXT: leal -1(%rax), %esi
+; X64-GENERIC-NEXT: cmpl $8388607, %esi # imm = 0x7FFFFF
+; X64-GENERIC-NEXT: setb %sil
+; X64-GENERIC-NEXT: orb %cl, %sil
+; X64-GENERIC-NEXT: addl $-8388608, %eax # imm = 0xFF800000
+; X64-GENERIC-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
+; X64-GENERIC-NEXT: setb %al
+; X64-GENERIC-NEXT: orb %dl, %al
+; X64-GENERIC-NEXT: orb %sil, %al
+; X64-GENERIC-NEXT: retq
;
; X64-NDD-LABEL: not_iszero_or_qnan_f:
; X64-NDD: # %bb.0: # %entry
; X64-NDD-NEXT: movd %xmm0, %eax
; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
; X64-NDD-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NDD-NEXT: setzul %cl
+; X64-NDD-NEXT: setl %cl
; X64-NDD-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-NDD-NEXT: setzuge %dl
+; X64-NDD-NEXT: setge %dl
; X64-NDD-NEXT: andb %dl, %cl
; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzue %dl
+; X64-NDD-NEXT: sete %dl
; X64-NDD-NEXT: decl %eax, %esi
; X64-NDD-NEXT: cmpl $8388607, %esi # imm = 0x7FFFFF
-; X64-NDD-NEXT: setzub %sil
+; X64-NDD-NEXT: setb %sil
; X64-NDD-NEXT: orb %sil, %dl
; X64-NDD-NEXT: addl $-8388608, %eax # imm = 0xFF800000
; X64-NDD-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; X64-NDD-NEXT: setzub %al
+; X64-NDD-NEXT: setb %al
; X64-NDD-NEXT: orb %cl, %al
; X64-NDD-NEXT: orb %dl, %al
; X64-NDD-NEXT: retq
+;
+; X64-ZU-LABEL: not_iszero_or_qnan_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-ZU-NEXT: setzul %cl
+; X64-ZU-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-ZU-NEXT: setzuge %dl
+; X64-ZU-NEXT: andb %cl, %dl
+; X64-ZU-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzue %cl
+; X64-ZU-NEXT: leal -1(%rax), %esi
+; X64-ZU-NEXT: cmpl $8388607, %esi # imm = 0x7FFFFF
+; X64-ZU-NEXT: setzub %sil
+; X64-ZU-NEXT: orb %cl, %sil
+; X64-ZU-NEXT: addl $-8388608, %eax # imm = 0xFF800000
+; X64-ZU-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
+; X64-ZU-NEXT: setzub %al
+; X64-ZU-NEXT: orb %dl, %al
+; X64-ZU-NEXT: orb %sil, %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 925) ; ~(0x60|0x2) = "~(zero|qnan)"
ret i1 %0
@@ -2553,43 +2667,62 @@ define i1 @not_iszero_or_snan_f(float %x) {
; X86-NEXT: orb %ch, %al
; X86-NEXT: retl
;
-; X64-LABEL: not_iszero_or_snan_f:
-; X64: # %bb.0: # %entry
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: sete %cl
-; X64-NEXT: leal -1(%rax), %edx
-; X64-NEXT: cmpl $8388607, %edx # imm = 0x7FFFFF
-; X64-NEXT: setb %dl
-; X64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NEXT: setge %sil
-; X64-NEXT: orb %cl, %sil
-; X64-NEXT: orb %dl, %sil
-; X64-NEXT: addl $-8388608, %eax # imm = 0xFF800000
-; X64-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; X64-NEXT: setb %al
-; X64-NEXT: orb %sil, %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_iszero_or_snan_f:
+; X64-GENERIC: # %bb.0: # %entry
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: sete %cl
+; X64-GENERIC-NEXT: leal -1(%rax), %edx
+; X64-GENERIC-NEXT: cmpl $8388607, %edx # imm = 0x7FFFFF
+; X64-GENERIC-NEXT: setb %dl
+; X64-GENERIC-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-GENERIC-NEXT: setge %sil
+; X64-GENERIC-NEXT: orb %cl, %sil
+; X64-GENERIC-NEXT: orb %dl, %sil
+; X64-GENERIC-NEXT: addl $-8388608, %eax # imm = 0xFF800000
+; X64-GENERIC-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
+; X64-GENERIC-NEXT: setb %al
+; X64-GENERIC-NEXT: orb %sil, %al
+; X64-GENERIC-NEXT: retq
;
; X64-NDD-LABEL: not_iszero_or_snan_f:
; X64-NDD: # %bb.0: # %entry
; X64-NDD-NEXT: movd %xmm0, %eax
; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzue %cl
+; X64-NDD-NEXT: sete %cl
; X64-NDD-NEXT: decl %eax, %edx
; X64-NDD-NEXT: cmpl $8388607, %edx # imm = 0x7FFFFF
-; X64-NDD-NEXT: setzub %dl
+; X64-NDD-NEXT: setb %dl
; X64-NDD-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NDD-NEXT: setzuge %sil
+; X64-NDD-NEXT: setge %sil
; X64-NDD-NEXT: orb %sil, %cl
; X64-NDD-NEXT: orb %dl, %cl
; X64-NDD-NEXT: addl $-8388608, %eax # imm = 0xFF800000
; X64-NDD-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; X64-NDD-NEXT: setzub %al
+; X64-NDD-NEXT: setb %al
; X64-NDD-NEXT: orb %cl, %al
; X64-NDD-NEXT: retq
+;
+; X64-ZU-LABEL: not_iszero_or_snan_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzue %cl
+; X64-ZU-NEXT: leal -1(%rax), %edx
+; X64-ZU-NEXT: cmpl $8388607, %edx # imm = 0x7FFFFF
+; X64-ZU-NEXT: setzub %dl
+; X64-ZU-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-ZU-NEXT: setzuge %sil
+; X64-ZU-NEXT: orb %cl, %sil
+; X64-ZU-NEXT: orb %dl, %sil
+; X64-ZU-NEXT: addl $-8388608, %eax # imm = 0xFF800000
+; X64-ZU-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
+; X64-ZU-NEXT: setzub %al
+; X64-ZU-NEXT: orb %sil, %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 926) ; ~(0x60|0x1) = "~(zero|snan)"
ret i1 %0
@@ -2612,13 +2745,13 @@ define i1 @isinf_or_nan_f(float %x) {
; X64-NEXT: setge %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: isinf_or_nan_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzuge %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: isinf_or_nan_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzuge %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 519) ; 0x204|0x3 = "inf|nan"
ret i1 %0
@@ -2641,13 +2774,13 @@ define i1 @not_isinf_or_nan_f(float %x) {
; X64-NEXT: setl %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: not_isinf_or_nan_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzul %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: not_isinf_or_nan_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzul %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 504) ; ~(0x204|0x3) = "~(inf|nan)"
ret i1 %0
@@ -2670,13 +2803,13 @@ define i1 @isfinite_or_nan_f(float %x) {
; X64-NEXT: setne %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: isfinite_or_nan_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzune %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: isfinite_or_nan_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzune %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 507) ; 0x1f8|0x3 = "finite|nan"
ret i1 %0
@@ -2699,13 +2832,13 @@ define i1 @not_isfinite_or_nan_f(float %x) {
; X64-NEXT: sete %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: not_isfinite_or_nan_f:
-; X64-NDD: # %bb.0: # %entry
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzue %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: not_isfinite_or_nan_f:
+; X64-ZU: # %bb.0: # %entry
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzue %al
+; X64-ZU-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 516) ; ~(0x1f8|0x3) = "~(finite|nan)"
ret i1 %0
@@ -2729,11 +2862,11 @@ define i1 @is_plus_inf_or_nan_f(float %x) {
; X64-NEXT: sete %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: is_plus_inf_or_nan_f:
-; X64-NDD: # %bb.0:
-; X64-NDD-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; X64-NDD-NEXT: setzue %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: is_plus_inf_or_nan_f:
+; X64-ZU: # %bb.0:
+; X64-ZU-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-ZU-NEXT: setzue %al
+; X64-ZU-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 515) ; 0x200|0x3 = "+inf|nan"
ret i1 %class
}
@@ -2756,11 +2889,11 @@ define i1 @is_minus_inf_or_nan_f(float %x) {
; X64-NEXT: sete %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: is_minus_inf_or_nan_f:
-; X64-NDD: # %bb.0:
-; X64-NDD-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; X64-NDD-NEXT: setzue %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: is_minus_inf_or_nan_f:
+; X64-ZU: # %bb.0:
+; X64-ZU-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-ZU-NEXT: setzue %al
+; X64-ZU-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 7) ; "-inf|nan"
ret i1 %class
}
@@ -2783,11 +2916,11 @@ define i1 @not_is_plus_inf_or_nan_f(float %x) {
; X64-NEXT: setne %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: not_is_plus_inf_or_nan_f:
-; X64-NDD: # %bb.0:
-; X64-NDD-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; X64-NDD-NEXT: setzune %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: not_is_plus_inf_or_nan_f:
+; X64-ZU: # %bb.0:
+; X64-ZU-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-ZU-NEXT: setzune %al
+; X64-ZU-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 508) ; ~(0x200|0x3) = "~(+inf|nan)"
ret i1 %class
}
@@ -2810,11 +2943,11 @@ define i1 @not_is_minus_inf_or_nan_f(float %x) {
; X64-NEXT: setne %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: not_is_minus_inf_or_nan_f:
-; X64-NDD: # %bb.0:
-; X64-NDD-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; X64-NDD-NEXT: setzune %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: not_is_minus_inf_or_nan_f:
+; X64-ZU: # %bb.0:
+; X64-ZU-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-ZU-NEXT: setzune %al
+; X64-ZU-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1016) ; "~(-inf|nan)"
ret i1 %class
}
@@ -2835,34 +2968,49 @@ define i1 @is_plus_inf_or_snan_f(float %x) {
; X86-NEXT: orb %cl, %al
; X86-NEXT: retl
;
-; X64-LABEL: is_plus_inf_or_snan_f:
-; X64: # %bb.0:
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: movl %eax, %ecx
-; X64-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
-; X64-NEXT: setl %dl
-; X64-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
-; X64-NEXT: setge %cl
-; X64-NEXT: andb %dl, %cl
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: sete %al
-; X64-NEXT: orb %cl, %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: is_plus_inf_or_snan_f:
+; X64-GENERIC: # %bb.0:
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: movl %eax, %ecx
+; X64-GENERIC-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
+; X64-GENERIC-NEXT: setl %dl
+; X64-GENERIC-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
+; X64-GENERIC-NEXT: setge %cl
+; X64-GENERIC-NEXT: andb %dl, %cl
+; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: sete %al
+; X64-GENERIC-NEXT: orb %cl, %al
+; X64-GENERIC-NEXT: retq
;
; X64-NDD-LABEL: is_plus_inf_or_snan_f:
; X64-NDD: # %bb.0:
; X64-NDD-NEXT: movd %xmm0, %eax
; X64-NDD-NEXT: andl $2147483647, %eax, %ecx # imm = 0x7FFFFFFF
; X64-NDD-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
-; X64-NDD-NEXT: setzul %dl
+; X64-NDD-NEXT: setl %dl
; X64-NDD-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
-; X64-NDD-NEXT: setzuge %cl
+; X64-NDD-NEXT: setge %cl
; X64-NDD-NEXT: andb %dl, %cl
; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzue %al
+; X64-NDD-NEXT: sete %al
; X64-NDD-NEXT: orb %cl, %al
; X64-NDD-NEXT: retq
+;
+; X64-ZU-LABEL: is_plus_inf_or_snan_f:
+; X64-ZU: # %bb.0:
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: movl %eax, %ecx
+; X64-ZU-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
+; X64-ZU-NEXT: setzul %dl
+; X64-ZU-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
+; X64-ZU-NEXT: setzuge %cl
+; X64-ZU-NEXT: andb %dl, %cl
+; X64-ZU-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzue %al
+; X64-ZU-NEXT: orb %cl, %al
+; X64-ZU-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 513) ; 0x200|0x1 = "+inf|snan"
ret i1 %class
}
@@ -2890,16 +3038,16 @@ define i1 @is_plus_inf_or_qnan_f(float %x) {
; X64-NEXT: orb %cl, %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: is_plus_inf_or_qnan_f:
-; X64-NDD: # %bb.0:
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzue %cl
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NDD-NEXT: setzuge %al
-; X64-NDD-NEXT: orb %cl, %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: is_plus_inf_or_qnan_f:
+; X64-ZU: # %bb.0:
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzue %cl
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-ZU-NEXT: setzuge %al
+; X64-ZU-NEXT: orb %cl, %al
+; X64-ZU-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 514) ; 0x200|0x1 = "+inf|qnan"
ret i1 %class
}
@@ -2919,33 +3067,47 @@ define i1 @not_is_plus_inf_or_snan_f(float %x) {
; X86-NEXT: orb %dl, %al
; X86-NEXT: retl
;
-; X64-LABEL: not_is_plus_inf_or_snan_f:
-; X64: # %bb.0:
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
-; X64-NEXT: sete %cl
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: setl %dl
-; X64-NEXT: orb %cl, %dl
-; X64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NEXT: setge %al
-; X64-NEXT: orb %dl, %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_is_plus_inf_or_snan_f:
+; X64-GENERIC: # %bb.0:
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
+; X64-GENERIC-NEXT: sete %cl
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: setl %dl
+; X64-GENERIC-NEXT: orb %cl, %dl
+; X64-GENERIC-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-GENERIC-NEXT: setge %al
+; X64-GENERIC-NEXT: orb %dl, %al
+; X64-GENERIC-NEXT: retq
;
; X64-NDD-LABEL: not_is_plus_inf_or_snan_f:
; X64-NDD: # %bb.0:
; X64-NDD-NEXT: movd %xmm0, %eax
; X64-NDD-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
-; X64-NDD-NEXT: setzue %cl
+; X64-NDD-NEXT: sete %cl
; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzul %dl
+; X64-NDD-NEXT: setl %dl
; X64-NDD-NEXT: orb %dl, %cl
; X64-NDD-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NDD-NEXT: setzuge %al
+; X64-NDD-NEXT: setge %al
; X64-NDD-NEXT: orb %cl, %al
; X64-NDD-NEXT: retq
+;
+; X64-ZU-LABEL: not_is_plus_inf_or_snan_f:
+; X64-ZU: # %bb.0:
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
+; X64-ZU-NEXT: setzue %cl
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzul %dl
+; X64-ZU-NEXT: orb %cl, %dl
+; X64-ZU-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-ZU-NEXT: setzuge %al
+; X64-ZU-NEXT: orb %dl, %al
+; X64-ZU-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 510) ; ~(+inf|snan)
ret i1 %class
}
@@ -2969,40 +3131,58 @@ define i1 @not_is_plus_inf_or_qnan_f(float %x) {
; X86-NEXT: orb %dh, %al
; X86-NEXT: retl
;
-; X64-LABEL: not_is_plus_inf_or_qnan_f:
-; X64: # %bb.0:
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: movl %eax, %ecx
-; X64-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
-; X64-NEXT: setl %dl
-; X64-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
-; X64-NEXT: setge %sil
-; X64-NEXT: andb %dl, %sil
-; X64-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
-; X64-NEXT: sete %dl
-; X64-NEXT: cmpl $2139095040, %ecx # imm = 0x7F800000
-; X64-NEXT: setl %al
-; X64-NEXT: orb %dl, %al
-; X64-NEXT: orb %sil, %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_is_plus_inf_or_qnan_f:
+; X64-GENERIC: # %bb.0:
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: movl %eax, %ecx
+; X64-GENERIC-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
+; X64-GENERIC-NEXT: setl %dl
+; X64-GENERIC-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
+; X64-GENERIC-NEXT: setge %sil
+; X64-GENERIC-NEXT: andb %dl, %sil
+; X64-GENERIC-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
+; X64-GENERIC-NEXT: sete %dl
+; X64-GENERIC-NEXT: cmpl $2139095040, %ecx # imm = 0x7F800000
+; X64-GENERIC-NEXT: setl %al
+; X64-GENERIC-NEXT: orb %dl, %al
+; X64-GENERIC-NEXT: orb %sil, %al
+; X64-GENERIC-NEXT: retq
;
; X64-NDD-LABEL: not_is_plus_inf_or_qnan_f:
; X64-NDD: # %bb.0:
; X64-NDD-NEXT: movd %xmm0, %eax
; X64-NDD-NEXT: andl $2147483647, %eax, %ecx # imm = 0x7FFFFFFF
; X64-NDD-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
-; X64-NDD-NEXT: setzul %dl
+; X64-NDD-NEXT: setl %dl
; X64-NDD-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
-; X64-NDD-NEXT: setzuge %sil
+; X64-NDD-NEXT: setge %sil
; X64-NDD-NEXT: andb %sil, %dl
; X64-NDD-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
-; X64-NDD-NEXT: setzue %al
+; X64-NDD-NEXT: sete %al
; X64-NDD-NEXT: cmpl $2139095040, %ecx # imm = 0x7F800000
-; X64-NDD-NEXT: setzul %cl
+; X64-NDD-NEXT: setl %cl
; X64-NDD-NEXT: orb %cl, %al
; X64-NDD-NEXT: orb %dl, %al
; X64-NDD-NEXT: retq
+;
+; X64-ZU-LABEL: not_is_plus_inf_or_qnan_f:
+; X64-ZU: # %bb.0:
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: movl %eax, %ecx
+; X64-ZU-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
+; X64-ZU-NEXT: setzul %dl
+; X64-ZU-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
+; X64-ZU-NEXT: setzuge %sil
+; X64-ZU-NEXT: andb %dl, %sil
+; X64-ZU-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
+; X64-ZU-NEXT: setzue %dl
+; X64-ZU-NEXT: cmpl $2139095040, %ecx # imm = 0x7F800000
+; X64-ZU-NEXT: setzul %al
+; X64-ZU-NEXT: orb %dl, %al
+; X64-ZU-NEXT: orb %sil, %al
+; X64-ZU-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 509) ; ~(+inf|qnan)
ret i1 %class
}
@@ -3023,34 +3203,49 @@ define i1 @is_minus_inf_or_snan_f(float %x) {
; X86-NEXT: orb %cl, %al
; X86-NEXT: retl
;
-; X64-LABEL: is_minus_inf_or_snan_f:
-; X64: # %bb.0:
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: movl %eax, %ecx
-; X64-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
-; X64-NEXT: setl %dl
-; X64-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
-; X64-NEXT: setge %cl
-; X64-NEXT: andb %dl, %cl
-; X64-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
-; X64-NEXT: sete %al
-; X64-NEXT: orb %cl, %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: is_minus_inf_or_snan_f:
+; X64-GENERIC: # %bb.0:
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: movl %eax, %ecx
+; X64-GENERIC-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
+; X64-GENERIC-NEXT: setl %dl
+; X64-GENERIC-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
+; X64-GENERIC-NEXT: setge %cl
+; X64-GENERIC-NEXT: andb %dl, %cl
+; X64-GENERIC-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
+; X64-GENERIC-NEXT: sete %al
+; X64-GENERIC-NEXT: orb %cl, %al
+; X64-GENERIC-NEXT: retq
;
; X64-NDD-LABEL: is_minus_inf_or_snan_f:
; X64-NDD: # %bb.0:
; X64-NDD-NEXT: movd %xmm0, %eax
; X64-NDD-NEXT: andl $2147483647, %eax, %ecx # imm = 0x7FFFFFFF
; X64-NDD-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
-; X64-NDD-NEXT: setzul %dl
+; X64-NDD-NEXT: setl %dl
; X64-NDD-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
-; X64-NDD-NEXT: setzuge %cl
+; X64-NDD-NEXT: setge %cl
; X64-NDD-NEXT: andb %dl, %cl
; X64-NDD-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
-; X64-NDD-NEXT: setzue %al
+; X64-NDD-NEXT: sete %al
; X64-NDD-NEXT: orb %cl, %al
; X64-NDD-NEXT: retq
+;
+; X64-ZU-LABEL: is_minus_inf_or_snan_f:
+; X64-ZU: # %bb.0:
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: movl %eax, %ecx
+; X64-ZU-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
+; X64-ZU-NEXT: setzul %dl
+; X64-ZU-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
+; X64-ZU-NEXT: setzuge %cl
+; X64-ZU-NEXT: andb %dl, %cl
+; X64-ZU-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
+; X64-ZU-NEXT: setzue %al
+; X64-ZU-NEXT: orb %cl, %al
+; X64-ZU-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 5) ; "-inf|snan"
ret i1 %class
}
@@ -3078,16 +3273,16 @@ define i1 @is_minus_inf_or_qnan_f(float %x) {
; X64-NEXT: orb %cl, %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: is_minus_inf_or_qnan_f:
-; X64-NDD: # %bb.0:
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
-; X64-NDD-NEXT: setzue %cl
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NDD-NEXT: setzuge %al
-; X64-NDD-NEXT: orb %cl, %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: is_minus_inf_or_qnan_f:
+; X64-ZU: # %bb.0:
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000
+; X64-ZU-NEXT: setzue %cl
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-ZU-NEXT: setzuge %al
+; X64-ZU-NEXT: orb %cl, %al
+; X64-ZU-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 6) ; "-inf|qnan"
ret i1 %class
}
@@ -3107,33 +3302,47 @@ define i1 @not_is_minus_inf_or_snan_f(float %x) {
; X86-NEXT: orb %dl, %al
; X86-NEXT: retl
;
-; X64-LABEL: not_is_minus_inf_or_snan_f:
-; X64: # %bb.0:
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: sete %cl
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: setl %dl
-; X64-NEXT: orb %cl, %dl
-; X64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NEXT: setge %al
-; X64-NEXT: orb %dl, %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_is_minus_inf_or_snan_f:
+; X64-GENERIC: # %bb.0:
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: sete %cl
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: setl %dl
+; X64-GENERIC-NEXT: orb %cl, %dl
+; X64-GENERIC-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-GENERIC-NEXT: setge %al
+; X64-GENERIC-NEXT: orb %dl, %al
+; X64-GENERIC-NEXT: retq
;
; X64-NDD-LABEL: not_is_minus_inf_or_snan_f:
; X64-NDD: # %bb.0:
; X64-NDD-NEXT: movd %xmm0, %eax
; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzue %cl
+; X64-NDD-NEXT: sete %cl
; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzul %dl
+; X64-NDD-NEXT: setl %dl
; X64-NDD-NEXT: orb %dl, %cl
; X64-NDD-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NDD-NEXT: setzuge %al
+; X64-NDD-NEXT: setge %al
; X64-NDD-NEXT: orb %cl, %al
; X64-NDD-NEXT: retq
+;
+; X64-ZU-LABEL: not_is_minus_inf_or_snan_f:
+; X64-ZU: # %bb.0:
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzue %cl
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzul %dl
+; X64-ZU-NEXT: orb %cl, %dl
+; X64-ZU-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-ZU-NEXT: setzuge %al
+; X64-ZU-NEXT: orb %dl, %al
+; X64-ZU-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1018) ; "~(-inf|snan)"
ret i1 %class
}
@@ -3157,40 +3366,58 @@ define i1 @not_is_minus_inf_or_qnan_f(float %x) {
; X86-NEXT: orb %dh, %al
; X86-NEXT: retl
;
-; X64-LABEL: not_is_minus_inf_or_qnan_f:
-; X64: # %bb.0:
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: movl %eax, %ecx
-; X64-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
-; X64-NEXT: setl %dl
-; X64-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
-; X64-NEXT: setge %sil
-; X64-NEXT: andb %dl, %sil
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: sete %dl
-; X64-NEXT: cmpl $2139095040, %ecx # imm = 0x7F800000
-; X64-NEXT: setl %al
-; X64-NEXT: orb %dl, %al
-; X64-NEXT: orb %sil, %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_is_minus_inf_or_qnan_f:
+; X64-GENERIC: # %bb.0:
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: movl %eax, %ecx
+; X64-GENERIC-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
+; X64-GENERIC-NEXT: setl %dl
+; X64-GENERIC-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
+; X64-GENERIC-NEXT: setge %sil
+; X64-GENERIC-NEXT: andb %dl, %sil
+; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: sete %dl
+; X64-GENERIC-NEXT: cmpl $2139095040, %ecx # imm = 0x7F800000
+; X64-GENERIC-NEXT: setl %al
+; X64-GENERIC-NEXT: orb %dl, %al
+; X64-GENERIC-NEXT: orb %sil, %al
+; X64-GENERIC-NEXT: retq
;
; X64-NDD-LABEL: not_is_minus_inf_or_qnan_f:
; X64-NDD: # %bb.0:
; X64-NDD-NEXT: movd %xmm0, %eax
; X64-NDD-NEXT: andl $2147483647, %eax, %ecx # imm = 0x7FFFFFFF
; X64-NDD-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
-; X64-NDD-NEXT: setzul %dl
+; X64-NDD-NEXT: setl %dl
; X64-NDD-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
-; X64-NDD-NEXT: setzuge %sil
+; X64-NDD-NEXT: setge %sil
; X64-NDD-NEXT: andb %sil, %dl
; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzue %al
+; X64-NDD-NEXT: sete %al
; X64-NDD-NEXT: cmpl $2139095040, %ecx # imm = 0x7F800000
-; X64-NDD-NEXT: setzul %cl
+; X64-NDD-NEXT: setl %cl
; X64-NDD-NEXT: orb %cl, %al
; X64-NDD-NEXT: orb %dl, %al
; X64-NDD-NEXT: retq
+;
+; X64-ZU-LABEL: not_is_minus_inf_or_qnan_f:
+; X64-ZU: # %bb.0:
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: movl %eax, %ecx
+; X64-ZU-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
+; X64-ZU-NEXT: setzul %dl
+; X64-ZU-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
+; X64-ZU-NEXT: setzuge %sil
+; X64-ZU-NEXT: andb %dl, %sil
+; X64-ZU-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzue %dl
+; X64-ZU-NEXT: cmpl $2139095040, %ecx # imm = 0x7F800000
+; X64-ZU-NEXT: setzul %al
+; X64-ZU-NEXT: orb %dl, %al
+; X64-ZU-NEXT: orb %sil, %al
+; X64-ZU-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1017) ; "-inf|qnan"
ret i1 %class
}
@@ -3220,17 +3447,17 @@ define i1 @issubnormal_or_nan_f(float %x) {
; X64-NEXT: orb %cl, %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: issubnormal_or_nan_f:
-; X64-NDD: # %bb.0:
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-NDD-NEXT: setzuge %cl
-; X64-NDD-NEXT: decl %eax
-; X64-NDD-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
-; X64-NDD-NEXT: setzub %al
-; X64-NDD-NEXT: orb %cl, %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: issubnormal_or_nan_f:
+; X64-ZU: # %bb.0:
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-ZU-NEXT: setzuge %cl
+; X64-ZU-NEXT: decl %eax
+; X64-ZU-NEXT: cmpl $8388607, %eax # imm = 0x7FFFFF
+; X64-ZU-NEXT: setzub %al
+; X64-ZU-NEXT: orb %cl, %al
+; X64-ZU-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 147) ; 0x90|0x3 = "subnormal|nan"
ret i1 %class
}
@@ -3256,12 +3483,12 @@ define i1 @issubnormal_or_zero_or_nan_f(float %x) {
; X64-NEXT: setb %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: issubnormal_or_zero_or_nan_f:
-; X64-NDD: # %bb.0:
-; X64-NDD-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; X64-NDD-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; X64-NDD-NEXT: setzub %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: issubnormal_or_zero_or_nan_f:
+; X64-ZU: # %bb.0:
+; X64-ZU-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-ZU-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-ZU-NEXT: setzub %al
+; X64-ZU-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 243) ; 0xf0|0x3 = "subnormal|zero|nan"
ret i1 %class
}
@@ -3285,12 +3512,12 @@ define i1 @issubnormal_or_zero_or_nan_f_daz(float %x) #0 {
; X64-NEXT: sete %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: issubnormal_or_zero_or_nan_f_daz:
-; X64-NDD: # %bb.0:
-; X64-NDD-NEXT: xorps %xmm1, %xmm1
-; X64-NDD-NEXT: ucomiss %xmm1, %xmm0
-; X64-NDD-NEXT: setzue %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: issubnormal_or_zero_or_nan_f_daz:
+; X64-ZU: # %bb.0:
+; X64-ZU-NEXT: xorps %xmm1, %xmm1
+; X64-ZU-NEXT: ucomiss %xmm1, %xmm0
+; X64-ZU-NEXT: setzue %al
+; X64-ZU-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 243) ; 0xf0|0x3 = "subnormal|zero|nan"
ret i1 %class
}
@@ -3311,34 +3538,49 @@ define i1 @issubnormal_or_zero_or_snan_f(float %x) {
; X86-NEXT: orb %cl, %al
; X86-NEXT: retl
;
-; X64-LABEL: issubnormal_or_zero_or_snan_f:
-; X64: # %bb.0:
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: movl %eax, %ecx
-; X64-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
-; X64-NEXT: setl %dl
-; X64-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
-; X64-NEXT: setge %cl
-; X64-NEXT: andb %dl, %cl
-; X64-NEXT: testl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: sete %al
-; X64-NEXT: orb %cl, %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: issubnormal_or_zero_or_snan_f:
+; X64-GENERIC: # %bb.0:
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: movl %eax, %ecx
+; X64-GENERIC-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
+; X64-GENERIC-NEXT: setl %dl
+; X64-GENERIC-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
+; X64-GENERIC-NEXT: setge %cl
+; X64-GENERIC-NEXT: andb %dl, %cl
+; X64-GENERIC-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: sete %al
+; X64-GENERIC-NEXT: orb %cl, %al
+; X64-GENERIC-NEXT: retq
;
; X64-NDD-LABEL: issubnormal_or_zero_or_snan_f:
; X64-NDD: # %bb.0:
; X64-NDD-NEXT: movd %xmm0, %eax
; X64-NDD-NEXT: andl $2147483647, %eax, %ecx # imm = 0x7FFFFFFF
; X64-NDD-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
-; X64-NDD-NEXT: setzul %dl
+; X64-NDD-NEXT: setl %dl
; X64-NDD-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
-; X64-NDD-NEXT: setzuge %cl
+; X64-NDD-NEXT: setge %cl
; X64-NDD-NEXT: andb %dl, %cl
; X64-NDD-NEXT: testl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzue %al
+; X64-NDD-NEXT: sete %al
; X64-NDD-NEXT: orb %cl, %al
; X64-NDD-NEXT: retq
+;
+; X64-ZU-LABEL: issubnormal_or_zero_or_snan_f:
+; X64-ZU: # %bb.0:
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: movl %eax, %ecx
+; X64-ZU-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2143289344, %ecx # imm = 0x7FC00000
+; X64-ZU-NEXT: setzul %dl
+; X64-ZU-NEXT: cmpl $2139095041, %ecx # imm = 0x7F800001
+; X64-ZU-NEXT: setzuge %cl
+; X64-ZU-NEXT: andb %dl, %cl
+; X64-ZU-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzue %al
+; X64-ZU-NEXT: orb %cl, %al
+; X64-ZU-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 241) ; 0x90|0x1 = "subnormal|snan"
ret i1 %class
}
@@ -3366,16 +3608,16 @@ define i1 @issubnormal_or_zero_or_qnan_f(float %x) {
; X64-NEXT: orb %cl, %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: issubnormal_or_zero_or_qnan_f:
-; X64-NDD: # %bb.0:
-; X64-NDD-NEXT: movd %xmm0, %eax
-; X64-NDD-NEXT: testl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzue %cl
-; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NDD-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NDD-NEXT: setzuge %al
-; X64-NDD-NEXT: orb %cl, %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: issubnormal_or_zero_or_qnan_f:
+; X64-ZU: # %bb.0:
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzue %cl
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-ZU-NEXT: setzuge %al
+; X64-ZU-NEXT: orb %cl, %al
+; X64-ZU-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 242) ; 0x90|0x2 = "subnormal|qnan"
ret i1 %class
}
@@ -3396,35 +3638,50 @@ define i1 @not_issubnormal_or_nan_f(float %x) {
; X86-NEXT: orb %dl, %al
; X86-NEXT: retl
;
-; X64-LABEL: not_issubnormal_or_nan_f:
-; X64: # %bb.0:
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: sete %cl
-; X64-NEXT: testl %eax, %eax
-; X64-NEXT: sete %dl
-; X64-NEXT: orb %cl, %dl
-; X64-NEXT: addl $-8388608, %eax # imm = 0xFF800000
-; X64-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; X64-NEXT: setb %al
-; X64-NEXT: orb %dl, %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_issubnormal_or_nan_f:
+; X64-GENERIC: # %bb.0:
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: sete %cl
+; X64-GENERIC-NEXT: testl %eax, %eax
+; X64-GENERIC-NEXT: sete %dl
+; X64-GENERIC-NEXT: orb %cl, %dl
+; X64-GENERIC-NEXT: addl $-8388608, %eax # imm = 0xFF800000
+; X64-GENERIC-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
+; X64-GENERIC-NEXT: setb %al
+; X64-GENERIC-NEXT: orb %dl, %al
+; X64-GENERIC-NEXT: retq
;
; X64-NDD-LABEL: not_issubnormal_or_nan_f:
; X64-NDD: # %bb.0:
; X64-NDD-NEXT: movd %xmm0, %eax
; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzue %cl
+; X64-NDD-NEXT: sete %cl
; X64-NDD-NEXT: testl %eax, %eax
-; X64-NDD-NEXT: setzue %dl
+; X64-NDD-NEXT: sete %dl
; X64-NDD-NEXT: orb %dl, %cl
; X64-NDD-NEXT: addl $-8388608, %eax # imm = 0xFF800000
; X64-NDD-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; X64-NDD-NEXT: setzub %al
+; X64-NDD-NEXT: setb %al
; X64-NDD-NEXT: orb %cl, %al
; X64-NDD-NEXT: retq
+;
+; X64-ZU-LABEL: not_issubnormal_or_nan_f:
+; X64-ZU: # %bb.0:
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzue %cl
+; X64-ZU-NEXT: testl %eax, %eax
+; X64-ZU-NEXT: setzue %dl
+; X64-ZU-NEXT: orb %cl, %dl
+; X64-ZU-NEXT: addl $-8388608, %eax # imm = 0xFF800000
+; X64-ZU-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
+; X64-ZU-NEXT: setzub %al
+; X64-ZU-NEXT: orb %dl, %al
+; X64-ZU-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 876) ; ~(0x90|0x3) = ~"subnormal|nan"
ret i1 %class
}
@@ -3450,12 +3707,12 @@ define i1 @not_issubnormal_or_zero_or_nan_f(float %x) {
; X64-NEXT: setae %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: not_issubnormal_or_zero_or_nan_f:
-; X64-NDD: # %bb.0:
-; X64-NDD-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; X64-NDD-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; X64-NDD-NEXT: setzuae %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: not_issubnormal_or_zero_or_nan_f:
+; X64-ZU: # %bb.0:
+; X64-ZU-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-ZU-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-ZU-NEXT: setzuae %al
+; X64-ZU-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 780) ; ~(0xf0|0x3) = ~"subnormal|zero|nan"
ret i1 %class
}
@@ -3479,12 +3736,12 @@ define i1 @not_issubnormal_or_zero_or_nan_f_daz(float %x) #0 {
; X64-NEXT: setne %al
; X64-NEXT: retq
;
-; X64-NDD-LABEL: not_issubnormal_or_zero_or_nan_f_daz:
-; X64-NDD: # %bb.0:
-; X64-NDD-NEXT: xorps %xmm1, %xmm1
-; X64-NDD-NEXT: ucomiss %xmm1, %xmm0
-; X64-NDD-NEXT: setzune %al
-; X64-NDD-NEXT: retq
+; X64-ZU-LABEL: not_issubnormal_or_zero_or_nan_f_daz:
+; X64-ZU: # %bb.0:
+; X64-ZU-NEXT: xorps %xmm1, %xmm1
+; X64-ZU-NEXT: ucomiss %xmm1, %xmm0
+; X64-ZU-NEXT: setzune %al
+; X64-ZU-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 780) ; ~(0xf0|0x3) = ~"subnormal|zero|nan"
ret i1 %class
}
@@ -3505,35 +3762,50 @@ define i1 @not_issubnormal_or_zero_or_snan_f(float %x) {
; X86-NEXT: orb %dl, %al
; X86-NEXT: retl
;
-; X64-LABEL: not_issubnormal_or_zero_or_snan_f:
-; X64: # %bb.0:
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NEXT: setge %cl
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: sete %dl
-; X64-NEXT: orb %cl, %dl
-; X64-NEXT: addl $-8388608, %eax # imm = 0xFF800000
-; X64-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; X64-NEXT: setb %al
-; X64-NEXT: orb %dl, %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_issubnormal_or_zero_or_snan_f:
+; X64-GENERIC: # %bb.0:
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-GENERIC-NEXT: setge %cl
+; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: sete %dl
+; X64-GENERIC-NEXT: orb %cl, %dl
+; X64-GENERIC-NEXT: addl $-8388608, %eax # imm = 0xFF800000
+; X64-GENERIC-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
+; X64-GENERIC-NEXT: setb %al
+; X64-GENERIC-NEXT: orb %dl, %al
+; X64-GENERIC-NEXT: retq
;
; X64-NDD-LABEL: not_issubnormal_or_zero_or_snan_f:
; X64-NDD: # %bb.0:
; X64-NDD-NEXT: movd %xmm0, %eax
; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
; X64-NDD-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NDD-NEXT: setzuge %cl
+; X64-NDD-NEXT: setge %cl
; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzue %dl
+; X64-NDD-NEXT: sete %dl
; X64-NDD-NEXT: orb %dl, %cl
; X64-NDD-NEXT: addl $-8388608, %eax # imm = 0xFF800000
; X64-NDD-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; X64-NDD-NEXT: setzub %al
+; X64-NDD-NEXT: setb %al
; X64-NDD-NEXT: orb %cl, %al
; X64-NDD-NEXT: retq
+;
+; X64-ZU-LABEL: not_issubnormal_or_zero_or_snan_f:
+; X64-ZU: # %bb.0:
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-ZU-NEXT: setzuge %cl
+; X64-ZU-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzue %dl
+; X64-ZU-NEXT: orb %cl, %dl
+; X64-ZU-NEXT: addl $-8388608, %eax # imm = 0xFF800000
+; X64-ZU-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
+; X64-ZU-NEXT: setzub %al
+; X64-ZU-NEXT: orb %dl, %al
+; X64-ZU-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 782) ; ~(0x90|0x1) = ~"subnormal|snan"
ret i1 %class
}
@@ -3557,41 +3829,59 @@ define i1 @not_issubnormal_or_zero_or_qnan_f(float %x) {
; X86-NEXT: orb %cl, %al
; X86-NEXT: retl
;
-; X64-LABEL: not_issubnormal_or_zero_or_qnan_f:
-; X64: # %bb.0:
-; X64-NEXT: movd %xmm0, %eax
-; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; X64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NEXT: setl %cl
-; X64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-NEXT: setge %dl
-; X64-NEXT: andb %cl, %dl
-; X64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NEXT: sete %cl
-; X64-NEXT: orb %dl, %cl
-; X64-NEXT: addl $-8388608, %eax # imm = 0xFF800000
-; X64-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; X64-NEXT: setb %al
-; X64-NEXT: orb %cl, %al
-; X64-NEXT: retq
+; X64-GENERIC-LABEL: not_issubnormal_or_zero_or_qnan_f:
+; X64-GENERIC: # %bb.0:
+; X64-GENERIC-NEXT: movd %xmm0, %eax
+; X64-GENERIC-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-GENERIC-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-GENERIC-NEXT: setl %cl
+; X64-GENERIC-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-GENERIC-NEXT: setge %dl
+; X64-GENERIC-NEXT: andb %cl, %dl
+; X64-GENERIC-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-GENERIC-NEXT: sete %cl
+; X64-GENERIC-NEXT: orb %dl, %cl
+; X64-GENERIC-NEXT: addl $-8388608, %eax # imm = 0xFF800000
+; X64-GENERIC-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
+; X64-GENERIC-NEXT: setb %al
+; X64-GENERIC-NEXT: orb %cl, %al
+; X64-GENERIC-NEXT: retq
;
; X64-NDD-LABEL: not_issubnormal_or_zero_or_qnan_f:
; X64-NDD: # %bb.0:
; X64-NDD-NEXT: movd %xmm0, %eax
; X64-NDD-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
; X64-NDD-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
-; X64-NDD-NEXT: setzul %cl
+; X64-NDD-NEXT: setl %cl
; X64-NDD-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
-; X64-NDD-NEXT: setzuge %dl
+; X64-NDD-NEXT: setge %dl
; X64-NDD-NEXT: andb %dl, %cl
; X64-NDD-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; X64-NDD-NEXT: setzue %dl
+; X64-NDD-NEXT: sete %dl
; X64-NDD-NEXT: orb %dl, %cl
; X64-NDD-NEXT: addl $-8388608, %eax # imm = 0xFF800000
; X64-NDD-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; X64-NDD-NEXT: setzub %al
+; X64-NDD-NEXT: setb %al
; X64-NDD-NEXT: orb %cl, %al
; X64-NDD-NEXT: retq
+;
+; X64-ZU-LABEL: not_issubnormal_or_zero_or_qnan_f:
+; X64-ZU: # %bb.0:
+; X64-ZU-NEXT: movd %xmm0, %eax
+; X64-ZU-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
+; X64-ZU-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
+; X64-ZU-NEXT: setzul %cl
+; X64-ZU-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
+; X64-ZU-NEXT: setzuge %dl
+; X64-ZU-NEXT: andb %cl, %dl
+; X64-ZU-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
+; X64-ZU-NEXT: setzue %cl
+; X64-ZU-NEXT: orb %dl, %cl
+; X64-ZU-NEXT: addl $-8388608, %eax # imm = 0xFF800000
+; X64-ZU-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
+; X64-ZU-NEXT: setzub %al
+; X64-ZU-NEXT: orb %cl, %al
+; X64-ZU-NEXT: retq
%class = tail call i1 @llvm.is.fpclass.f32(float %x, i32 781) ; ~(0x90|0x2) = ~"subnormal|qnan"
ret i1 %class
}
@@ -3607,5 +3897,3 @@ attributes #0 = { "denormal-fp-math"="ieee,preserve-sign" }
; Maybe daz
attributes #1 = { "denormal-fp-math"="ieee,dynamic" }
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; X64-GENERIC: {{.*}}
diff --git a/llvm/test/CodeGen/X86/scmp.ll b/llvm/test/CodeGen/X86/scmp.ll
index 874913629e9e3..f20d8aee3185a 100644
--- a/llvm/test/CodeGen/X86/scmp.ll
+++ b/llvm/test/CodeGen/X86/scmp.ll
@@ -3,6 +3,7 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=X64,SSE,SSE4
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=X64,AVX,AVX2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=X64,AVX,AVX512
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+zu | FileCheck %s --check-prefix=ZU
; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=X86
define i8 @scmp.8.8(i8 %x, i8 %y) nounwind {
@@ -14,6 +15,14 @@ define i8 @scmp.8.8(i8 %x, i8 %y) nounwind {
; X64-NEXT: subb %cl, %al
; X64-NEXT: retq
;
+; ZU-LABEL: scmp.8.8:
+; ZU: # %bb.0:
+; ZU-NEXT: cmpb %sil, %dil
+; ZU-NEXT: setzul %cl
+; ZU-NEXT: setzug %al
+; ZU-NEXT: subb %cl, %al
+; ZU-NEXT: retq
+;
; X86-LABEL: scmp.8.8:
; X86: # %bb.0:
; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
@@ -35,6 +44,14 @@ define i8 @scmp.8.16(i16 %x, i16 %y) nounwind {
; X64-NEXT: subb %cl, %al
; X64-NEXT: retq
;
+; ZU-LABEL: scmp.8.16:
+; ZU: # %bb.0:
+; ZU-NEXT: cmpw %si, %di
+; ZU-NEXT: setzul %cl
+; ZU-NEXT: setzug %al
+; ZU-NEXT: subb %cl, %al
+; ZU-NEXT: retq
+;
; X86-LABEL: scmp.8.16:
; X86: # %bb.0:
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
@@ -56,6 +73,14 @@ define i8 @scmp.8.32(i32 %x, i32 %y) nounwind {
; X64-NEXT: subb %cl, %al
; X64-NEXT: retq
;
+; ZU-LABEL: scmp.8.32:
+; ZU: # %bb.0:
+; ZU-NEXT: cmpl %esi, %edi
+; ZU-NEXT: setzul %cl
+; ZU-NEXT: setzug %al
+; ZU-NEXT: subb %cl, %al
+; ZU-NEXT: retq
+;
; X86-LABEL: scmp.8.32:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
@@ -77,6 +102,14 @@ define i8 @scmp.8.64(i64 %x, i64 %y) nounwind {
; X64-NEXT: subb %cl, %al
; X64-NEXT: retq
;
+; ZU-LABEL: scmp.8.64:
+; ZU: # %bb.0:
+; ZU-NEXT: cmpq %rsi, %rdi
+; ZU-NEXT: setzul %cl
+; ZU-NEXT: setzug %al
+; ZU-NEXT: subb %cl, %al
+; ZU-NEXT: retq
+;
; X86-LABEL: scmp.8.64:
; X86: # %bb.0:
; X86-NEXT: pushl %ebx
@@ -115,6 +148,18 @@ define i8 @scmp.8.128(i128 %x, i128 %y) nounwind {
; X64-NEXT: subb %r8b, %al
; X64-NEXT: retq
;
+; ZU-LABEL: scmp.8.128:
+; ZU: # %bb.0:
+; ZU-NEXT: cmpq %rdx, %rdi
+; ZU-NEXT: movq %rsi, %rax
+; ZU-NEXT: sbbq %rcx, %rax
+; ZU-NEXT: setzul %r8b
+; ZU-NEXT: cmpq %rdi, %rdx
+; ZU-NEXT: sbbq %rsi, %rcx
+; ZU-NEXT: setzul %al
+; ZU-NEXT: subb %r8b, %al
+; ZU-NEXT: retq
+;
; X86-LABEL: scmp.8.128:
; X86: # %bb.0:
; X86-NEXT: pushl %ebp
@@ -161,6 +206,15 @@ define i32 @scmp.32.32(i32 %x, i32 %y) nounwind {
; X64-NEXT: movsbl %cl, %eax
; X64-NEXT: retq
;
+; ZU-LABEL: scmp.32.32:
+; ZU: # %bb.0:
+; ZU-NEXT: cmpl %esi, %edi
+; ZU-NEXT: setzul %al
+; ZU-NEXT: setzug %cl
+; ZU-NEXT: subb %al, %cl
+; ZU-NEXT: movsbl %cl, %eax
+; ZU-NEXT: retq
+;
; X86-LABEL: scmp.32.32:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
@@ -184,6 +238,15 @@ define i32 @scmp.32.64(i64 %x, i64 %y) nounwind {
; X64-NEXT: movsbl %cl, %eax
; X64-NEXT: retq
;
+; ZU-LABEL: scmp.32.64:
+; ZU: # %bb.0:
+; ZU-NEXT: cmpq %rsi, %rdi
+; ZU-NEXT: setzul %al
+; ZU-NEXT: setzug %cl
+; ZU-NEXT: subb %al, %cl
+; ZU-NEXT: movsbl %cl, %eax
+; ZU-NEXT: retq
+;
; X86-LABEL: scmp.32.64:
; X86: # %bb.0:
; X86-NEXT: pushl %ebx
@@ -220,6 +283,15 @@ define i64 @scmp.64.64(i64 %x, i64 %y) nounwind {
; X64-NEXT: movsbq %cl, %rax
; X64-NEXT: retq
;
+; ZU-LABEL: scmp.64.64:
+; ZU: # %bb.0:
+; ZU-NEXT: cmpq %rsi, %rdi
+; ZU-NEXT: setzul %al
+; ZU-NEXT: setzug %cl
+; ZU-NEXT: subb %al, %cl
+; ZU-NEXT: movsbq %cl, %rax
+; ZU-NEXT: retq
+;
; X86-LABEL: scmp.64.64:
; X86: # %bb.0:
; X86-NEXT: pushl %ebx
@@ -257,6 +329,14 @@ define i4 @scmp_narrow_result(i32 %x, i32 %y) nounwind {
; X64-NEXT: subb %cl, %al
; X64-NEXT: retq
;
+; ZU-LABEL: scmp_narrow_result:
+; ZU: # %bb.0:
+; ZU-NEXT: cmpl %esi, %edi
+; ZU-NEXT: setzul %cl
+; ZU-NEXT: setzug %al
+; ZU-NEXT: subb %cl, %al
+; ZU-NEXT: retq
+;
; X86-LABEL: scmp_narrow_result:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
@@ -282,6 +362,18 @@ define i8 @scmp_narrow_op(i62 %x, i62 %y) nounwind {
; X64-NEXT: subb %cl, %al
; X64-NEXT: retq
;
+; ZU-LABEL: scmp_narrow_op:
+; ZU: # %bb.0:
+; ZU-NEXT: shlq $2, %rsi
+; ZU-NEXT: sarq $2, %rsi
+; ZU-NEXT: shlq $2, %rdi
+; ZU-NEXT: sarq $2, %rdi
+; ZU-NEXT: cmpq %rsi, %rdi
+; ZU-NEXT: setzul %cl
+; ZU-NEXT: setzug %al
+; ZU-NEXT: subb %cl, %al
+; ZU-NEXT: retq
+;
; X86-LABEL: scmp_narrow_op:
; X86: # %bb.0:
; X86-NEXT: pushl %ebx
@@ -325,6 +417,19 @@ define i141 @scmp_wide_result(i32 %x, i32 %y) nounwind {
; X64-NEXT: andl $8191, %ecx # imm = 0x1FFF
; X64-NEXT: retq
;
+; ZU-LABEL: scmp_wide_result:
+; ZU: # %bb.0:
+; ZU-NEXT: cmpl %esi, %edi
+; ZU-NEXT: setzul %al
+; ZU-NEXT: setzug %cl
+; ZU-NEXT: subb %al, %cl
+; ZU-NEXT: movsbq %cl, %rax
+; ZU-NEXT: movq %rax, %rdx
+; ZU-NEXT: sarq $63, %rdx
+; ZU-NEXT: movl %edx, %ecx
+; ZU-NEXT: andl $8191, %ecx # imm = 0x1FFF
+; ZU-NEXT: retq
+;
; X86-LABEL: scmp_wide_result:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
@@ -363,6 +468,22 @@ define i8 @scmp_wide_op(i109 %x, i109 %y) nounwind {
; X64-NEXT: subb %r8b, %al
; X64-NEXT: retq
;
+; ZU-LABEL: scmp_wide_op:
+; ZU: # %bb.0:
+; ZU-NEXT: shlq $19, %rcx
+; ZU-NEXT: sarq $19, %rcx
+; ZU-NEXT: shlq $19, %rsi
+; ZU-NEXT: sarq $19, %rsi
+; ZU-NEXT: cmpq %rdx, %rdi
+; ZU-NEXT: movq %rsi, %rax
+; ZU-NEXT: sbbq %rcx, %rax
+; ZU-NEXT: setzul %r8b
+; ZU-NEXT: cmpq %rdi, %rdx
+; ZU-NEXT: sbbq %rsi, %rcx
+; ZU-NEXT: setzul %al
+; ZU-NEXT: subb %r8b, %al
+; ZU-NEXT: retq
+;
; X86-LABEL: scmp_wide_op:
; X86: # %bb.0:
; X86-NEXT: pushl %ebp
@@ -417,6 +538,19 @@ define i41 @scmp_uncommon_types(i7 %x, i7 %y) nounwind {
; X64-NEXT: movsbq %cl, %rax
; X64-NEXT: retq
;
+; ZU-LABEL: scmp_uncommon_types:
+; ZU: # %bb.0:
+; ZU-NEXT: addb %sil, %sil
+; ZU-NEXT: sarb %sil
+; ZU-NEXT: addb %dil, %dil
+; ZU-NEXT: sarb %dil
+; ZU-NEXT: cmpb %sil, %dil
+; ZU-NEXT: setzul %al
+; ZU-NEXT: setzug %cl
+; ZU-NEXT: subb %al, %cl
+; ZU-NEXT: movsbq %cl, %rax
+; ZU-NEXT: retq
+;
; X86-LABEL: scmp_uncommon_types:
; X86: # %bb.0:
; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
@@ -463,6 +597,15 @@ define <4 x i32> @scmp_normal_vectors(<4 x i32> %x, <4 x i32> %y) nounwind {
; AVX512-NEXT: vmovdqa32 %xmm1, %xmm0 {%k1}
; AVX512-NEXT: retq
;
+; ZU-LABEL: scmp_normal_vectors:
+; ZU: # %bb.0:
+; ZU-NEXT: movdqa %xmm0, %xmm2
+; ZU-NEXT: pcmpgtd %xmm1, %xmm2
+; ZU-NEXT: pcmpgtd %xmm0, %xmm1
+; ZU-NEXT: psubd %xmm2, %xmm1
+; ZU-NEXT: movdqa %xmm1, %xmm0
+; ZU-NEXT: retq
+;
; X86-LABEL: scmp_normal_vectors:
; X86: # %bb.0:
; X86-NEXT: pushl %ebx
@@ -620,6 +763,51 @@ define <4 x i8> @scmp_narrow_vec_result(<4 x i32> %x, <4 x i32> %y) nounwind {
; AVX-NEXT: vpinsrb $3, %ecx, %xmm2, %xmm0
; AVX-NEXT: retq
;
+; ZU-LABEL: scmp_narrow_vec_result:
+; ZU: # %bb.0:
+; ZU-NEXT: movd %xmm1, %eax
+; ZU-NEXT: movd %xmm0, %ecx
+; ZU-NEXT: cmpl %eax, %ecx
+; ZU-NEXT: setzul %al
+; ZU-NEXT: setzug %cl
+; ZU-NEXT: subb %al, %cl
+; ZU-NEXT: movzbl %cl, %eax
+; ZU-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,1,1]
+; ZU-NEXT: movd %xmm2, %ecx
+; ZU-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,1,1]
+; ZU-NEXT: movd %xmm2, %edx
+; ZU-NEXT: cmpl %ecx, %edx
+; ZU-NEXT: setzul %cl
+; ZU-NEXT: setzug %dl
+; ZU-NEXT: subb %cl, %dl
+; ZU-NEXT: movzbl %dl, %ecx
+; ZU-NEXT: shll $8, %ecx
+; ZU-NEXT: orl %eax, %ecx
+; ZU-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,2,3]
+; ZU-NEXT: movd %xmm2, %eax
+; ZU-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,2,3]
+; ZU-NEXT: movd %xmm2, %edx
+; ZU-NEXT: cmpl %eax, %edx
+; ZU-NEXT: setzul %al
+; ZU-NEXT: setzug %dl
+; ZU-NEXT: subb %al, %dl
+; ZU-NEXT: movzbl %dl, %eax
+; ZU-NEXT: shll $16, %eax
+; ZU-NEXT: orl %ecx, %eax
+; ZU-NEXT: pshufd {{.*#+}} xmm1 = xmm1[3,3,3,3]
+; ZU-NEXT: movd %xmm1, %ecx
+; ZU-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,3]
+; ZU-NEXT: movd %xmm0, %edx
+; ZU-NEXT: cmpl %ecx, %edx
+; ZU-NEXT: setzul %cl
+; ZU-NEXT: setzug %dl
+; ZU-NEXT: subb %cl, %dl
+; ZU-NEXT: movzbl %dl, %ecx
+; ZU-NEXT: shll $24, %ecx
+; ZU-NEXT: orl %eax, %ecx
+; ZU-NEXT: movd %ecx, %xmm0
+; ZU-NEXT: retq
+;
; X86-LABEL: scmp_narrow_vec_result:
; X86: # %bb.0:
; X86-NEXT: pushl %ebx
@@ -705,6 +893,21 @@ define <4 x i32> @scmp_narrow_vec_op(<4 x i8> %x, <4 x i8> %y) nounwind {
; AVX512-NEXT: vmovdqa32 %xmm1, %xmm0 {%k1}
; AVX512-NEXT: retq
;
+; ZU-LABEL: scmp_narrow_vec_op:
+; ZU: # %bb.0:
+; ZU-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; ZU-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3]
+; ZU-NEXT: psrad $24, %xmm1
+; ZU-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; ZU-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
+; ZU-NEXT: psrad $24, %xmm0
+; ZU-NEXT: movdqa %xmm0, %xmm2
+; ZU-NEXT: pcmpgtd %xmm1, %xmm2
+; ZU-NEXT: pcmpgtd %xmm0, %xmm1
+; ZU-NEXT: psubd %xmm2, %xmm1
+; ZU-NEXT: movdqa %xmm1, %xmm0
+; ZU-NEXT: retq
+;
; X86-LABEL: scmp_narrow_vec_op:
; X86: # %bb.0:
; X86-NEXT: pushl %ebx
@@ -852,6 +1055,48 @@ define <16 x i32> @scmp_wide_vec_result(<16 x i8> %x, <16 x i8> %y) nounwind {
; AVX512-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1}
; AVX512-NEXT: retq
;
+; ZU-LABEL: scmp_wide_vec_result:
+; ZU: # %bb.0:
+; ZU-NEXT: movdqa %xmm1, %xmm2
+; ZU-NEXT: movdqa %xmm0, %xmm3
+; ZU-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; ZU-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; ZU-NEXT: psrad $24, %xmm0
+; ZU-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3],xmm4[4],xmm3[4],xmm4[5],xmm3[5],xmm4[6],xmm3[6],xmm4[7],xmm3[7]
+; ZU-NEXT: punpcklwd {{.*#+}} xmm5 = xmm5[0],xmm4[0],xmm5[1],xmm4[1],xmm5[2],xmm4[2],xmm5[3],xmm4[3]
+; ZU-NEXT: psrad $24, %xmm5
+; ZU-NEXT: movdqa %xmm5, %xmm6
+; ZU-NEXT: pcmpgtd %xmm0, %xmm6
+; ZU-NEXT: pcmpgtd %xmm5, %xmm0
+; ZU-NEXT: psubd %xmm6, %xmm0
+; ZU-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
+; ZU-NEXT: psrad $24, %xmm1
+; ZU-NEXT: punpckhwd {{.*#+}} xmm4 = xmm4[4,4,5,5,6,6,7,7]
+; ZU-NEXT: psrad $24, %xmm4
+; ZU-NEXT: movdqa %xmm4, %xmm5
+; ZU-NEXT: pcmpgtd %xmm1, %xmm5
+; ZU-NEXT: pcmpgtd %xmm4, %xmm1
+; ZU-NEXT: psubd %xmm5, %xmm1
+; ZU-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm2[8],xmm4[9],xmm2[9],xmm4[10],xmm2[10],xmm4[11],xmm2[11],xmm4[12],xmm2[12],xmm4[13],xmm2[13],xmm4[14],xmm2[14],xmm4[15],xmm2[15]
+; ZU-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1],xmm2[2],xmm4[2],xmm2[3],xmm4[3]
+; ZU-NEXT: psrad $24, %xmm2
+; ZU-NEXT: punpckhbw {{.*#+}} xmm5 = xmm5[8],xmm3[8],xmm5[9],xmm3[9],xmm5[10],xmm3[10],xmm5[11],xmm3[11],xmm5[12],xmm3[12],xmm5[13],xmm3[13],xmm5[14],xmm3[14],xmm5[15],xmm3[15]
+; ZU-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm5[0],xmm3[1],xmm5[1],xmm3[2],xmm5[2],xmm3[3],xmm5[3]
+; ZU-NEXT: psrad $24, %xmm3
+; ZU-NEXT: movdqa %xmm3, %xmm6
+; ZU-NEXT: pcmpgtd %xmm2, %xmm6
+; ZU-NEXT: pcmpgtd %xmm3, %xmm2
+; ZU-NEXT: psubd %xmm6, %xmm2
+; ZU-NEXT: punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm4[4],xmm3[5],xmm4[5],xmm3[6],xmm4[6],xmm3[7],xmm4[7]
+; ZU-NEXT: psrad $24, %xmm3
+; ZU-NEXT: punpckhwd {{.*#+}} xmm4 = xmm4[4],xmm5[4],xmm4[5],xmm5[5],xmm4[6],xmm5[6],xmm4[7],xmm5[7]
+; ZU-NEXT: psrad $24, %xmm4
+; ZU-NEXT: movdqa %xmm4, %xmm5
+; ZU-NEXT: pcmpgtd %xmm3, %xmm5
+; ZU-NEXT: pcmpgtd %xmm4, %xmm3
+; ZU-NEXT: psubd %xmm5, %xmm3
+; ZU-NEXT: retq
+;
; X86-LABEL: scmp_wide_vec_result:
; X86: # %bb.0:
; X86-NEXT: pushl %ebp
@@ -1504,6 +1749,146 @@ define <16 x i8> @scmp_wide_vec_op(<16 x i64> %x, <16 x i64> %y) nounwind {
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
;
+; ZU-LABEL: scmp_wide_vec_op:
+; ZU: # %bb.0:
+; ZU-NEXT: movq %xmm7, %rax
+; ZU-NEXT: cmpq {{[0-9]+}}(%rsp), %rax
+; ZU-NEXT: setzul %al
+; ZU-NEXT: setzug %cl
+; ZU-NEXT: subb %al, %cl
+; ZU-NEXT: movzbl %cl, %eax
+; ZU-NEXT: movd %eax, %xmm8
+; ZU-NEXT: pshufd {{.*#+}} xmm7 = xmm7[2,3,2,3]
+; ZU-NEXT: movq %xmm7, %rax
+; ZU-NEXT: cmpq {{[0-9]+}}(%rsp), %rax
+; ZU-NEXT: setzul %al
+; ZU-NEXT: setzug %cl
+; ZU-NEXT: subb %al, %cl
+; ZU-NEXT: movzbl %cl, %eax
+; ZU-NEXT: movd %eax, %xmm7
+; ZU-NEXT: punpcklbw {{.*#+}} xmm8 = xmm8[0],xmm7[0],xmm8[1],xmm7[1],xmm8[2],xmm7[2],xmm8[3],xmm7[3],xmm8[4],xmm7[4],xmm8[5],xmm7[5],xmm8[6],xmm7[6],xmm8[7],xmm7[7]
+; ZU-NEXT: movq %xmm6, %rax
+; ZU-NEXT: cmpq {{[0-9]+}}(%rsp), %rax
+; ZU-NEXT: setzul %al
+; ZU-NEXT: setzug %cl
+; ZU-NEXT: subb %al, %cl
+; ZU-NEXT: movzbl %cl, %eax
+; ZU-NEXT: movd %eax, %xmm7
+; ZU-NEXT: pshufd {{.*#+}} xmm6 = xmm6[2,3,2,3]
+; ZU-NEXT: movq %xmm6, %rax
+; ZU-NEXT: cmpq {{[0-9]+}}(%rsp), %rax
+; ZU-NEXT: setzul %al
+; ZU-NEXT: setzug %cl
+; ZU-NEXT: subb %al, %cl
+; ZU-NEXT: movzbl %cl, %eax
+; ZU-NEXT: movd %eax, %xmm6
+; ZU-NEXT: punpcklbw {{.*#+}} xmm7 = xmm7[0],xmm6[0],xmm7[1],xmm6[1],xmm7[2],xmm6[2],xmm7[3],xmm6[3],xmm7[4],xmm6[4],xmm7[5],xmm6[5],xmm7[6],xmm6[6],xmm7[7],xmm6[7]
+; ZU-NEXT: punpcklwd {{.*#+}} xmm7 = xmm7[0],xmm8[0],xmm7[1],xmm8[1],xmm7[2],xmm8[2],xmm7[3],xmm8[3]
+; ZU-NEXT: movq %xmm5, %rax
+; ZU-NEXT: cmpq {{[0-9]+}}(%rsp), %rax
+; ZU-NEXT: setzul %al
+; ZU-NEXT: setzug %cl
+; ZU-NEXT: subb %al, %cl
+; ZU-NEXT: movzbl %cl, %eax
+; ZU-NEXT: movd %eax, %xmm6
+; ZU-NEXT: pshufd {{.*#+}} xmm5 = xmm5[2,3,2,3]
+; ZU-NEXT: movq %xmm5, %rax
+; ZU-NEXT: cmpq {{[0-9]+}}(%rsp), %rax
+; ZU-NEXT: setzul %al
+; ZU-NEXT: setzug %cl
+; ZU-NEXT: subb %al, %cl
+; ZU-NEXT: movzbl %cl, %eax
+; ZU-NEXT: movd %eax, %xmm5
+; ZU-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm5[0],xmm6[1],xmm5[1],xmm6[2],xmm5[2],xmm6[3],xmm5[3],xmm6[4],xmm5[4],xmm6[5],xmm5[5],xmm6[6],xmm5[6],xmm6[7],xmm5[7]
+; ZU-NEXT: movq %xmm4, %rax
+; ZU-NEXT: cmpq {{[0-9]+}}(%rsp), %rax
+; ZU-NEXT: setzul %al
+; ZU-NEXT: setzug %cl
+; ZU-NEXT: subb %al, %cl
+; ZU-NEXT: movzbl %cl, %eax
+; ZU-NEXT: movd %eax, %xmm5
+; ZU-NEXT: pshufd {{.*#+}} xmm4 = xmm4[2,3,2,3]
+; ZU-NEXT: movq %xmm4, %rax
+; ZU-NEXT: cmpq {{[0-9]+}}(%rsp), %rax
+; ZU-NEXT: setzul %al
+; ZU-NEXT: setzug %cl
+; ZU-NEXT: subb %al, %cl
+; ZU-NEXT: movzbl %cl, %eax
+; ZU-NEXT: movd %eax, %xmm4
+; ZU-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm4[0],xmm5[1],xmm4[1],xmm5[2],xmm4[2],xmm5[3],xmm4[3],xmm5[4],xmm4[4],xmm5[5],xmm4[5],xmm5[6],xmm4[6],xmm5[7],xmm4[7]
+; ZU-NEXT: punpcklwd {{.*#+}} xmm5 = xmm5[0],xmm6[0],xmm5[1],xmm6[1],xmm5[2],xmm6[2],xmm5[3],xmm6[3]
+; ZU-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm7[0],xmm5[1],xmm7[1]
+; ZU-NEXT: movq %xmm3, %rax
+; ZU-NEXT: cmpq {{[0-9]+}}(%rsp), %rax
+; ZU-NEXT: setzul %al
+; ZU-NEXT: setzug %cl
+; ZU-NEXT: subb %al, %cl
+; ZU-NEXT: movzbl %cl, %eax
+; ZU-NEXT: movd %eax, %xmm4
+; ZU-NEXT: pshufd {{.*#+}} xmm3 = xmm3[2,3,2,3]
+; ZU-NEXT: movq %xmm3, %rax
+; ZU-NEXT: cmpq {{[0-9]+}}(%rsp), %rax
+; ZU-NEXT: setzul %al
+; ZU-NEXT: setzug %cl
+; ZU-NEXT: subb %al, %cl
+; ZU-NEXT: movzbl %cl, %eax
+; ZU-NEXT: movd %eax, %xmm3
+; ZU-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3],xmm4[4],xmm3[4],xmm4[5],xmm3[5],xmm4[6],xmm3[6],xmm4[7],xmm3[7]
+; ZU-NEXT: movq %xmm2, %rax
+; ZU-NEXT: cmpq {{[0-9]+}}(%rsp), %rax
+; ZU-NEXT: setzul %al
+; ZU-NEXT: setzug %cl
+; ZU-NEXT: subb %al, %cl
+; ZU-NEXT: movzbl %cl, %eax
+; ZU-NEXT: movd %eax, %xmm3
+; ZU-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,2,3]
+; ZU-NEXT: movq %xmm2, %rax
+; ZU-NEXT: cmpq {{[0-9]+}}(%rsp), %rax
+; ZU-NEXT: setzul %al
+; ZU-NEXT: setzug %cl
+; ZU-NEXT: subb %al, %cl
+; ZU-NEXT: movzbl %cl, %eax
+; ZU-NEXT: movd %eax, %xmm2
+; ZU-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3],xmm3[4],xmm2[4],xmm3[5],xmm2[5],xmm3[6],xmm2[6],xmm3[7],xmm2[7]
+; ZU-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1],xmm3[2],xmm4[2],xmm3[3],xmm4[3]
+; ZU-NEXT: movq %xmm1, %rax
+; ZU-NEXT: cmpq {{[0-9]+}}(%rsp), %rax
+; ZU-NEXT: setzul %al
+; ZU-NEXT: setzug %cl
+; ZU-NEXT: subb %al, %cl
+; ZU-NEXT: movzbl %cl, %eax
+; ZU-NEXT: movd %eax, %xmm2
+; ZU-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
+; ZU-NEXT: movq %xmm1, %rax
+; ZU-NEXT: cmpq {{[0-9]+}}(%rsp), %rax
+; ZU-NEXT: setzul %al
+; ZU-NEXT: setzug %cl
+; ZU-NEXT: subb %al, %cl
+; ZU-NEXT: movzbl %cl, %eax
+; ZU-NEXT: movd %eax, %xmm1
+; ZU-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3],xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7]
+; ZU-NEXT: movq %xmm0, %rax
+; ZU-NEXT: cmpq {{[0-9]+}}(%rsp), %rax
+; ZU-NEXT: setzul %al
+; ZU-NEXT: setzug %cl
+; ZU-NEXT: subb %al, %cl
+; ZU-NEXT: movzbl %cl, %eax
+; ZU-NEXT: movd %eax, %xmm1
+; ZU-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
+; ZU-NEXT: movq %xmm0, %rax
+; ZU-NEXT: cmpq {{[0-9]+}}(%rsp), %rax
+; ZU-NEXT: setzul %al
+; ZU-NEXT: setzug %cl
+; ZU-NEXT: subb %al, %cl
+; ZU-NEXT: movzbl %cl, %eax
+; ZU-NEXT: movd %eax, %xmm0
+; ZU-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
+; ZU-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
+; ZU-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1]
+; ZU-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm5[0]
+; ZU-NEXT: movdqa %xmm1, %xmm0
+; ZU-NEXT: retq
+;
; X86-LABEL: scmp_wide_vec_op:
; X86: # %bb.0:
; X86-NEXT: pushl %ebp
@@ -2215,6 +2600,163 @@ define <7 x i117> @scmp_uncommon_vectors(<7 x i7> %x, <7 x i7> %y) nounwind {
; AVX-NEXT: popq %rbp
; AVX-NEXT: retq
;
+; ZU-LABEL: scmp_uncommon_vectors:
+; ZU: # %bb.0:
+; ZU-NEXT: pushq %rbp
+; ZU-NEXT: pushq %r15
+; ZU-NEXT: pushq %r14
+; ZU-NEXT: pushq %r13
+; ZU-NEXT: pushq %r12
+; ZU-NEXT: pushq %rbx
+; ZU-NEXT: movq %rdi, %rax
+; ZU-NEXT: movzbl {{[0-9]+}}(%rsp), %edi
+; ZU-NEXT: movzbl {{[0-9]+}}(%rsp), %r10d
+; ZU-NEXT: movzbl {{[0-9]+}}(%rsp), %r11d
+; ZU-NEXT: movzbl {{[0-9]+}}(%rsp), %ebx
+; ZU-NEXT: movzbl {{[0-9]+}}(%rsp), %ebp
+; ZU-NEXT: movzbl {{[0-9]+}}(%rsp), %r14d
+; ZU-NEXT: movzbl {{[0-9]+}}(%rsp), %r15d
+; ZU-NEXT: addb %r15b, %r15b
+; ZU-NEXT: sarb %r15b
+; ZU-NEXT: addb %sil, %sil
+; ZU-NEXT: sarb %sil
+; ZU-NEXT: cmpb %r15b, %sil
+; ZU-NEXT: setzul %sil
+; ZU-NEXT: setzug %r15b
+; ZU-NEXT: subb %sil, %r15b
+; ZU-NEXT: movsbq %r15b, %rsi
+; ZU-NEXT: movq %rsi, (%rax)
+; ZU-NEXT: movq %rsi, %xmm0
+; ZU-NEXT: sarq $63, %rsi
+; ZU-NEXT: addb %r14b, %r14b
+; ZU-NEXT: sarb %r14b
+; ZU-NEXT: movzbl {{[0-9]+}}(%rsp), %r15d
+; ZU-NEXT: addb %r15b, %r15b
+; ZU-NEXT: sarb %r15b
+; ZU-NEXT: cmpb %r14b, %r15b
+; ZU-NEXT: setzul %r14b
+; ZU-NEXT: setzug %r15b
+; ZU-NEXT: subb %r14b, %r15b
+; ZU-NEXT: movsbq %r15b, %r14
+; ZU-NEXT: movq %r14, %r15
+; ZU-NEXT: sarq $63, %r15
+; ZU-NEXT: addb %bpl, %bpl
+; ZU-NEXT: sarb %bpl
+; ZU-NEXT: addb %dl, %dl
+; ZU-NEXT: sarb %dl
+; ZU-NEXT: cmpb %bpl, %dl
+; ZU-NEXT: setzul %dl
+; ZU-NEXT: setzug %bpl
+; ZU-NEXT: subb %dl, %bpl
+; ZU-NEXT: movsbq %bpl, %rdx
+; ZU-NEXT: movq %rdx, %r12
+; ZU-NEXT: sarq $63, %r12
+; ZU-NEXT: addb %bl, %bl
+; ZU-NEXT: sarb %bl
+; ZU-NEXT: addb %cl, %cl
+; ZU-NEXT: sarb %cl
+; ZU-NEXT: cmpb %bl, %cl
+; ZU-NEXT: setzul %cl
+; ZU-NEXT: setzug %bl
+; ZU-NEXT: subb %cl, %bl
+; ZU-NEXT: movsbq %bl, %rbx
+; ZU-NEXT: movq %rbx, %rcx
+; ZU-NEXT: sarq $63, %rcx
+; ZU-NEXT: addb %r11b, %r11b
+; ZU-NEXT: sarb %r11b
+; ZU-NEXT: addb %r8b, %r8b
+; ZU-NEXT: sarb %r8b
+; ZU-NEXT: cmpb %r11b, %r8b
+; ZU-NEXT: setzul %r8b
+; ZU-NEXT: setzug %r11b
+; ZU-NEXT: subb %r8b, %r11b
+; ZU-NEXT: movsbq %r11b, %r8
+; ZU-NEXT: movq %r8, %r11
+; ZU-NEXT: sarq $63, %r11
+; ZU-NEXT: addb %r10b, %r10b
+; ZU-NEXT: sarb %r10b
+; ZU-NEXT: addb %r9b, %r9b
+; ZU-NEXT: sarb %r9b
+; ZU-NEXT: cmpb %r10b, %r9b
+; ZU-NEXT: setzul %r9b
+; ZU-NEXT: setzug %r10b
+; ZU-NEXT: subb %r9b, %r10b
+; ZU-NEXT: movsbq %r10b, %r9
+; ZU-NEXT: movq %r9, %r10
+; ZU-NEXT: sarq $63, %r10
+; ZU-NEXT: addb %dil, %dil
+; ZU-NEXT: sarb %dil
+; ZU-NEXT: movzbl {{[0-9]+}}(%rsp), %ebp
+; ZU-NEXT: addb %bpl, %bpl
+; ZU-NEXT: sarb %bpl
+; ZU-NEXT: cmpb %dil, %bpl
+; ZU-NEXT: setzul %dil
+; ZU-NEXT: setzug %bpl
+; ZU-NEXT: subb %dil, %bpl
+; ZU-NEXT: movsbq %bpl, %rdi
+; ZU-NEXT: movq %rdi, %r13
+; ZU-NEXT: sarq $63, %r13
+; ZU-NEXT: movl %r13d, 96(%rax)
+; ZU-NEXT: movabsq $2251799813685247, %rbp # imm = 0x7FFFFFFFFFFFF
+; ZU-NEXT: andq %r13, %rbp
+; ZU-NEXT: shldq $62, %rdi, %r13
+; ZU-NEXT: movq %r13, 88(%rax)
+; ZU-NEXT: movq %r10, %r13
+; ZU-NEXT: shldq $20, %r9, %r13
+; ZU-NEXT: movq %r13, 64(%rax)
+; ZU-NEXT: movq %r11, %r13
+; ZU-NEXT: shldq $31, %r8, %r13
+; ZU-NEXT: movq %r13, 48(%rax)
+; ZU-NEXT: movq %rcx, %r13
+; ZU-NEXT: shldq $42, %rbx, %r13
+; ZU-NEXT: movq %r13, 32(%rax)
+; ZU-NEXT: movabsq $9007199254738944, %r13 # imm = 0x1FFFFFFFFFF800
+; ZU-NEXT: andq %r12, %r13
+; ZU-NEXT: shldq $53, %rdx, %r12
+; ZU-NEXT: movq %r12, 16(%rax)
+; ZU-NEXT: movq %rbp, %r12
+; ZU-NEXT: shrq $48, %r12
+; ZU-NEXT: movb %r12b, 102(%rax)
+; ZU-NEXT: shrq $32, %rbp
+; ZU-NEXT: movw %bp, 100(%rax)
+; ZU-NEXT: movabsq $9007199254740991, %r12 # imm = 0x1FFFFFFFFFFFFF
+; ZU-NEXT: andq %r12, %r15
+; ZU-NEXT: shldq $9, %r14, %r15
+; ZU-NEXT: shlq $62, %rdi
+; ZU-NEXT: orq %r15, %rdi
+; ZU-NEXT: movq %rdi, 80(%rax)
+; ZU-NEXT: shlq $42, %rbx
+; ZU-NEXT: shrq $11, %r13
+; ZU-NEXT: orq %rbx, %r13
+; ZU-NEXT: movq %r13, 24(%rax)
+; ZU-NEXT: shlq $9, %r14
+; ZU-NEXT: andl $511, %r10d # imm = 0x1FF
+; ZU-NEXT: orq %r14, %r10
+; ZU-NEXT: movq %r10, 72(%rax)
+; ZU-NEXT: shlq $20, %r9
+; ZU-NEXT: andl $1048575, %r11d # imm = 0xFFFFF
+; ZU-NEXT: orq %r9, %r11
+; ZU-NEXT: movq %r11, 56(%rax)
+; ZU-NEXT: shlq $31, %r8
+; ZU-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF
+; ZU-NEXT: orq %r8, %rcx
+; ZU-NEXT: movq %rcx, 40(%rax)
+; ZU-NEXT: movq %rsi, %xmm1
+; ZU-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; ZU-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
+; ZU-NEXT: movq %xmm0, %rcx
+; ZU-NEXT: andq %r12, %rcx
+; ZU-NEXT: shlq $53, %rdx
+; ZU-NEXT: orq %rcx, %rdx
+; ZU-NEXT: movq %rdx, 8(%rax)
+; ZU-NEXT: popq %rbx
+; ZU-NEXT: popq %r12
+; ZU-NEXT: popq %r13
+; ZU-NEXT: popq %r14
+; ZU-NEXT: popq %r15
+; ZU-NEXT: popq %rbp
+; ZU-NEXT: retq
+;
; X86-LABEL: scmp_uncommon_vectors:
; X86: # %bb.0:
; X86-NEXT: pushl %ebp
@@ -2427,6 +2969,18 @@ define <1 x i3> @scmp_scalarize(<1 x i33> %x, <1 x i33> %y) nounwind {
; X64-NEXT: subb %cl, %al
; X64-NEXT: retq
;
+; ZU-LABEL: scmp_scalarize:
+; ZU: # %bb.0:
+; ZU-NEXT: shlq $31, %rsi
+; ZU-NEXT: sarq $31, %rsi
+; ZU-NEXT: shlq $31, %rdi
+; ZU-NEXT: sarq $31, %rdi
+; ZU-NEXT: cmpq %rsi, %rdi
+; ZU-NEXT: setzul %cl
+; ZU-NEXT: setzug %al
+; ZU-NEXT: subb %cl, %al
+; ZU-NEXT: retq
+;
; X86-LABEL: scmp_scalarize:
; X86: # %bb.0:
; X86-NEXT: pushl %ebx
@@ -2574,6 +3128,37 @@ define <2 x i8> @scmp_bool_operands(<2 x i1> %x, <2 x i1> %y) nounwind {
; AVX512-NEXT: vpinsrb $1, %ecx, %xmm0, %xmm0
; AVX512-NEXT: retq
;
+; ZU-LABEL: scmp_bool_operands:
+; ZU: # %bb.0:
+; ZU-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp)
+; ZU-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
+; ZU-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
+; ZU-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
+; ZU-NEXT: andb $1, %al
+; ZU-NEXT: negb %al
+; ZU-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
+; ZU-NEXT: movzbl -{{[0-9]+}}(%rsp), %esi
+; ZU-NEXT: andb $1, %dl
+; ZU-NEXT: negb %dl
+; ZU-NEXT: cmpb %al, %dl
+; ZU-NEXT: setzul %al
+; ZU-NEXT: setzug %dl
+; ZU-NEXT: subb %al, %dl
+; ZU-NEXT: movzbl %dl, %eax
+; ZU-NEXT: andb $1, %cl
+; ZU-NEXT: negb %cl
+; ZU-NEXT: andb $1, %sil
+; ZU-NEXT: negb %sil
+; ZU-NEXT: cmpb %cl, %sil
+; ZU-NEXT: setzul %cl
+; ZU-NEXT: setzug %dl
+; ZU-NEXT: subb %cl, %dl
+; ZU-NEXT: movzbl %dl, %ecx
+; ZU-NEXT: shll $8, %ecx
+; ZU-NEXT: orl %eax, %ecx
+; ZU-NEXT: movd %ecx, %xmm0
+; ZU-NEXT: retq
+;
; X86-LABEL: scmp_bool_operands:
; X86: # %bb.0:
; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
@@ -2664,6 +3249,28 @@ define <2 x i16> @scmp_ret_wider_than_operands(<2 x i8> %x, <2 x i8> %y) nounwin
; AVX-NEXT: vpinsrw $1, %eax, %xmm0, %xmm0
; AVX-NEXT: retq
;
+; ZU-LABEL: scmp_ret_wider_than_operands:
+; ZU: # %bb.0:
+; ZU-NEXT: movd %xmm1, %eax
+; ZU-NEXT: movl %eax, %ecx
+; ZU-NEXT: shrl $8, %ecx
+; ZU-NEXT: movd %xmm0, %edx
+; ZU-NEXT: movl %edx, %esi
+; ZU-NEXT: shrl $8, %esi
+; ZU-NEXT: cmpb %cl, %sil
+; ZU-NEXT: setzul %cl
+; ZU-NEXT: setzug %sil
+; ZU-NEXT: subb %cl, %sil
+; ZU-NEXT: movsbl %sil, %ecx
+; ZU-NEXT: cmpb %al, %dl
+; ZU-NEXT: setzul %al
+; ZU-NEXT: setzug %dl
+; ZU-NEXT: subb %al, %dl
+; ZU-NEXT: movsbl %dl, %eax
+; ZU-NEXT: movd %eax, %xmm0
+; ZU-NEXT: pinsrw $1, %ecx, %xmm0
+; ZU-NEXT: retq
+;
; X86-LABEL: scmp_ret_wider_than_operands:
; X86: # %bb.0:
; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
diff --git a/llvm/test/CodeGen/X86/select_const_i128.ll b/llvm/test/CodeGen/X86/select_const_i128.ll
index a464a1048d145..347935dd0430f 100644
--- a/llvm/test/CodeGen/X86/select_const_i128.ll
+++ b/llvm/test/CodeGen/X86/select_const_i128.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v2 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v2 -mattr=+ndd | FileCheck --check-prefix=NDD %s
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v2 -mattr=+ndd,+zu | FileCheck --check-prefix=NDD-ZU %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v2 -mattr=+zu | FileCheck --check-prefix=ZU %s
define i128 @select_eq_i128(ptr %a) {
; CHECK-LABEL: select_eq_i128:
@@ -20,24 +20,24 @@ define i128 @select_eq_i128(ptr %a) {
; NDD: # %bb.0:
; NDD-NEXT: movdqa (%rdi), %xmm0
; NDD-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; NDD-NEXT: xorl %eax, %eax
; NDD-NEXT: ptest %xmm0, %xmm0
-; NDD-NEXT: setzune %al
-; NDD-NEXT: movzbl %al, %eax
+; NDD-NEXT: setne %al
; NDD-NEXT: addq $-1, %rax
; NDD-NEXT: movabsq $9223372036854775807, %rdx # imm = 0x7FFFFFFFFFFFFFFF
; NDD-NEXT: adcq $0, %rdx
; NDD-NEXT: retq
;
-; NDD-ZU-LABEL: select_eq_i128:
-; NDD-ZU: # %bb.0:
-; NDD-ZU-NEXT: movdqa (%rdi), %xmm0
-; NDD-ZU-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; NDD-ZU-NEXT: ptest %xmm0, %xmm0
-; NDD-ZU-NEXT: setzune %al
-; NDD-ZU-NEXT: addq $-1, %rax
-; NDD-ZU-NEXT: movabsq $9223372036854775807, %rdx # imm = 0x7FFFFFFFFFFFFFFF
-; NDD-ZU-NEXT: adcq $0, %rdx
-; NDD-ZU-NEXT: retq
+; ZU-LABEL: select_eq_i128:
+; ZU: # %bb.0:
+; ZU-NEXT: movdqa (%rdi), %xmm0
+; ZU-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; ZU-NEXT: ptest %xmm0, %xmm0
+; ZU-NEXT: setzune %al
+; ZU-NEXT: addq $-1, %rax
+; ZU-NEXT: movabsq $9223372036854775807, %rdx # imm = 0x7FFFFFFFFFFFFFFF
+; ZU-NEXT: adcq $0, %rdx
+; ZU-NEXT: retq
%1 = load i128, ptr %a, align 16
%cmp = icmp eq i128 %1, 1
%cond = select i1 %cmp, i128 170141183460469231731687303715884105727, i128 -170141183460469231731687303715884105728
>From 17bd9242a2cecc76ae54764e14be4974e4f520c0 Mon Sep 17 00:00:00 2001
From: Feng Zou <feng.zou at intel.com>
Date: Fri, 13 Jun 2025 15:53:31 +0800
Subject: [PATCH 6/6] Revert the change in memfold-nd2rmw.mir
---
llvm/test/CodeGen/X86/apx/memfold-nd2rmw.mir | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/X86/apx/memfold-nd2rmw.mir b/llvm/test/CodeGen/X86/apx/memfold-nd2rmw.mir
index 4f00076b92a4d..54e140686876f 100644
--- a/llvm/test/CodeGen/X86/apx/memfold-nd2rmw.mir
+++ b/llvm/test/CodeGen/X86/apx/memfold-nd2rmw.mir
@@ -4,7 +4,7 @@
# below show be morphed into an ADD32mi by the register allocator, making it
# load-operate-store to %stack.2.
#
-# CHECK: MOV32mi %stack.2
+# CHECK: ADD32mi %stack.2
--- |
define fastcc void @add32ri_nd_2_add32mi(i1 %arg, i1 %arg1, i1 %arg2, ptr %arg3, ptr %arg4, i1 %arg5, i8 %arg6) #0 {
More information about the llvm-commits
mailing list