[llvm] [TableGen] Avoid evaluating RHS of a BinOp until short-circuit is complete (PR #144021)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-tablegen

Author: Min-Yih Hsu (mshockwave)

<details>
<summary>Changes</summary>

This patch adds an even more aggressive short-circuit on `!and` and `!or` that completely avoids the evaluation of RHS operand until short circuiting decisions are made.

-----
Context: https://discourse.llvm.org/t/how-to-do-short-circuit-evaluation-in-tablegen/86847

---
Full diff: https://github.com/llvm/llvm-project/pull/144021.diff


2 Files Affected:

- (modified) llvm/lib/TableGen/Record.cpp (+2-1) 
- (modified) llvm/test/TableGen/true-false.td (+7-2) 


``````````diff
diff --git a/llvm/lib/TableGen/Record.cpp b/llvm/lib/TableGen/Record.cpp
index 4c8b41237c604..d0bf8323511c2 100644
--- a/llvm/lib/TableGen/Record.cpp
+++ b/llvm/lib/TableGen/Record.cpp
@@ -1558,7 +1558,6 @@ const Init *BinOpInit::Fold(const Record *CurRec) const {
 
 const Init *BinOpInit::resolveReferences(Resolver &R) const {
   const Init *lhs = LHS->resolveReferences(R);
-  const Init *rhs = RHS->resolveReferences(R);
 
   unsigned Opc = getOpcode();
   if (Opc == AND || Opc == OR) {
@@ -1577,6 +1576,8 @@ const Init *BinOpInit::resolveReferences(Resolver &R) const {
     }
   }
 
+  const Init *rhs = RHS->resolveReferences(R);
+
   if (LHS != lhs || RHS != rhs)
     return (BinOpInit::get(getOpcode(), lhs, rhs, getType()))
         ->Fold(R.getCurrentRecord());
diff --git a/llvm/test/TableGen/true-false.td b/llvm/test/TableGen/true-false.td
index 5a59f20b21d25..8a1949327e610 100644
--- a/llvm/test/TableGen/true-false.td
+++ b/llvm/test/TableGen/true-false.td
@@ -67,13 +67,18 @@ def rec7 {
   bits<3> flags = { true, false, true };
 }
 
-// `!and` and `!or` should be short-circuit such that `!tail` on empty list will never
-// be evaluated.
+// `!and` and `!or` should be short-circuit such that any of the `!head` or
+// `!tail` on empty list below will never be evaluated.
 // CHECK: def rec8
+// CHECK:   bit v = 0;
+// CHECK:   int v2 = -1;
 // CHECK:   list<int> newSeq = [];
 // CHECK:   list<int> newSeq2 = [];
 
 class Foo <list<int> seq = []> {
+  bit v = !and(false, !head(seq));
+  int v2 = !or(-1, !head(seq));
+
   bit unresolved = !ne(!find(NAME, "BAR"), -1);
   list<int> newSeq  = !if(!and(false, unresolved), !tail(seq), seq);
   list<int> newSeq2 = !if(!or(-1, unresolved), seq, !tail(seq));

``````````

</details>


https://github.com/llvm/llvm-project/pull/144021