[llvm] [AMDGPU][AsmParser] Support true16 register suffix for valid register range (PR #143997)
Shilei Tian via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 12 21:21:05 PDT 2025
https://github.com/shiltian updated https://github.com/llvm/llvm-project/pull/143997
>From cc0d0d0093c6375c5aad4b9e19f1ef74ef3a0240 Mon Sep 17 00:00:00 2001
From: Shilei Tian <i at tianshilei.me>
Date: Thu, 12 Jun 2025 19:49:40 -0400
Subject: [PATCH 1/2] [AMDGPU][AsmParser] Support true16 register suffix for
valid register range
`v[5].l` and `v[5:5].h` are acceptable operand, because `v[5]` and `v[5:5]` are
accepted. This PR adds the support for it.
---
.../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 23 ++++++++++++++++---
llvm/test/MC/AMDGPU/gfx11_asm_vop1.s | 6 +++++
llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s | 6 +++++
3 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index b43876582daa8..bfd2e2ce8d467 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1395,7 +1395,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
MCRegister ParseRegList(RegisterKind &RegKind, unsigned &RegNum,
unsigned &RegWidth,
SmallVectorImpl<AsmToken> &Tokens);
- bool ParseRegRange(unsigned& Num, unsigned& Width);
+ bool ParseRegRange(unsigned &Num, unsigned &Width, unsigned &SubReg);
MCRegister getRegularReg(RegisterKind RegKind, unsigned RegNum,
unsigned SubReg, unsigned RegWidth, SMLoc Loc);
@@ -2857,7 +2857,8 @@ MCRegister AMDGPUAsmParser::getRegularReg(RegisterKind RegKind, unsigned RegNum,
return Reg;
}
-bool AMDGPUAsmParser::ParseRegRange(unsigned &Num, unsigned &RegWidth) {
+bool AMDGPUAsmParser::ParseRegRange(unsigned &Num, unsigned &RegWidth,
+ unsigned &SubReg) {
int64_t RegLo, RegHi;
if (!skipToken(AsmToken::LBrac, "missing register index"))
return false;
@@ -2894,8 +2895,24 @@ bool AMDGPUAsmParser::ParseRegRange(unsigned &Num, unsigned &RegWidth) {
return false;
}
+ if (RegHi == RegLo) {
+ StringRef RegSuffix;
+ SMLoc RegSuffixLoc = getLoc();
+ if (parseId(RegSuffix)) {
+ if (RegSuffix.consume_back(".l")) {
+ SubReg = AMDGPU::lo16;
+ } else if (RegSuffix.consume_back(".h")) {
+ SubReg = AMDGPU::hi16;
+ } else {
+ Error(RegSuffixLoc, "invalid register suffix");
+ return false;
+ }
+ }
+ }
+
Num = static_cast<unsigned>(RegLo);
RegWidth = 32 * ((RegHi - RegLo) + 1);
+
return true;
}
@@ -2949,7 +2966,7 @@ MCRegister AMDGPUAsmParser::ParseRegularReg(RegisterKind &RegKind,
RegWidth = 32;
} else {
// Range of registers: v[XX:YY]. ":YY" is optional.
- if (!ParseRegRange(RegNum, RegWidth))
+ if (!ParseRegRange(RegNum, RegWidth, SubReg))
return MCRegister();
}
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop1.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop1.s
index 93e01954bea55..f1438532d7c5e 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop1.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop1.s
@@ -3808,3 +3808,9 @@ v_trunc_f64 v[5:6], src_scc
v_trunc_f64 v[254:255], 0xaf123456
// GFX11: v_trunc_f64_e32 v[254:255], 0xaf123456 ; encoding: [0xff,0x2e,0xfc,0x7f,0x56,0x34,0x12,0xaf]
+
+v_trunc_f16 v[5].l, v[1].h
+// GFX11: v_trunc_f16_e32 v5.l, v1.h ; encoding: [0x81,0xbb,0x0a,0x7e]
+
+v_trunc_f16 v[5:5].l, v[1:1].h
+// GFX11: v_trunc_f16_e32 v5.l, v1.h ; encoding: [0x81,0xbb,0x0a,0x7e]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
index 55a25ad3ec81b..54d10271b6699 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
@@ -1231,3 +1231,9 @@ v_trunc_f16_e32 v5.l, v199.l dpp8:[7,6,5,4,3,2,1,0]
v_trunc_f16_e32 v5.l, v199.l quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:23: error: invalid operand for instruction
+
+v_ceil_f16_e32 v[5:5].s, 0xfe0b
+// GFX11: :[[@LINE-1]]:22: error: invalid register suffix
+
+v_ceil_f16_e32 v[6:7].l, 0xfe0b
+// GFX11: :[[@LINE-1]]:16: error: invalid operand for instruction
>From 59dfc5d052390edcc0b0288bfd8d026f96842674 Mon Sep 17 00:00:00 2001
From: Shilei Tian <i at tianshilei.me>
Date: Fri, 13 Jun 2025 00:20:29 -0400
Subject: [PATCH 2/2] fixup! [AMDGPU][AsmParser] Support true16 register suffix
for valid register range
---
.../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 18 +++++++-----------
llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s | 2 +-
2 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index bfd2e2ce8d467..0dc1d13773229 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -2896,17 +2896,13 @@ bool AMDGPUAsmParser::ParseRegRange(unsigned &Num, unsigned &RegWidth,
}
if (RegHi == RegLo) {
- StringRef RegSuffix;
- SMLoc RegSuffixLoc = getLoc();
- if (parseId(RegSuffix)) {
- if (RegSuffix.consume_back(".l")) {
- SubReg = AMDGPU::lo16;
- } else if (RegSuffix.consume_back(".h")) {
- SubReg = AMDGPU::hi16;
- } else {
- Error(RegSuffixLoc, "invalid register suffix");
- return false;
- }
+ StringRef RegSuffix = getTokenStr();
+ if (RegSuffix == ".l") {
+ SubReg = AMDGPU::lo16;
+ lex();
+ } else if (RegSuffix == ".h") {
+ SubReg = AMDGPU::hi16;
+ lex();
}
}
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
index 54d10271b6699..d19220867f29f 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
@@ -1233,7 +1233,7 @@ v_trunc_f16_e32 v5.l, v199.l quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:23: error: invalid operand for instruction
v_ceil_f16_e32 v[5:5].s, 0xfe0b
-// GFX11: :[[@LINE-1]]:22: error: invalid register suffix
+// GFX11: :[[@LINE-1]]:22: error: invalid operand for instruction
v_ceil_f16_e32 v[6:7].l, 0xfe0b
// GFX11: :[[@LINE-1]]:16: error: invalid operand for instruction
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