[llvm] [Xtensa] Implement Xtensa Floating Point Option. (PR #136086)

[Andrei Safronov via llvm-commits]

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@@ -113,6 +113,36 @@ static DecodeStatus DecodeMR23RegisterClass(MCInst &Inst, uint64_t RegNo,
   return MCDisassembler::Success;
 }
 
+static const MCPhysReg FPRDecoderTable[] = {
+    Xtensa::F0,  Xtensa::F1,  Xtensa::F2,  Xtensa::F3, Xtensa::F4,  Xtensa::F5,
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andreisfr wrote:

Thank you very much for comments! Fixed. I used the sequential register property in this case, and I've used it to simplify register decoding in several other places.

https://github.com/llvm/llvm-project/pull/136086