[llvm] [X86] X86FixupInstTuning - extend BLENDPD/S -> MOVSD/S handling to SSE variant (PR #143961)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 12 13:10:17 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-x86
Author: Simon Pilgrim (RKSimon)
<details>
<summary>Changes</summary>
CC @<!-- -->houngkoungting
---
Patch is 28.81 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/143961.diff
15 Files Affected:
- (modified) llvm/lib/Target/X86/X86FixupInstTuning.cpp (+8-2)
- (modified) llvm/test/CodeGen/X86/combine-and.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/combine-or-shuffle.ll (+8-18)
- (modified) llvm/test/CodeGen/X86/insertelement-zero.ll (+2-2)
- (modified) llvm/test/CodeGen/X86/masked_expandload.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/masked_load.ll (+2-2)
- (modified) llvm/test/CodeGen/X86/sse-insertelt-from-mem.ll (+5-11)
- (modified) llvm/test/CodeGen/X86/sse-insertelt.ll (+4-9)
- (modified) llvm/test/CodeGen/X86/sse-scalar-fp-arith.ll (+48-96)
- (modified) llvm/test/CodeGen/X86/sse41.ll (+3-3)
- (modified) llvm/test/CodeGen/X86/vec_floor.ll (+16-16)
- (modified) llvm/test/CodeGen/X86/vector-shuffle-128-v2.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/vector-shuffle-combining-ssse3.ll (+4-9)
- (modified) llvm/test/CodeGen/X86/vector-zmov.ll (+9-23)
- (modified) llvm/test/CodeGen/X86/vselect.ll (+8-18)
``````````diff
diff --git a/llvm/lib/Target/X86/X86FixupInstTuning.cpp b/llvm/lib/Target/X86/X86FixupInstTuning.cpp
index fd13305d8a73d..be0a8c23ea5c4 100644
--- a/llvm/lib/Target/X86/X86FixupInstTuning.cpp
+++ b/llvm/lib/Target/X86/X86FixupInstTuning.cpp
@@ -234,10 +234,16 @@ bool X86FixupInstTuningPass::processInstruction(
};
switch (Opc) {
- case X86::VBLENDPSrri:
- return ProcessBLENDToMOV(X86::VMOVSSrr);
+ case X86::BLENDPDrri:
+ return ProcessBLENDToMOV(X86::MOVSDrr);
case X86::VBLENDPDrri:
return ProcessBLENDToMOV(X86::VMOVSDrr);
+
+ case X86::BLENDPSrri:
+ return ProcessBLENDToMOV(X86::MOVSSrr);
+ case X86::VBLENDPSrri:
+ return ProcessBLENDToMOV(X86::VMOVSSrr);
+
case X86::VPERMILPDri:
return ProcessVPERMILPDri(X86::VSHUFPDrri);
case X86::VPERMILPDYri:
diff --git a/llvm/test/CodeGen/X86/combine-and.ll b/llvm/test/CodeGen/X86/combine-and.ll
index 173457ff46677..9ca4ebfec2774 100644
--- a/llvm/test/CodeGen/X86/combine-and.ll
+++ b/llvm/test/CodeGen/X86/combine-and.ll
@@ -189,7 +189,7 @@ define <4 x i32> @test11(<4 x i32> %A) {
; SSE-LABEL: test11:
; SSE: # %bb.0:
; SSE-NEXT: xorps %xmm1, %xmm1
-; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
+; SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
; SSE-NEXT: retq
;
; AVX-LABEL: test11:
diff --git a/llvm/test/CodeGen/X86/combine-or-shuffle.ll b/llvm/test/CodeGen/X86/combine-or-shuffle.ll
index 2b5f09113ca68..2f2a05fa6939b 100644
--- a/llvm/test/CodeGen/X86/combine-or-shuffle.ll
+++ b/llvm/test/CodeGen/X86/combine-or-shuffle.ll
@@ -108,15 +108,10 @@ define <4 x i32> @test4(<4 x i32> %a, <4 x i32> %b) {
define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b) {
-; SSE2-LABEL: test5:
-; SSE2: # %bb.0:
-; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
-; SSE2-NEXT: retq
-;
-; SSE4-LABEL: test5:
-; SSE4: # %bb.0:
-; SSE4-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
-; SSE4-NEXT: retq
+; SSE-LABEL: test5:
+; SSE: # %bb.0:
+; SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
+; SSE-NEXT: retq
;
; AVX1-LABEL: test5:
; AVX1: # %bb.0:
@@ -283,15 +278,10 @@ define <4 x i32> @test11(<4 x i32> %a, <4 x i32> %b) {
define <4 x i32> @test12(<4 x i32> %a, <4 x i32> %b) {
-; SSE2-LABEL: test12:
-; SSE2: # %bb.0:
-; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
-; SSE2-NEXT: retq
-;
-; SSE4-LABEL: test12:
-; SSE4: # %bb.0:
-; SSE4-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
-; SSE4-NEXT: retq
+; SSE-LABEL: test12:
+; SSE: # %bb.0:
+; SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
+; SSE-NEXT: retq
;
; AVX1-LABEL: test12:
; AVX1: # %bb.0:
diff --git a/llvm/test/CodeGen/X86/insertelement-zero.ll b/llvm/test/CodeGen/X86/insertelement-zero.ll
index 31551360be483..6036eddb0ca84 100644
--- a/llvm/test/CodeGen/X86/insertelement-zero.ll
+++ b/llvm/test/CodeGen/X86/insertelement-zero.ll
@@ -214,7 +214,7 @@ define <8 x float> @insert_v8f32_z12345z7(<8 x float> %a) {
; SSE41-LABEL: insert_v8f32_z12345z7:
; SSE41: # %bb.0:
; SSE41-NEXT: xorps %xmm2, %xmm2
-; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]
+; SSE41-NEXT: movss {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]
; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm1[0,1],xmm2[2],xmm1[3]
; SSE41-NEXT: retq
;
@@ -287,7 +287,7 @@ define <8 x i32> @insert_v8i32_z12345z7(<8 x i32> %a) {
; SSE41-LABEL: insert_v8i32_z12345z7:
; SSE41: # %bb.0:
; SSE41-NEXT: xorps %xmm2, %xmm2
-; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]
+; SSE41-NEXT: movss {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]
; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm1[0,1],xmm2[2],xmm1[3]
; SSE41-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/masked_expandload.ll b/llvm/test/CodeGen/X86/masked_expandload.ll
index b7fe8e053fa15..e81a983c07018 100644
--- a/llvm/test/CodeGen/X86/masked_expandload.ll
+++ b/llvm/test/CodeGen/X86/masked_expandload.ll
@@ -1097,7 +1097,7 @@ define <2 x float> @expandload_v2f32_v2i1(ptr %base, <2 x float> %src0, <2 x i32
; SSE42-NEXT: retq
; SSE42-NEXT: LBB4_1: ## %cond.load
; SSE42-NEXT: movss (%rdi), %xmm1 ## xmm1 = mem[0],zero,zero,zero
-; SSE42-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
+; SSE42-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
; SSE42-NEXT: addq $4, %rdi
; SSE42-NEXT: testb $2, %al
; SSE42-NEXT: je LBB4_4
diff --git a/llvm/test/CodeGen/X86/masked_load.ll b/llvm/test/CodeGen/X86/masked_load.ll
index e2e26da95b874..37ab4276fbcca 100644
--- a/llvm/test/CodeGen/X86/masked_load.ll
+++ b/llvm/test/CodeGen/X86/masked_load.ll
@@ -817,7 +817,7 @@ define <2 x float> @load_v2f32_v2i32(<2 x i32> %trigger, ptr %addr, <2 x float>
; SSE42-NEXT: retq
; SSE42-NEXT: LBB7_1: ## %cond.load
; SSE42-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; SSE42-NEXT: blendps {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
+; SSE42-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
; SSE42-NEXT: testb $2, %al
; SSE42-NEXT: je LBB7_4
; SSE42-NEXT: LBB7_3: ## %cond.load1
@@ -1220,7 +1220,7 @@ define <8 x float> @load_v8f32_v8i1_zero(<8 x i1> %mask, ptr %addr) {
; SSE42-NEXT: je LBB10_10
; SSE42-NEXT: LBB10_9: ## %cond.load10
; SSE42-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
-; SSE42-NEXT: blendps {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3]
+; SSE42-NEXT: movss {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3]
; SSE42-NEXT: testb $32, %al
; SSE42-NEXT: je LBB10_12
; SSE42-NEXT: LBB10_11: ## %cond.load13
diff --git a/llvm/test/CodeGen/X86/sse-insertelt-from-mem.ll b/llvm/test/CodeGen/X86/sse-insertelt-from-mem.ll
index 5ae9055835716..1c3cfd079e9e9 100644
--- a/llvm/test/CodeGen/X86/sse-insertelt-from-mem.ll
+++ b/llvm/test/CodeGen/X86/sse-insertelt-from-mem.ll
@@ -7,17 +7,11 @@
; 0'th element insertion into an SSE register.
define <4 x float> @insert_f32_firstelt(<4 x float> %x, ptr %s.addr) {
-; SSE2-LABEL: insert_f32_firstelt:
-; SSE2: # %bb.0:
-; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
-; SSE2-NEXT: retq
-;
-; SSE41-LABEL: insert_f32_firstelt:
-; SSE41: # %bb.0:
-; SSE41-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
-; SSE41-NEXT: retq
+; SSE-LABEL: insert_f32_firstelt:
+; SSE: # %bb.0:
+; SSE-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
+; SSE-NEXT: retq
;
; AVX-LABEL: insert_f32_firstelt:
; AVX: # %bb.0:
diff --git a/llvm/test/CodeGen/X86/sse-insertelt.ll b/llvm/test/CodeGen/X86/sse-insertelt.ll
index 1e4fe81abc136..f174eaaca38c2 100644
--- a/llvm/test/CodeGen/X86/sse-insertelt.ll
+++ b/llvm/test/CodeGen/X86/sse-insertelt.ll
@@ -7,15 +7,10 @@
; 0'th element insertion into an SSE register.
define <4 x float> @insert_f32_firstelt(<4 x float> %x, float %s) {
-; SSE2-LABEL: insert_f32_firstelt:
-; SSE2: # %bb.0:
-; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
-; SSE2-NEXT: retq
-;
-; SSE41-LABEL: insert_f32_firstelt:
-; SSE41: # %bb.0:
-; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
-; SSE41-NEXT: retq
+; SSE-LABEL: insert_f32_firstelt:
+; SSE: # %bb.0:
+; SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
+; SSE-NEXT: retq
;
; AVX-LABEL: insert_f32_firstelt:
; AVX: # %bb.0:
diff --git a/llvm/test/CodeGen/X86/sse-scalar-fp-arith.ll b/llvm/test/CodeGen/X86/sse-scalar-fp-arith.ll
index 006c3006350cc..12bfb8d4fc9cf 100644
--- a/llvm/test/CodeGen/X86/sse-scalar-fp-arith.ll
+++ b/llvm/test/CodeGen/X86/sse-scalar-fp-arith.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,X86-SSE,SSE2,X86-SSE2
-; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,X86-SSE,SSE41,X86-SSE41
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,X86-SSE,X86-SSE2
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,X86-SSE,X86-SSE41
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,X86-AVX,X86-AVX1
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=AVX,X86-AVX,X86-AVX512
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,X64-SSE,SSE2,X64-SSE2
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,X64-SSE,SSE41,X64-SSE41
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,X64-SSE,X64-SSE2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,X64-SSE,X64-SSE41
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,X64-AVX,X64-AVX1
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=AVX,X64-AVX,X64-AVX512
@@ -1150,17 +1150,11 @@ define <4 x float> @insert_test5_add_ss(<4 x float> %a, <4 x float> %b) {
}
define <4 x float> @insert_test5_sub_ss(<4 x float> %a, <4 x float> %b) {
-; SSE2-LABEL: insert_test5_sub_ss:
-; SSE2: # %bb.0:
-; SSE2-NEXT: subps %xmm0, %xmm1
-; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
-; SSE2-NEXT: ret{{[l|q]}}
-;
-; SSE41-LABEL: insert_test5_sub_ss:
-; SSE41: # %bb.0:
-; SSE41-NEXT: subps %xmm0, %xmm1
-; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
-; SSE41-NEXT: ret{{[l|q]}}
+; SSE-LABEL: insert_test5_sub_ss:
+; SSE: # %bb.0:
+; SSE-NEXT: subps %xmm0, %xmm1
+; SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
+; SSE-NEXT: ret{{[l|q]}}
;
; AVX-LABEL: insert_test5_sub_ss:
; AVX: # %bb.0:
@@ -1188,17 +1182,11 @@ define <4 x float> @insert_test5_mul_ss(<4 x float> %a, <4 x float> %b) {
}
define <4 x float> @insert_test5_div_ss(<4 x float> %a, <4 x float> %b) {
-; SSE2-LABEL: insert_test5_div_ss:
-; SSE2: # %bb.0:
-; SSE2-NEXT: divps %xmm0, %xmm1
-; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
-; SSE2-NEXT: ret{{[l|q]}}
-;
-; SSE41-LABEL: insert_test5_div_ss:
-; SSE41: # %bb.0:
-; SSE41-NEXT: divps %xmm0, %xmm1
-; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
-; SSE41-NEXT: ret{{[l|q]}}
+; SSE-LABEL: insert_test5_div_ss:
+; SSE: # %bb.0:
+; SSE-NEXT: divps %xmm0, %xmm1
+; SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
+; SSE-NEXT: ret{{[l|q]}}
;
; AVX-LABEL: insert_test5_div_ss:
; AVX: # %bb.0:
@@ -1226,17 +1214,11 @@ define <2 x double> @insert_test5_add_sd(<2 x double> %a, <2 x double> %b) {
}
define <2 x double> @insert_test5_sub_sd(<2 x double> %a, <2 x double> %b) {
-; SSE2-LABEL: insert_test5_sub_sd:
-; SSE2: # %bb.0:
-; SSE2-NEXT: subpd %xmm0, %xmm1
-; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
-; SSE2-NEXT: ret{{[l|q]}}
-;
-; SSE41-LABEL: insert_test5_sub_sd:
-; SSE41: # %bb.0:
-; SSE41-NEXT: subpd %xmm0, %xmm1
-; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
-; SSE41-NEXT: ret{{[l|q]}}
+; SSE-LABEL: insert_test5_sub_sd:
+; SSE: # %bb.0:
+; SSE-NEXT: subpd %xmm0, %xmm1
+; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
+; SSE-NEXT: ret{{[l|q]}}
;
; AVX-LABEL: insert_test5_sub_sd:
; AVX: # %bb.0:
@@ -1264,17 +1246,11 @@ define <2 x double> @insert_test5_mul_sd(<2 x double> %a, <2 x double> %b) {
}
define <2 x double> @insert_test5_div_sd(<2 x double> %a, <2 x double> %b) {
-; SSE2-LABEL: insert_test5_div_sd:
-; SSE2: # %bb.0:
-; SSE2-NEXT: divpd %xmm0, %xmm1
-; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
-; SSE2-NEXT: ret{{[l|q]}}
-;
-; SSE41-LABEL: insert_test5_div_sd:
-; SSE41: # %bb.0:
-; SSE41-NEXT: divpd %xmm0, %xmm1
-; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
-; SSE41-NEXT: ret{{[l|q]}}
+; SSE-LABEL: insert_test5_div_sd:
+; SSE: # %bb.0:
+; SSE-NEXT: divpd %xmm0, %xmm1
+; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
+; SSE-NEXT: ret{{[l|q]}}
;
; AVX-LABEL: insert_test5_div_sd:
; AVX: # %bb.0:
@@ -1287,29 +1263,17 @@ define <2 x double> @insert_test5_div_sd(<2 x double> %a, <2 x double> %b) {
}
define <4 x float> @add_ss_mask(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) {
-; X86-SSE2-LABEL: add_ss_mask:
-; X86-SSE2: # %bb.0:
-; X86-SSE2-NEXT: testb $1, {{[0-9]+}}(%esp)
-; X86-SSE2-NEXT: jne .LBB70_1
-; X86-SSE2-NEXT: # %bb.2:
-; X86-SSE2-NEXT: movss {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]
-; X86-SSE2-NEXT: retl
-; X86-SSE2-NEXT: .LBB70_1:
-; X86-SSE2-NEXT: addss %xmm0, %xmm1
-; X86-SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
-; X86-SSE2-NEXT: retl
-;
-; X86-SSE41-LABEL: add_ss_mask:
-; X86-SSE41: # %bb.0:
-; X86-SSE41-NEXT: testb $1, {{[0-9]+}}(%esp)
-; X86-SSE41-NEXT: jne .LBB70_1
-; X86-SSE41-NEXT: # %bb.2:
-; X86-SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]
-; X86-SSE41-NEXT: retl
-; X86-SSE41-NEXT: .LBB70_1:
-; X86-SSE41-NEXT: addss %xmm0, %xmm1
-; X86-SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
-; X86-SSE41-NEXT: retl
+; X86-SSE-LABEL: add_ss_mask:
+; X86-SSE: # %bb.0:
+; X86-SSE-NEXT: testb $1, {{[0-9]+}}(%esp)
+; X86-SSE-NEXT: jne .LBB70_1
+; X86-SSE-NEXT: # %bb.2:
+; X86-SSE-NEXT: movss {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]
+; X86-SSE-NEXT: retl
+; X86-SSE-NEXT: .LBB70_1:
+; X86-SSE-NEXT: addss %xmm0, %xmm1
+; X86-SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
+; X86-SSE-NEXT: retl
;
; X86-AVX1-LABEL: add_ss_mask:
; X86-AVX1: # %bb.0:
@@ -1329,29 +1293,17 @@ define <4 x float> @add_ss_mask(<4 x float> %a, <4 x float> %b, <4 x float> %c,
; X86-AVX512-NEXT: vmovaps %xmm2, %xmm0
; X86-AVX512-NEXT: retl
;
-; X64-SSE2-LABEL: add_ss_mask:
-; X64-SSE2: # %bb.0:
-; X64-SSE2-NEXT: testb $1, %dil
-; X64-SSE2-NEXT: jne .LBB70_1
-; X64-SSE2-NEXT: # %bb.2:
-; X64-SSE2-NEXT: movss {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]
-; X64-SSE2-NEXT: retq
-; X64-SSE2-NEXT: .LBB70_1:
-; X64-SSE2-NEXT: addss %xmm0, %xmm1
-; X64-SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
-; X64-SSE2-NEXT: retq
-;
-; X64-SSE41-LABEL: add_ss_mask:
-; X64-SSE41: # %bb.0:
-; X64-SSE41-NEXT: testb $1, %dil
-; X64-SSE41-NEXT: jne .LBB70_1
-; X64-SSE41-NEXT: # %bb.2:
-; X64-SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]
-; X64-SSE41-NEXT: retq
-; X64-SSE41-NEXT: .LBB70_1:
-; X64-SSE41-NEXT: addss %xmm0, %xmm1
-; X64-SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
-; X64-SSE41-NEXT: retq
+; X64-SSE-LABEL: add_ss_mask:
+; X64-SSE: # %bb.0:
+; X64-SSE-NEXT: testb $1, %dil
+; X64-SSE-NEXT: jne .LBB70_1
+; X64-SSE-NEXT: # %bb.2:
+; X64-SSE-NEXT: movss {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]
+; X64-SSE-NEXT: retq
+; X64-SSE-NEXT: .LBB70_1:
+; X64-SSE-NEXT: addss %xmm0, %xmm1
+; X64-SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
+; X64-SSE-NEXT: retq
;
; X64-AVX1-LABEL: add_ss_mask:
; X64-AVX1: # %bb.0:
@@ -1402,7 +1354,7 @@ define <2 x double> @add_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double>
; X86-SSE41-NEXT: retl
; X86-SSE41-NEXT: .LBB71_1:
; X86-SSE41-NEXT: addsd %xmm0, %xmm1
-; X86-SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
+; X86-SSE41-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
; X86-SSE41-NEXT: retl
;
; X86-AVX1-LABEL: add_sd_mask:
@@ -1444,7 +1396,7 @@ define <2 x double> @add_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double>
; X64-SSE41-NEXT: retq
; X64-SSE41-NEXT: .LBB71_1:
; X64-SSE41-NEXT: addsd %xmm0, %xmm1
-; X64-SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
+; X64-SSE41-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
; X64-SSE41-NEXT: retq
;
; X64-AVX1-LABEL: add_sd_mask:
diff --git a/llvm/test/CodeGen/X86/sse41.ll b/llvm/test/CodeGen/X86/sse41.ll
index 53a10ab0c26ff..4f5b7ee0eaea0 100644
--- a/llvm/test/CodeGen/X86/sse41.ll
+++ b/llvm/test/CodeGen/X86/sse41.ll
@@ -345,7 +345,7 @@ define <4 x float> @blendps_not_insertps_1(<4 x float> %t1, float %t2) nounwind
; X86-SSE: ## %bb.0:
; X86-SSE-NEXT: movss {{[0-9]+}}(%esp), %xmm1 ## xmm1 = mem[0],zero,zero,zero
; X86-SSE-NEXT: ## encoding: [0xf3,0x0f,0x10,0x4c,0x24,0x04]
-; X86-SSE-NEXT: blendps $1, %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x0c,0xc1,0x01]
+; X86-SSE-NEXT: movss %xmm1, %xmm0 ## encoding: [0xf3,0x0f,0x10,0xc1]
; X86-SSE-NEXT: ## xmm0 = xmm1[0],xmm0[1,2,3]
; X86-SSE-NEXT: retl ## encoding: [0xc3]
;
@@ -367,7 +367,7 @@ define <4 x float> @blendps_not_insertps_1(<4 x float> %t1, float %t2) nounwind
;
; X64-SSE-LABEL: blendps_not_insertps_1:
; X64-SSE: ## %bb.0:
-; X64-SSE-NEXT: blendps $1, %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x0c,0xc1,0x01]
+; X64-SSE-NEXT: movss %xmm1, %xmm0 ## encoding: [0xf3,0x0f,0x10,0xc1]
; X64-SSE-NEXT: ## xmm0 = xmm1[0],xmm0[1,2,3]
; X64-SSE-NEXT: retq ## encoding: [0xc3]
;
@@ -434,7 +434,7 @@ define <4 x float> @insertps_or_blendps(<4 x float> %t1, float %t2) minsize noun
define <4 x float> @blendps_not_insertps_2(<4 x float> %t1, <4 x float> %t2) nounwind {
; SSE-LABEL: blendps_not_insertps_2:
; SSE: ## %bb.0:
-; SSE-NEXT: blendps $1, %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x0c,0xc1,0x01]
+; SSE-NEXT: movss %xmm1, %xmm0 ## encoding: [0xf3,0x0f,0x10,0xc1]
; SSE-NEXT: ## xmm0 = xmm1[0],xmm0[1,2,3]
; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
;
diff --git a/llvm/test/CodeGen/X86/vec_floor.ll b/llvm/test/CodeGen/X86/vec_floor.ll
index 0538cac12cbf7..1007969b6c6d1 100644
--- a/llvm/test/CodeGen/X86/vec_floor.ll
+++ b/llvm/test/CodeGen/X86/vec_floor.ll
@@ -1361,7 +1361,7 @@ define <4 x float> @floor_mask_ss(<4 x float> %x, <4 x float> %y, <4 x float> %w
; SSE41-NEXT: xorps %xmm2, %xmm2
; SSE41-NEXT: roundss $9, %xmm0, %xmm2
; SSE41-NEXT: LBB52_2:
-; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3]
+; SSE41-NEXT: movss {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3]
; SSE41-NEXT: movaps %xmm1, %xmm0
; SSE41-NEXT: retq
;
@@ -1402,7 +1402,7 @@ define <4 x float> @floor_maskz_ss(<4 x float> %x, <4 x float> %y, i8 %k) nounwi
; SSE41-NEXT: xorps %xmm2, %xmm2
; SSE41-NEXT: roundss $9, %xmm0, %xmm2
; SSE41-NEXT: LBB53_2:
-; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3]
+; SSE41-NEXT: movss {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3]
; SSE41-NEXT: movaps %xmm1, %xmm0
; SSE41-NEXT: retq
;
@@ -1441,7 +1441,7 @@ define <2 x double> @floor_mask_sd(<2 x double> %x, <2 x double> %y, <2 x double
; SSE41-NEXT: xorps %xmm2, %xmm2
; SSE41-NEXT: roundsd $9, %xmm0, %xmm2
; SSE41-NEXT: LBB54_2:
-; SSE41-NEXT: blendpd {{.*#+}} xmm1 = xmm2[0],xmm1[1]
+; SSE41-NEXT: movsd {{.*#+}} xmm1 = xmm2[0],xmm1[1]
; SSE41-NEXT: movapd %xmm1, %xmm0
; SSE41-NEXT: retq
;
@@ -1482,7 +1482,7 @@ define <2 x double> @floor_maskz_sd(<2 x double> %x, <2 x double> %y, i8 %k) nou
; SSE41-NEXT: xorps %xmm2, %xmm2
; SSE41-NEXT: roundsd $9, %xmm0, %xmm2
; SSE41-NEXT: LBB55_2:
-; SSE41-NEXT: blendpd {{.*#+}} xmm1 = xmm2[0],xmm1[1]
+; SSE41-NEXT: movsd {{.*#+}} xmm1 = xmm2[0],xmm1[1]
; SSE41-NEXT: movapd %xmm1, %xmm0
; SSE41-NEXT: retq
;
@@ -1521,7 +1521,7 @@ define <4 x float> @floor_mask_ss_trunc(<4 x float> %x, <4 x float> %y, <4 x flo
; SSE41-NEXT: xorps %xmm2, %xmm2
; SSE41-NEXT: roundss $9, %xmm0, %xmm2
; SSE41-NEXT: LBB56_2:
-; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3]
+; SSE41-NEXT: movss {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3]
; SSE41-NEXT: movaps %xmm1, %xmm0
; SSE41-NEXT: retq
;
@@ -1562,7 +1562,7 @@ define <4 x float> @floor_maskz_ss_trunc(<4 x float> %x, <4 x float> %y, i16 %k)
; SSE41-NEXT: LBB57_1:
; SSE41-NEXT: roundss $9, %xmm0, %xmm0
; SSE41-NEXT: LBB57_3:
-; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
+; SSE41-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
; SSE41-NEXT: movaps %xmm1, %xmm0
; SSE41-NEXT: retq
;
@@ -1602,7 +1602,7 @@ define <2 x double> @floor_mask_sd_trunc(<2 x double> %x, <2 x double> %y, <2 x
;...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/143961
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