[llvm] [RISCV] Save vector registers in interrupt handler. (PR #143808)

[Brandon Wu via llvm-commits]

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@@ -56,14 +56,44 @@ def CSR_XLEN_F32_Interrupt: CalleeSavedRegs<(add CSR_Interrupt,
 def CSR_XLEN_F64_Interrupt: CalleeSavedRegs<(add CSR_Interrupt,
                                              (sequence "F%u_D", 0, 31))>;
 
+// Same as CSR_Interrupt, but including all vector registers.
+def CSR_XLEN_V_Interrupt: CalleeSavedRegs<(add CSR_Interrupt,
+                                           (sequence "V%u", 0, 31))>;
+
+// Same as CSR_Interrupt, but including all 32-bit FP registers and all vector
+// registers.
+def CSR_XLEN_F32_V_Interrupt: CalleeSavedRegs<(add CSR_Interrupt,
+                                               (sequence "F%u_F", 0, 31),
+                                               (sequence "V%u", 0, 31))>;
+
+// Same as CSR_Interrupt, but including all 64-bit FP registers and all vector
+// registers.
+def CSR_XLEN_F64_V_Interrupt: CalleeSavedRegs<(add CSR_Interrupt,
+                                               (sequence "F%u_D", 0, 31),
+                                               (sequence "V%u", 0, 31))>;
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4vtomat wrote:

I think callee-saved register also have this issue when I change https://github.com/llvm/llvm-project/blob/4f60321ca183ebf132e97e54d8d560643c5c3340/llvm/test/CodeGen/RISCV/rvv/callee-saved-regs.ll#L89-L90 to only use `v24`, it uses `vs8r`.

https://github.com/llvm/llvm-project/pull/143808