[llvm] [SPIR-V] Fix ExecutionMode generation (PR #143888)
Nathan Gauër via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 12 06:49:10 PDT 2025
https://github.com/Keenuts updated https://github.com/llvm/llvm-project/pull/143888
>From 352cc338998aa91a3806f52edc038037dc9d1913 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nathan=20Gau=C3=ABr?= <brioche at google.com>
Date: Thu, 12 Jun 2025 14:50:38 +0200
Subject: [PATCH 1/2] [SPIR-V] Fix ExecutionMode generation
PR #141787 added code to emit the Fragment execution model.
This required emitting the OriginUpperLeft ExecutionMode.
But this was done by using the same codepath used for OpEntrypoint.
This has 2 issues:
- the interface variables were added to both OpEntryPoint and OpExecutionMode.
- the existing OpExecutionMode logic was not used.
This commit fixes this, regrouping OpExecutionMode handling in one
place, and fixing bad codegen issue when interface variiables are added.
---
llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp | 16 ++++++++++++++++
llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp | 13 +------------
llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp | 2 --
3 files changed, 17 insertions(+), 14 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp b/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
index d4becc2865049..26b94788b810e 100644
--- a/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
@@ -510,6 +510,22 @@ void SPIRVAsmPrinter::outputExecutionMode(const Module &M) {
continue;
MCRegister FReg = MAI->getFuncReg(&F);
assert(FReg.isValid());
+
+ if (Attribute Attr = F.getFnAttribute("hlsl.shader"); Attr.isValid()) {
+ // SPIR-V common validation: Fragment requires OriginUpperLeft or
+ // OriginLowerLeft.
+ // VUID-StandaloneSpirv-OriginLowerLeft-04653: Fragment must declare
+ // OriginUpperLeft.
+ if (Attr.getValueAsString() == "pixel") {
+ MCInst Inst;
+ Inst.setOpcode(SPIRV::OpExecutionMode);
+ Inst.addOperand(MCOperand::createReg(FReg));
+ unsigned EM =
+ static_cast<unsigned>(SPIRV::ExecutionMode::OriginUpperLeft);
+ Inst.addOperand(MCOperand::createImm(EM));
+ outputMCInst(Inst);
+ }
+ }
if (MDNode *Node = F.getMetadata("reqd_work_group_size"))
outputExecutionModeFromMDNode(FReg, Node, SPIRV::ExecutionMode::LocalSize,
3, 1);
diff --git a/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
index 091368a309a82..36cc5cbe655bc 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
@@ -475,21 +475,10 @@ bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
// environment if we need to.
const SPIRVSubtarget *ST =
static_cast<const SPIRVSubtarget *>(&MIRBuilder.getMF().getSubtarget());
- SPIRV::ExecutionModel::ExecutionModel ExecutionModel =
- getExecutionModel(*ST, F);
auto MIB = MIRBuilder.buildInstr(SPIRV::OpEntryPoint)
- .addImm(static_cast<uint32_t>(ExecutionModel))
+ .addImm(static_cast<uint32_t>(getExecutionModel(*ST, F)))
.addUse(FuncVReg);
addStringImm(F.getName(), MIB);
-
- if (ExecutionModel == SPIRV::ExecutionModel::Fragment) {
- // SPIR-V common validation: Fragment requires OriginUpperLeft or
- // OriginLowerLeft VUID-StandaloneSpirv-OriginLowerLeft-04653: Fragment
- // must declare OriginUpperLeft.
- MIRBuilder.buildInstr(SPIRV::OpExecutionMode)
- .addUse(FuncVReg)
- .addImm(static_cast<uint32_t>(SPIRV::ExecutionMode::OriginUpperLeft));
- }
} else if (F.getLinkage() != GlobalValue::InternalLinkage &&
F.getLinkage() != GlobalValue::PrivateLinkage) {
SPIRV::LinkageType::LinkageType LnkTy =
diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
index 2ddd028c79412..b71a9dd68dd44 100644
--- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
@@ -595,8 +595,6 @@ void SPIRVModuleAnalysis::processOtherInstrs(const Module &M) {
collectOtherInstr(MI, MAI, SPIRV::MB_DebugNames, IS);
} else if (OpCode == SPIRV::OpEntryPoint) {
collectOtherInstr(MI, MAI, SPIRV::MB_EntryPoints, IS);
- } else if (OpCode == SPIRV::OpExecutionMode) {
- collectOtherInstr(MI, MAI, SPIRV::MB_EntryPoints, IS);
} else if (TII->isAliasingInstr(MI)) {
collectOtherInstr(MI, MAI, SPIRV::MB_AliasingInsts, IS);
} else if (TII->isDecorationInstr(MI)) {
>From 6fd3879ade593acc2113653b3a05b336d72d5270 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nathan=20Gau=C3=ABr?= <brioche at google.com>
Date: Thu, 12 Jun 2025 15:48:09 +0200
Subject: [PATCH 2/2] add test
---
llvm/test/CodeGen/SPIRV/ExecutionMode_Fragment.ll | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/llvm/test/CodeGen/SPIRV/ExecutionMode_Fragment.ll b/llvm/test/CodeGen/SPIRV/ExecutionMode_Fragment.ll
index 0a62db446cc11..4fa764fe192d3 100644
--- a/llvm/test/CodeGen/SPIRV/ExecutionMode_Fragment.ll
+++ b/llvm/test/CodeGen/SPIRV/ExecutionMode_Fragment.ll
@@ -1,12 +1,20 @@
; RUN: llc -O0 -mtriple=spirv-unknown-vulkan1.3-pixel %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan1.3-pixel %s -o - -filetype=obj | spirv-val --target-env vulkan1.3 %}
-; CHECK-DAG: OpEntryPoint Fragment %[[#entry:]] "main"
+; CHECK-DAG: OpEntryPoint Fragment %[[#entry:]] "main" {{.*}}
; CHECK-DAG: OpExecutionMode %[[#entry]] OriginUpperLeft
-define void @main() #1 {
+
+define void @main() #0 {
entry:
+ %0 = tail call target("spirv.VulkanBuffer", [0 x i32], 12, 1) @llvm.spv.resource.handlefrombinding.tspirv.VulkanBuffer_a0i32_12_1t(i32 0, i32 1, i32 1, i32 0, i1 false)
+ %1 = tail call noundef align 4 dereferenceable(4) ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.VulkanBuffer_a0i32_12_1t(target("spirv.VulkanBuffer", [0 x i32], 12, 1) %0, i32 0)
+ store i32 1, ptr addrspace(11) %1, align 4
+
ret void
}
-attributes #1 = { "hlsl.shader"="pixel" }
+declare target("spirv.VulkanBuffer", [0 x i32], 12, 1) @llvm.spv.resource.handlefrombinding.tspirv.VulkanBuffer_a0i32_12_1t(i32, i32, i32, i32, i1) #1
+
+attributes #0 = { "hlsl.shader"="pixel" }
+attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(none) }
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