[llvm] [AArch64] Add fixed-length SVE USDOT support (PR #143730)

[Nicholas Guy via llvm-commits]

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@@ -407,6 +407,33 @@ define <4 x i32> @four_way_i8_i32_vl128(ptr %accptr, ptr %uptr, ptr %sptr) {
   ret <4 x i32> %partial.reduce
 }
 
+define <4 x i32> @four_way_i8_i32_vl128_usdot(ptr %accptr, ptr %uptr, ptr %sptr) {
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NickGuy-Arm wrote:

Done, though the i8->i64 case is supported (by usdot-ing i8->i32, then extending and accumulating into the i64 vector). So the negative test case is i16->i64, which the SVE USDOT instruction does not support.

https://github.com/llvm/llvm-project/pull/143730