[llvm] ARM: Avoid using getTargetLowering in TargetLowering (PR #143833)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 12 05:12:06 PDT 2025
https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/143833
>From c2d65c3c74272cc611720e13831d1a6f6099b3e6 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Thu, 12 Jun 2025 14:02:33 +0900
Subject: [PATCH] ARM: Avoid using getTargetLowering in TargetLowering
This is this.
---
llvm/lib/Target/ARM/ARMISelLowering.cpp | 37 ++++++++++---------------
1 file changed, 15 insertions(+), 22 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index d2e910a248f23..f17eb72bb2e26 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -2688,8 +2688,7 @@ ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
unsigned RegBegin, RegEnd;
CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
- EVT PtrVT =
- DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
+ EVT PtrVT = getPointerTy(DAG.getDataLayout());
unsigned int i, j;
for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
SDValue Const = DAG.getConstant(4*i, dl, MVT::i32);
@@ -5024,7 +5023,7 @@ ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
SDValue
ARMTargetLowering::LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const {
// Let legalize expand this if it isn't a legal type yet.
- if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
+ if (!isTypeLegal(Op.getValueType()))
return SDValue();
SDValue Value, OverflowCmp;
@@ -5070,7 +5069,7 @@ static SDValue ConvertCarryFlagToBooleanCarry(SDValue Flags, EVT VT,
SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op,
SelectionDAG &DAG) const {
// Let legalize expand this if it isn't a legal type yet.
- if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
+ if (!isTypeLegal(Op.getValueType()))
return SDValue();
SDValue LHS = Op.getOperand(0);
@@ -5168,7 +5167,7 @@ SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
if (Cond.getResNo() == 1 &&
(Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
Opc == ISD::USUBO)) {
- if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
+ if (!isTypeLegal(Cond->getValueType(0)))
return SDValue();
SDValue Value, OverflowCmp;
@@ -5530,8 +5529,7 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
}
if (isUnsupportedFloatingType(LHS.getValueType())) {
- DAG.getTargetLoweringInfo().softenSetCCOperands(
- DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
+ softenSetCCOperands(DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
// If softenSetCCOperands only returned one value, we should compare it to
// zero.
@@ -5736,7 +5734,7 @@ SDValue ARMTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
(Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
Opc == ISD::USUBO || OptimizeMul)) {
// Only lower legal XALUO ops.
- if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
+ if (!isTypeLegal(Cond->getValueType(0)))
return SDValue();
// The actual operation with overflow check.
@@ -5766,8 +5764,7 @@ SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
SDLoc dl(Op);
if (isUnsupportedFloatingType(LHS.getValueType())) {
- DAG.getTargetLoweringInfo().softenSetCCOperands(
- DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
+ softenSetCCOperands(DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
// If softenSetCCOperands only returned one value, we should compare it to
// zero.
@@ -5787,7 +5784,7 @@ SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
Opc == ISD::USUBO || OptimizeMul) &&
(CC == ISD::SETEQ || CC == ISD::SETNE)) {
// Only lower legal XALUO ops.
- if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
+ if (!isTypeLegal(LHS->getValueType(0)))
return SDValue();
// The actual operation with overflow check.
@@ -6255,7 +6252,6 @@ static SDValue CombineVMOVDRRCandidateWithVecOp(const SDNode *BC,
/// vectors), since the legalizer won't know what to do with that.
SDValue ARMTargetLowering::ExpandBITCAST(SDNode *N, SelectionDAG &DAG,
const ARMSubtarget *Subtarget) const {
- const TargetLowering &TLI = DAG.getTargetLoweringInfo();
SDLoc dl(N);
SDValue Op = N->getOperand(0);
@@ -6282,7 +6278,7 @@ SDValue ARMTargetLowering::ExpandBITCAST(SDNode *N, SelectionDAG &DAG,
return SDValue();
// Turn i64->f64 into VMOVDRR.
- if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
+ if (SrcVT == MVT::i64 && isTypeLegal(DstVT)) {
// Do not force values to GPRs (this is what VMOVDRR does for the inputs)
// if we can combine the bitcast with its source.
if (SDValue Val = CombineVMOVDRRCandidateWithVecOp(N, DAG))
@@ -6294,7 +6290,7 @@ SDValue ARMTargetLowering::ExpandBITCAST(SDNode *N, SelectionDAG &DAG,
}
// Turn f64->i64 into VMOVRRD.
- if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
+ if (DstVT == MVT::i64 && isTypeLegal(SrcVT)) {
SDValue Cvt;
if (DAG.getDataLayout().isBigEndian() && SrcVT.isVector() &&
SrcVT.getVectorNumElements() > 1)
@@ -9931,7 +9927,6 @@ SDValue ARMTargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const {
auto PtrVT = getPointerTy(DAG.getDataLayout());
MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
- const TargetLowering &TLI = DAG.getTargetLoweringInfo();
// Pair of floats / doubles used to pass the result.
Type *RetTy = StructType::get(ArgTy, ArgTy);
@@ -9945,7 +9940,7 @@ SDValue ARMTargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const {
const uint64_t ByteSize = DL.getTypeAllocSize(RetTy);
const Align StackAlign = DL.getPrefTypeAlign(RetTy);
int FrameIdx = MFI.CreateStackObject(ByteSize, StackAlign, false);
- SRet = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy(DL));
+ SRet = DAG.getFrameIndex(FrameIdx, getPointerTy(DL));
ArgListEntry Entry;
Entry.Node = SRet;
@@ -10003,7 +9998,6 @@ SDValue ARMTargetLowering::LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG,
SDLoc dl(Op);
const auto &DL = DAG.getDataLayout();
- const auto &TLI = DAG.getTargetLoweringInfo();
const char *Name = nullptr;
if (Signed)
@@ -10011,7 +10005,7 @@ SDValue ARMTargetLowering::LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG,
else
Name = (VT == MVT::i32) ? "__rt_udiv" : "__rt_udiv64";
- SDValue ES = DAG.getExternalSymbol(Name, TLI.getPointerTy(DL));
+ SDValue ES = DAG.getExternalSymbol(Name, getPointerTy(DL));
ARMTargetLowering::ArgListTy Args;
@@ -10101,7 +10095,6 @@ void ARMTargetLowering::ExpandDIV_Windows(
SDValue Op, SelectionDAG &DAG, bool Signed,
SmallVectorImpl<SDValue> &Results) const {
const auto &DL = DAG.getDataLayout();
- const auto &TLI = DAG.getTargetLoweringInfo();
assert(Op.getValueType() == MVT::i64 &&
"unexpected type for custom lowering DIV");
@@ -10113,7 +10106,7 @@ void ARMTargetLowering::ExpandDIV_Windows(
SDValue Lower = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Result);
SDValue Upper = DAG.getNode(ISD::SRL, dl, MVT::i64, Result,
- DAG.getConstant(32, dl, TLI.getPointerTy(DL)));
+ DAG.getConstant(32, dl, getPointerTy(DL)));
Upper = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Upper);
Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lower, Upper));
@@ -10525,8 +10518,8 @@ SDValue ARMTargetLowering::LowerFSETCC(SDValue Op, SelectionDAG &DAG) const {
// If we don't have instructions of this float type then soften to a libcall
// and use SETCC instead.
if (isUnsupportedFloatingType(LHS.getValueType())) {
- DAG.getTargetLoweringInfo().softenSetCCOperands(
- DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS, Chain, IsSignaling);
+ softenSetCCOperands(DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS,
+ Chain, IsSignaling);
if (!RHS.getNode()) {
RHS = DAG.getConstant(0, dl, LHS.getValueType());
CC = ISD::SETNE;
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