[llvm] 5987f1e - [InstCombine] Regenerate `narrow-switch.ll` test (NFC)
Antonio Frighetto via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 12 02:58:51 PDT 2025
Author: Antonio Frighetto
Date: 2025-06-12T11:57:22+02:00
New Revision: 5987f1ee5cc59a05961156c04010ab0f3c857628
URL: https://github.com/llvm/llvm-project/commit/5987f1ee5cc59a05961156c04010ab0f3c857628
DIFF: https://github.com/llvm/llvm-project/commit/5987f1ee5cc59a05961156c04010ab0f3c857628.diff
LOG: [InstCombine] Regenerate `narrow-switch.ll` test (NFC)
`narrow-switch.ll` test has been regenerated via latest UTC using
`--prefix-filecheck-ir-name _`, so as to avoid conflicts with
scripted variable names.
Added:
Modified:
llvm/test/Transforms/InstCombine/narrow-switch.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/InstCombine/narrow-switch.ll b/llvm/test/Transforms/InstCombine/narrow-switch.ll
index 05a30b910e5ee..90f56a61fa410 100644
--- a/llvm/test/Transforms/InstCombine/narrow-switch.ll
+++ b/llvm/test/Transforms/InstCombine/narrow-switch.ll
@@ -1,15 +1,27 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --prefix-filecheck-ir-name _ --version 5
; Vary legal integer types in data layout.
; RUN: opt < %s -passes=instcombine -S -data-layout=n32 | FileCheck %s --check-prefix=ALL --check-prefix=CHECK32
; RUN: opt < %s -passes=instcombine -S -data-layout=n32:64 | FileCheck %s --check-prefix=ALL --check-prefix=CHECK64
define i32 @positive1(i64 %a) {
-; ALL-LABEL: @positive1(
-; ALL: switch i32
-; ALL-NEXT: i32 10, label %return
-; ALL-NEXT: i32 100, label %sw.bb1
-; ALL-NEXT: i32 1001, label %sw.bb2
+; ALL-LABEL: define i32 @positive1(
+; ALL-SAME: i64 [[A:%.*]]) {
+; ALL-NEXT: [[ENTRY:.*]]:
+; ALL-NEXT: [[TRUNC:%.*]] = trunc i64 [[A]] to i32
+; ALL-NEXT: switch i32 [[TRUNC]], label %[[SW_DEFAULT:.*]] [
+; ALL-NEXT: i32 10, label %[[RETURN:.*]]
+; ALL-NEXT: i32 100, label %[[SW_BB1:.*]]
+; ALL-NEXT: i32 1001, label %[[SW_BB2:.*]]
; ALL-NEXT: ]
+; ALL: [[SW_BB1]]:
+; ALL-NEXT: br label %[[RETURN]]
+; ALL: [[SW_BB2]]:
+; ALL-NEXT: br label %[[RETURN]]
+; ALL: [[SW_DEFAULT]]:
+; ALL-NEXT: br label %[[RETURN]]
+; ALL: [[RETURN]]:
+; ALL-NEXT: [[RETVAL_0:%.*]] = phi i32 [ 24, %[[SW_DEFAULT]] ], [ 123, %[[SW_BB2]] ], [ 213, %[[SW_BB1]] ], [ 231, %[[ENTRY]] ]
+; ALL-NEXT: ret i32 [[RETVAL_0]]
;
entry:
%and = and i64 %a, 4294967295
@@ -34,12 +46,24 @@ return:
}
define i32 @negative1(i64 %a) {
-; ALL-LABEL: @negative1(
-; ALL: switch i32
-; ALL-NEXT: i32 -10, label %return
-; ALL-NEXT: i32 -100, label %sw.bb1
-; ALL-NEXT: i32 -1001, label %sw.bb2
+; ALL-LABEL: define i32 @negative1(
+; ALL-SAME: i64 [[A:%.*]]) {
+; ALL-NEXT: [[ENTRY:.*]]:
+; ALL-NEXT: [[TRUNC:%.*]] = trunc i64 [[A]] to i32
+; ALL-NEXT: switch i32 [[TRUNC]], label %[[SW_DEFAULT:.*]] [
+; ALL-NEXT: i32 -10, label %[[RETURN:.*]]
+; ALL-NEXT: i32 -100, label %[[SW_BB1:.*]]
+; ALL-NEXT: i32 -1001, label %[[SW_BB2:.*]]
; ALL-NEXT: ]
+; ALL: [[SW_BB1]]:
+; ALL-NEXT: br label %[[RETURN]]
+; ALL: [[SW_BB2]]:
+; ALL-NEXT: br label %[[RETURN]]
+; ALL: [[SW_DEFAULT]]:
+; ALL-NEXT: br label %[[RETURN]]
+; ALL: [[RETURN]]:
+; ALL-NEXT: [[RETVAL_0:%.*]] = phi i32 [ 24, %[[SW_DEFAULT]] ], [ 123, %[[SW_BB2]] ], [ 213, %[[SW_BB1]] ], [ 231, %[[ENTRY]] ]
+; ALL-NEXT: ret i32 [[RETVAL_0]]
;
entry:
%or = or i64 %a, -4294967296
@@ -67,12 +91,24 @@ return:
; assertion.
define i32 @trunc72to68(i72 %a) {
-; ALL-LABEL: @trunc72to68(
-; ALL: switch i68
-; ALL-NEXT: i68 10, label %return
-; ALL-NEXT: i68 100, label %sw.bb1
-; ALL-NEXT: i68 1001, label %sw.bb2
+; ALL-LABEL: define i32 @trunc72to68(
+; ALL-SAME: i72 [[A:%.*]]) {
+; ALL-NEXT: [[ENTRY:.*]]:
+; ALL-NEXT: [[TRUNC:%.*]] = trunc i72 [[A]] to i68
+; ALL-NEXT: switch i68 [[TRUNC]], label %[[SW_DEFAULT:.*]] [
+; ALL-NEXT: i68 10, label %[[RETURN:.*]]
+; ALL-NEXT: i68 100, label %[[SW_BB1:.*]]
+; ALL-NEXT: i68 1001, label %[[SW_BB2:.*]]
; ALL-NEXT: ]
+; ALL: [[SW_BB1]]:
+; ALL-NEXT: br label %[[RETURN]]
+; ALL: [[SW_BB2]]:
+; ALL-NEXT: br label %[[RETURN]]
+; ALL: [[SW_DEFAULT]]:
+; ALL-NEXT: br label %[[RETURN]]
+; ALL: [[RETURN]]:
+; ALL-NEXT: [[RETVAL_0:%.*]] = phi i32 [ 24, %[[SW_DEFAULT]] ], [ 123, %[[SW_BB2]] ], [ 213, %[[SW_BB1]] ], [ 231, %[[ENTRY]] ]
+; ALL-NEXT: ret i32 [[RETVAL_0]]
;
entry:
%and = and i72 %a, 295147905179352825855
@@ -103,15 +139,38 @@ return:
; because both are illegal.
define void @trunc64to58(i64 %a) {
-; ALL-LABEL: @trunc64to58(
-; CHECK32: switch i58
-; CHECK32-NEXT: i58 0, label %sw.bb1
-; CHECK32-NEXT: i58 18717182647723699, label %sw.bb2
+; CHECK32-LABEL: define void @trunc64to58(
+; CHECK32-SAME: i64 [[A:%.*]]) {
+; CHECK32-NEXT: [[ENTRY:.*:]]
+; CHECK32-NEXT: [[TMP0:%.*]] = trunc i64 [[A]] to i58
+; CHECK32-NEXT: [[TMP1:%.*]] = and i58 [[TMP0]], 15
+; CHECK32-NEXT: [[TRUNC:%.*]] = mul nuw i58 [[TMP1]], 18717182647723699
+; CHECK32-NEXT: switch i58 [[TRUNC]], label %[[SW_DEFAULT:.*]] [
+; CHECK32-NEXT: i58 0, label %[[SW_BB1:.*]]
+; CHECK32-NEXT: i58 18717182647723699, label %[[SW_BB2:.*]]
; CHECK32-NEXT: ]
-; CHECK64: switch i64
-; CHECK64-NEXT: i64 0, label %sw.bb1
-; CHECK64-NEXT: i64 18717182647723699, label %sw.bb2
+; CHECK32: [[SW_BB1]]:
+; CHECK32-NEXT: br label %[[SW_DEFAULT]]
+; CHECK32: [[SW_BB2]]:
+; CHECK32-NEXT: br label %[[SW_DEFAULT]]
+; CHECK32: [[SW_DEFAULT]]:
+; CHECK32-NEXT: ret void
+;
+; CHECK64-LABEL: define void @trunc64to58(
+; CHECK64-SAME: i64 [[A:%.*]]) {
+; CHECK64-NEXT: [[ENTRY:.*:]]
+; CHECK64-NEXT: [[_TMP0:%.*]] = and i64 [[A]], 15
+; CHECK64-NEXT: [[TMP0:%.*]] = mul nuw nsw i64 [[_TMP0]], 18717182647723699
+; CHECK64-NEXT: switch i64 [[TMP0]], label %[[SW_DEFAULT:.*]] [
+; CHECK64-NEXT: i64 0, label %[[SW_BB1:.*]]
+; CHECK64-NEXT: i64 18717182647723699, label %[[SW_BB2:.*]]
; CHECK64-NEXT: ]
+; CHECK64: [[SW_BB1]]:
+; CHECK64-NEXT: br label %[[SW_DEFAULT]]
+; CHECK64: [[SW_BB2]]:
+; CHECK64-NEXT: br label %[[SW_DEFAULT]]
+; CHECK64: [[SW_DEFAULT]]:
+; CHECK64-NEXT: ret void
;
entry:
%tmp0 = and i64 %a, 15
@@ -136,18 +195,19 @@ sw.default:
; https://llvm.org/bugs/show_bug.cgi?id=31260
define i8 @PR31260(i8 %x) {
-; ALL-LABEL: @PR31260(
-; ALL-NEXT: entry:
-; ALL-NEXT: [[T4:%.*]] = and i8 [[X:%.*]], 2
-; ALL-NEXT: switch i8 [[T4]], label [[EXIT:%.*]] [
-; ALL-NEXT: i8 0, label [[CASE126:%.*]]
-; ALL-NEXT: i8 2, label [[CASE124:%.*]]
+; ALL-LABEL: define i8 @PR31260(
+; ALL-SAME: i8 [[X:%.*]]) {
+; ALL-NEXT: [[ENTRY:.*:]]
+; ALL-NEXT: [[T4:%.*]] = and i8 [[X]], 2
+; ALL-NEXT: switch i8 [[T4]], label %[[EXIT:.*]] [
+; ALL-NEXT: i8 0, label %[[CASE126:.*]]
+; ALL-NEXT: i8 2, label %[[CASE124:.*]]
; ALL-NEXT: ]
-; ALL: exit:
+; ALL: [[EXIT]]:
; ALL-NEXT: ret i8 1
-; ALL: case126:
+; ALL: [[CASE126]]:
; ALL-NEXT: ret i8 3
-; ALL: case124:
+; ALL: [[CASE124]]:
; ALL-NEXT: ret i8 5
;
entry:
@@ -169,12 +229,33 @@ case124:
; Make sure the arithmetic evaluation of the switch
; condition is evaluated on the original type
define i32 @trunc32to16(i32 %a0) #0 {
-; ALL-LABEL: @trunc32to16(
-; ALL: switch i16
-; ALL-NEXT: i16 63, label %sw.bb
-; ALL-NEXT: i16 1, label %sw.bb1
-; ALL-NEXT: i16 100, label %sw.bb2
+; ALL-LABEL: define i32 @trunc32to16(
+; ALL-SAME: i32 [[A0:%.*]]) {
+; ALL-NEXT: [[ENTRY:.*:]]
+; ALL-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
+; ALL-NEXT: [[XOR:%.*]] = lshr i32 [[A0]], 16
+; ALL-NEXT: [[TMP0:%.*]] = trunc nuw i32 [[XOR]] to i16
+; ALL-NEXT: [[TRUNC:%.*]] = xor i16 [[TMP0]], 15784
+; ALL-NEXT: switch i16 [[TRUNC]], label %[[SW_EPILOG:.*]] [
+; ALL-NEXT: i16 63, label %[[SW_BB:.*]]
+; ALL-NEXT: i16 1, label %[[SW_BB1:.*]]
+; ALL-NEXT: i16 100, label %[[SW_BB2:.*]]
; ALL-NEXT: ]
+; ALL: [[SW_BB]]:
+; ALL-NEXT: store i32 90, ptr [[RETVAL]], align 4
+; ALL-NEXT: br label %[[RETURN:.*]]
+; ALL: [[SW_BB1]]:
+; ALL-NEXT: store i32 91, ptr [[RETVAL]], align 4
+; ALL-NEXT: br label %[[RETURN]]
+; ALL: [[SW_BB2]]:
+; ALL-NEXT: store i32 92, ptr [[RETVAL]], align 4
+; ALL-NEXT: br label %[[RETURN]]
+; ALL: [[SW_EPILOG]]:
+; ALL-NEXT: store i32 113, ptr [[RETVAL]], align 4
+; ALL-NEXT: br label %[[RETURN]]
+; ALL: [[RETURN]]:
+; ALL-NEXT: [[RVAL:%.*]] = load i32, ptr [[RETVAL]], align 4
+; ALL-NEXT: ret i32 [[RVAL]]
;
entry:
%retval = alloca i32, align 4
@@ -182,9 +263,9 @@ entry:
%shr = lshr i32 %xor, 16
%add = add i32 %shr, -917677090
switch i32 %add, label %sw.epilog [
- i32 -917677027, label %sw.bb
- i32 -917677089, label %sw.bb1
- i32 -917676990, label %sw.bb2
+ i32 -917677027, label %sw.bb
+ i32 -917677089, label %sw.bb1
+ i32 -917676990, label %sw.bb2
]
sw.bb: ; preds = %entry
@@ -219,11 +300,32 @@ declare i32 @goo()
; if original type is legal (i32 in this case)
define void @PR29009() {
-; ALL-LABEL: @PR29009(
-; ALL: switch i32
-; ALL-NEXT: i32 0, label
-; ALL-NEXT: i32 3, label
+; ALL-LABEL: define void @PR29009() {
+; ALL-NEXT: br label %[[BB1:.*]]
+; ALL: [[BB1]]:
+; ALL-NEXT: [[TMP2:%.*]] = load volatile i32, ptr @njob, align 4
+; ALL-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP2]], 0
+; ALL-NEXT: br i1 [[DOTNOT]], label %[[BB10:.*]], label %[[BB3:.*]]
+; ALL: [[BB3]]:
+; ALL-NEXT: [[TMP4:%.*]] = call i32 @goo()
+; ALL-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], 7
+; ALL-NEXT: switch i32 [[TMP5]], label %[[BB6:.*]] [
+; ALL-NEXT: i32 0, label %[[BB7:.*]]
+; ALL-NEXT: i32 3, label %[[BB8:.*]]
; ALL-NEXT: ]
+; ALL: [[BB6]]:
+; ALL-NEXT: store i32 6, ptr @a, align 4
+; ALL-NEXT: br label %[[BB9:.*]]
+; ALL: [[BB7]]:
+; ALL-NEXT: store i32 1, ptr @a, align 4
+; ALL-NEXT: br label %[[BB9]]
+; ALL: [[BB8]]:
+; ALL-NEXT: store i32 2, ptr @a, align 4
+; ALL-NEXT: br label %[[BB9]]
+; ALL: [[BB9]]:
+; ALL-NEXT: br label %[[BB1]]
+; ALL: [[BB10]]:
+; ALL-NEXT: ret void
;
br label %1
@@ -236,8 +338,8 @@ define void @PR29009() {
%5 = call i32 @goo()
%6 = and i32 %5, 7
switch i32 %6, label %7 [
- i32 0, label %8
- i32 3, label %9
+ i32 0, label %8
+ i32 3, label %9
]
; <label>:7: ; preds = %4
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