[llvm] [Xtensa] Implement Xtensa Interrupt/Exception/Debug Options. (PR #143820)

[Matt Arsenault via llvm-commits]

================
@@ -115,9 +217,18 @@ def MR01 :  RegisterClass<"Xtensa", [i32], 32, (add M0, M1)>;
 def MR23 :  RegisterClass<"Xtensa", [i32], 32, (add M2, M3)>;
 def MR   :  RegisterClass<"Xtensa", [i32], 32, (add MR01, MR23)>;
 
+//def SR :  RegisterClass<"Xtensa", [i32], 32, (add
+//  LBEG, LEND, LCOUNT, SAR, BREG, LITBASE, ACCLO, ACCHI, MR, WINDOWBASE, WINDOWSTART,
+//  MEMCTL, VECBASE, MISC0, MISC1, MISC2, MISC3)>;
----------------
arsenm wrote:

Commented out code 

https://github.com/llvm/llvm-project/pull/143820