[llvm] [AArch64] Use `ZIP1/2` over `INS` for vector concat (PR #142427)

[Eli Friedman via llvm-commits]

efriedma-quic wrote:

If we care about Cortex-A55, you could do something with convertToThreeAddress, which would allow converting the INS to ZIP1/2 if it saves a move.

I haven't been doing any performance work with small cores recently; I'm not sure if any current cores have a half-width NEON unit.  Maybe someone at Arm knows.

https://github.com/llvm/llvm-project/pull/142427