[llvm] 7a3bcf9 - [RISCV] Add missing predicate for PseudoTHVdotVMAQA family instructions

[Jim Lin via llvm-commits]

Author: Jim Lin
Date: 2025-06-12T08:43:06+08:00
New Revision: 7a3bcf9f7179e6904d405de36360714da07c31ba

URL: https://github.com/llvm/llvm-project/commit/7a3bcf9f7179e6904d405de36360714da07c31ba
DIFF: https://github.com/llvm/llvm-project/commit/7a3bcf9f7179e6904d405de36360714da07c31ba.diff

LOG: [RISCV] Add missing predicate for PseudoTHVdotVMAQA family instructions

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
index 2fccbcaf2cf37..89441444a994e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
@@ -660,10 +660,12 @@ def : Pat<(i32 (sub GPR:$rd, (mul (sexti16 (i32 GPR:$rs1)),
           (TH_MULSH GPR:$rd, GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasVendorXTHeadMac, IsRV32]
 
+let Predicates = [HasVendorXTHeadVdot] in {
 defm PseudoTHVdotVMAQA      : VPseudoVMAQA_VV_VX;
 defm PseudoTHVdotVMAQAU     : VPseudoVMAQA_VV_VX;
 defm PseudoTHVdotVMAQASU    : VPseudoVMAQA_VV_VX;
 defm PseudoTHVdotVMAQAUS    : VPseudoVMAQA_VX;
+}
 
 let Predicates = [HasVendorXTHeadVdot] in {
 defm : VPatTernaryVMAQA_VV_VX<"int_riscv_th_vmaqa",  "PseudoTHVdotVMAQA",