[llvm] [llvm][InstCombine] Fold signum(x) into scmp(x, 0) (PR #143445)
Yash Solanki via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 11 10:09:40 PDT 2025
https://github.com/yashnator updated https://github.com/llvm/llvm-project/pull/143445
>From 6c41e1327168a9b8d743df64fb47335227eb40ef Mon Sep 17 00:00:00 2001
From: Yash Solanki <252yash at gmail.com>
Date: Tue, 10 Jun 2025 02:53:42 +0530
Subject: [PATCH 1/2] [Instcombine][Tests] Add test for folding select to cmp
with weak inequalities and constants on RHS. Tests has baseline CHECK lines.
---
.../Transforms/InstCombine/select-to-cmp.ll | 295 ++++++++++++++++++
1 file changed, 295 insertions(+)
create mode 100644 llvm/test/Transforms/InstCombine/select-to-cmp.ll
diff --git a/llvm/test/Transforms/InstCombine/select-to-cmp.ll b/llvm/test/Transforms/InstCombine/select-to-cmp.ll
new file mode 100644
index 0000000000000..73ee037f6f22a
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/select-to-cmp.ll
@@ -0,0 +1,295 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -passes=instcombine -S < %s | FileCheck %s
+
+; Fold (x < y) ? -1 : zext(x != y) to scmp(x, y)
+define i32 @scmp_x_y_from_lt(i32 %x, i32 %y) {
+; CHECK-LABEL: define i32 @scmp_x_y_from_lt(
+; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
+; CHECK-NEXT: [[SEL:%.*]] = call i32 @llvm.scmp.i32.i32(i32 [[X]], i32 [[Y]])
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %cmp1 = icmp ne i32 %x, %y
+ %zext = zext i1 %cmp1 to i32
+ %cmp2 = icmp slt i32 %x, %y
+ %sel = select i1 %cmp2, i32 -1, i32 %zext
+ ret i32 %sel
+}
+
+; Fold (x < y) ? -1 : zext(x > y) to scmp(x, y)
+define i32 @scmp_x_y_from_lt_gt(i32 %x, i32 %y) {
+; CHECK-LABEL: define i32 @scmp_x_y_from_lt_gt(
+; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
+; CHECK-NEXT: [[SEL:%.*]] = call i32 @llvm.scmp.i32.i32(i32 [[X]], i32 [[Y]])
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %cmp1 = icmp sgt i32 %x, %y
+ %zext = zext i1 %cmp1 to i32
+ %cmp2 = icmp slt i32 %x, %y
+ %sel = select i1 %cmp2, i32 -1, i32 %zext
+ ret i32 %sel
+}
+
+; Fold (x > y) ? 1 : sext(x != y) to scmp(x, y)
+define i32 @scmp_x_y_from_gt_sext_ne(i32 %x, i32 %y) {
+; CHECK-LABEL: define i32 @scmp_x_y_from_gt_sext_ne(
+; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
+; CHECK-NEXT: [[SEL:%.*]] = call i32 @llvm.scmp.i32.i32(i32 [[X]], i32 [[Y]])
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %cmp1 = icmp ne i32 %x, %y
+ %sext = sext i1 %cmp1 to i32
+ %cmp2 = icmp sgt i32 %x, %y
+ %sel = select i1 %cmp2, i32 1, i32 %sext
+ ret i32 %sel
+}
+
+; Fold (x > y) ? 1 : sext(x < y) to scmp(x, y)
+define i32 @scmp_x_y_from_gt_sext_lt(i32 %x, i32 %y) {
+; CHECK-LABEL: define i32 @scmp_x_y_from_gt_sext_lt(
+; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
+; CHECK-NEXT: [[SEL:%.*]] = call i32 @llvm.scmp.i32.i32(i32 [[X]], i32 [[Y]])
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %cmp1 = icmp slt i32 %x, %y
+ %sext = sext i1 %cmp1 to i32
+ %cmp2 = icmp sgt i32 %x, %y
+ %sel = select i1 %cmp2, i32 1, i32 %sext
+ ret i32 %sel
+}
+
+; Fold (x <= y - 1) ? -1 : zext(x != y) to ucmp(x, y)
+define i32 @ucmp_x_y_from_le_sub_zext_ne(i32 %x, i32 %y) {
+; CHECK-LABEL: define i32 @ucmp_x_y_from_le_sub_zext_ne(
+; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
+; CHECK-NEXT: [[YM1:%.*]] = add i32 [[Y]], -1
+; CHECK-NEXT: [[CMP1_NOT:%.*]] = icmp ugt i32 [[X]], [[YM1]]
+; CHECK-NEXT: [[NEQ:%.*]] = icmp ne i32 [[X]], [[Y]]
+; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[NEQ]] to i32
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP1_NOT]], i32 [[ZEXT]], i32 -1
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %ym1 = sub i32 %y, 1
+ %cmp1 = icmp ule i32 %x, %ym1
+ %neq = icmp ne i32 %x, %y
+ %zext = zext i1 %neq to i32
+ %sel = select i1 %cmp1, i32 -1, i32 %zext
+ ret i32 %sel
+}
+
+; Fold (x <= y - 1) ? -1 : zext(x > y) to ucmp(x, y)
+define i32 @ucmp_x_y_from_le_sub_zext_gt(i32 %x, i32 %y) {
+; CHECK-LABEL: define i32 @ucmp_x_y_from_le_sub_zext_gt(
+; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
+; CHECK-NEXT: [[YM1:%.*]] = add i32 [[Y]], -1
+; CHECK-NEXT: [[CMP1_NOT:%.*]] = icmp ugt i32 [[X]], [[YM1]]
+; CHECK-NEXT: [[GT:%.*]] = icmp ugt i32 [[X]], [[Y]]
+; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[GT]] to i32
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP1_NOT]], i32 [[ZEXT]], i32 -1
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %ym1 = sub i32 %y, 1
+ %cmp1 = icmp ule i32 %x, %ym1
+ %gt = icmp ugt i32 %x, %y
+ %zext = zext i1 %gt to i32
+ %sel = select i1 %cmp1, i32 -1, i32 %zext
+ ret i32 %sel
+}
+
+; Fold (x >= y + 1) ? 1 : sext(x != y) to ucmp(x, y)
+define i32 @ucmp_x_y_from_ge_add_sext_ne(i32 %x, i32 %y) {
+; CHECK-LABEL: define i32 @ucmp_x_y_from_ge_add_sext_ne(
+; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
+; CHECK-NEXT: [[YP1:%.*]] = add i32 [[Y]], 1
+; CHECK-NEXT: [[CMP1_NOT:%.*]] = icmp ult i32 [[X]], [[YP1]]
+; CHECK-NEXT: [[NEQ:%.*]] = icmp ne i32 [[X]], [[Y]]
+; CHECK-NEXT: [[SEXT:%.*]] = sext i1 [[NEQ]] to i32
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP1_NOT]], i32 [[SEXT]], i32 1
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %yp1 = add i32 %y, 1
+ %cmp1 = icmp uge i32 %x, %yp1
+ %neq = icmp ne i32 %x, %y
+ %sext = sext i1 %neq to i32
+ %sel = select i1 %cmp1, i32 1, i32 %sext
+ ret i32 %sel
+}
+
+; Fold (x >= y + 1) ? 1 : sext(x < y) to ucmp(x, y)
+define i32 @ucmp_x_y_from_ge_add_sext_lt(i32 %x, i32 %y) {
+; CHECK-LABEL: define i32 @ucmp_x_y_from_ge_add_sext_lt(
+; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
+; CHECK-NEXT: [[YP1:%.*]] = add i32 [[Y]], 1
+; CHECK-NEXT: [[CMP1_NOT:%.*]] = icmp ult i32 [[X]], [[YP1]]
+; CHECK-NEXT: [[LT:%.*]] = icmp ult i32 [[X]], [[Y]]
+; CHECK-NEXT: [[SEXT:%.*]] = sext i1 [[LT]] to i32
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP1_NOT]], i32 [[SEXT]], i32 1
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %yp1 = add i32 %y, 1
+ %cmp1 = icmp uge i32 %x, %yp1
+ %lt = icmp ult i32 %x, %y
+ %sext = sext i1 %lt to i32
+ %sel = select i1 %cmp1, i32 1, i32 %sext
+ ret i32 %sel
+}
+
+; Fold (x > y - 1) ? zext(x != y) : -1 to scmp(x, y)
+define i32 @scmp_x_y_from_gt_sub_zext_ne(i32 %x, i32 %y) {
+; CHECK-LABEL: define i32 @scmp_x_y_from_gt_sub_zext_ne(
+; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
+; CHECK-NEXT: [[YM1:%.*]] = add i32 [[Y]], -1
+; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[X]], [[YM1]]
+; CHECK-NEXT: [[NE:%.*]] = icmp ne i32 [[X]], [[Y]]
+; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[NE]] to i32
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP1]], i32 [[ZEXT]], i32 -1
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %ym1 = sub i32 %y, 1
+ %cmp1 = icmp sgt i32 %x, %ym1
+ %ne = icmp ne i32 %x, %y
+ %zext = zext i1 %ne to i32
+ %sel = select i1 %cmp1, i32 %zext, i32 -1
+ ret i32 %sel
+}
+
+; Fold (x > y - 1) ? zext(x > y) : -1 to ucmp(x, y)
+define i32 @ucmp_x_y_from_gt_sub_zext_gt(i32 %x, i32 %y) {
+; CHECK-LABEL: define i32 @ucmp_x_y_from_gt_sub_zext_gt(
+; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
+; CHECK-NEXT: [[YM1:%.*]] = add i32 [[Y]], -1
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 [[X]], [[YM1]]
+; CHECK-NEXT: [[GT:%.*]] = icmp ugt i32 [[X]], [[Y]]
+; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[GT]] to i32
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP1]], i32 [[ZEXT]], i32 -1
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %ym1 = sub i32 %y, 1
+ %cmp1 = icmp ugt i32 %x, %ym1
+ %gt = icmp ugt i32 %x, %y
+ %zext = zext i1 %gt to i32
+ %sel = select i1 %cmp1, i32 %zext, i32 -1
+ ret i32 %sel
+}
+
+; Fold (x < y + 1) ? sext(x != y) : 1 to scmp(x, y)
+define i32 @scmp_x_y_from_lt_add_sext_ne(i32 %x, i32 %y) {
+; CHECK-LABEL: define i32 @scmp_x_y_from_lt_add_sext_ne(
+; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
+; CHECK-NEXT: [[YP1:%.*]] = add i32 [[Y]], 1
+; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[X]], [[YP1]]
+; CHECK-NEXT: [[NE:%.*]] = icmp ne i32 [[X]], [[Y]]
+; CHECK-NEXT: [[SEXT:%.*]] = sext i1 [[NE]] to i32
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP1]], i32 [[SEXT]], i32 1
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %yp1 = add i32 %y, 1
+ %cmp1 = icmp slt i32 %x, %yp1
+ %ne = icmp ne i32 %x, %y
+ %sext = sext i1 %ne to i32
+ %sel = select i1 %cmp1, i32 %sext, i32 1
+ ret i32 %sel
+}
+
+; Fold (x < y + 1) ? sext(x < y) : 1 to ucmp(x, y)
+define i32 @ucmp_x_y_from_lt_add_sext_lt(i32 %x, i32 %y) {
+; CHECK-LABEL: define i32 @ucmp_x_y_from_lt_add_sext_lt(
+; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
+; CHECK-NEXT: [[YP1:%.*]] = add i32 [[Y]], 1
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[X]], [[YP1]]
+; CHECK-NEXT: [[LT:%.*]] = icmp ult i32 [[X]], [[Y]]
+; CHECK-NEXT: [[SEXT:%.*]] = sext i1 [[LT]] to i32
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP1]], i32 [[SEXT]], i32 1
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %yp1 = add i32 %y, 1
+ %cmp1 = icmp ult i32 %x, %yp1
+ %lt = icmp ult i32 %x, %y
+ %sext = sext i1 %lt to i32
+ %sel = select i1 %cmp1, i32 %sext, i32 1
+ ret i32 %sel
+}
+
+; Testing with constants
+
+define i32 @scmp_x_0_inverted(i32 %x) {
+; CHECK-LABEL: define i32 @scmp_x_0_inverted(
+; CHECK-SAME: i32 [[X:%.*]]) {
+; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[X]], 0
+; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP4]] to i32
+; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i32 [[X]], -1
+; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 -1
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ %2 = icmp ne i32 %x, 0
+ %3 = zext i1 %2 to i32
+ %4 = icmp sgt i32 %x, -1
+ %5 = select i1 %4, i32 %3, i32 -1
+ ret i32 %5
+}
+
+define i32 @scmp_x_neg_6_sgt_form(i32 %x) {
+; CHECK-LABEL: define i32 @scmp_x_neg_6_sgt_form(
+; CHECK-SAME: i32 [[X:%.*]]) {
+; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[X]], -6
+; CHECK-NEXT: [[NE:%.*]] = icmp ne i32 [[X]], -5
+; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[NE]] to i32
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP1]], i32 [[ZEXT]], i32 -1
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %cmp1 = icmp sgt i32 %x, -6
+ %ne = icmp ne i32 %x, -5
+ %zext = zext i1 %ne to i32
+ %sel = select i1 %cmp1, i32 %zext, i32 -1
+ ret i32 %sel
+}
+
+define i32 @ucmp_x_5_ult_form(i32 %x) {
+; CHECK-LABEL: define i32 @ucmp_x_5_ult_form(
+; CHECK-SAME: i32 [[X:%.*]]) {
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[X]], 6
+; CHECK-NEXT: [[NE:%.*]] = icmp ne i32 [[X]], 5
+; CHECK-NEXT: [[SEXT:%.*]] = sext i1 [[NE]] to i32
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP1]], i32 [[SEXT]], i32 1
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %cmp1 = icmp ult i32 %x, 6
+ %ne = icmp ne i32 %x, 5
+ %sext = sext i1 %ne to i32
+ %sel = select i1 %cmp1, i32 %sext, i32 1
+ ret i32 %sel
+}
+
+; Negative examples
+
+; (x < y) ? -1 : zext(x == y)
+define i32 @scmp_negative_1(i32 %x, i32 %y) {
+; CHECK-LABEL: define i32 @scmp_negative_1(
+; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
+; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[X]], [[Y]]
+; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP1]] to i32
+; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[X]], [[Y]]
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP2]], i32 -1, i32 [[ZEXT]]
+; CHECK-NEXT: ret i32 [[SEL]]
+;
+ %cmp1 = icmp eq i32 %x, %y
+ %zext = zext i1 %cmp1 to i32
+ %cmp2 = icmp slt i32 %x, %y
+ %sel = select i1 %cmp2, i32 -1, i32 %zext
+ ret i32 %sel
+}
+
+define i32 @scmp_ne_0(i32 noundef %0) {
+; CHECK-LABEL: define i32 @scmp_ne_0(
+; CHECK-SAME: i32 noundef [[TMP0:%.*]]) {
+; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP0]], 0
+; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP5]] to i32
+; CHECK-NEXT: [[TMP4:%.*]] = icmp sgt i32 [[TMP0]], 1
+; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP4]], i32 [[TMP3]], i32 -1
+; CHECK-NEXT: ret i32 [[TMP2]]
+;
+ %2 = icmp ne i32 %0, 0
+ %3 = zext i1 %2 to i32
+ %4 = icmp sgt i32 %0, 1
+ %5 = select i1 %4, i32 %3, i32 -1
+ ret i32 %5
+}
>From a9e08772d422100f4e6fad3cafa8770a22967ae2 Mon Sep 17 00:00:00 2001
From: Yash Solanki <252yash at gmail.com>
Date: Wed, 11 Jun 2025 20:10:42 +0530
Subject: [PATCH 2/2] [InstCombine] Fold select to cmp for weak inequalities
and for comparisons with constant on RHS.
Fold select into scmp/ucmp based on signedness of
the comparison predicate. Add fold for:
Weak inequalities and their logical inverses:
- (x <= y - 1) ? -1 : zext(x != y) | (x > y - 1) ? zext(x != y) : -1
- (x <= y - 1) ? -1 : zext(x > y) | (x > y - 1) ? zext(x > y) : -1
- (x >= y + 1) ? 1 : sext(x != y) | (x < y - 1) ? sext(x != y) : 1
- (x >= y + 1) ? 1 : sext(x < y) | (x < y - 1) ? sext(x < y) : 1
and strict version of above inequalities and their logical inverses.
Resolves #143259
---
.../InstCombine/InstCombineSelect.cpp | 74 ++++++++++++++++---
.../Transforms/InstCombine/select-to-cmp.ll | 63 +++-------------
2 files changed, 76 insertions(+), 61 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
index 8f46ae304353d..c5b96e0c9e9c4 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
@@ -3554,10 +3554,11 @@ static Instruction *foldBitCeil(SelectInst &SI, IRBuilderBase &Builder,
}
// This function tries to fold the following operations:
-// (x < y) ? -1 : zext(x != y)
-// (x < y) ? -1 : zext(x > y)
-// (x > y) ? 1 : sext(x != y)
-// (x > y) ? 1 : sext(x < y)
+// (x < y) ? -1 : zext(x != y) | (x <= y - 1) ? -1 : zext(x != y)
+// (x < y) ? -1 : zext(x > y) | (x <= y - 1) ? -1 : zext(x > y)
+// (x > y) ? 1 : sext(x != y) | (x >= y + 1) ? 1: sext(x != y)
+// (x > y) ? 1 : sext(x < y) | (x >= y + 1) ? 1: sext(x < y)
+// and their logical inverses
// Into ucmp/scmp(x, y), where signedness is determined by the signedness
// of the comparison in the original sequence.
Instruction *InstCombinerImpl::foldSelectToCmp(SelectInst &SI) {
@@ -3572,12 +3573,22 @@ Instruction *InstCombinerImpl::foldSelectToCmp(SelectInst &SI) {
if (!LHS->getType()->isIntOrIntVectorTy())
return nullptr;
+ // If the select instrction doesn't have 1/-1 for the TV check if FV has 1/-1.
+ // If it does, then use the inverted inequality and swap TV and FV
+ if (!match(TV, m_AllOnes()) && !match(TV, m_One())) {
+ if (match(FV, m_AllOnes()) || match(FV, m_One())) {
+ Pred = ICmpInst::getInversePredicate(Pred);
+ std::swap(TV, FV);
+ }
+ }
+
// Try to swap operands and the predicate. We need to be careful when doing
// so because two of the patterns have opposite predicates, so use the
// constant inside select to determine if swapping operands would be
// beneficial to us.
- if ((ICmpInst::isGT(Pred) && match(TV, m_AllOnes())) ||
- (ICmpInst::isLT(Pred) && match(TV, m_One()))) {
+ if (((ICmpInst::isGT(Pred) || ICmpInst::isGE(Pred)) &&
+ match(TV, m_AllOnes())) ||
+ ((ICmpInst::isLT(Pred) || ICmpInst::isLE(Pred)) && match(TV, m_One()))) {
Pred = ICmpInst::getSwappedPredicate(Pred);
std::swap(LHS, RHS);
}
@@ -3585,14 +3596,56 @@ Instruction *InstCombinerImpl::foldSelectToCmp(SelectInst &SI) {
bool Replace = false;
CmpPredicate ExtendedCmpPredicate;
+ Value *FV_RHS;
+
+ // (x <= y - 1) ? -1 : zext(x != y)
+ // (x <= y - 1) ? -1 : zext(x > y)
+ if (ICmpInst::isLE(Pred) && match(TV, m_AllOnes()) &&
+ match(FV, m_ZExt(m_c_ICmp(ExtendedCmpPredicate, m_Specific(LHS),
+ m_Value(FV_RHS)))) &&
+ (ExtendedCmpPredicate == ICmpInst::ICMP_NE ||
+ ICmpInst::getInversePredicate(ExtendedCmpPredicate) == Pred)) {
+ if (match(RHS, m_Add(m_Specific(FV_RHS), m_AllOnes())) ||
+ match(FV_RHS, m_Add(m_Specific(RHS), m_One())))
+ Replace = true;
+ else if (auto *C = dyn_cast<ConstantInt>(RHS)) {
+ if (auto *D = dyn_cast<ConstantInt>(FV_RHS)) {
+ if ((IsSigned && C->getSExtValue() + 1 == D->getSExtValue()) ||
+ (!IsSigned && C->getZExtValue() + 1 == D->getZExtValue()))
+ Replace = true;
+ }
+ }
+ }
+
// (x < y) ? -1 : zext(x != y)
// (x < y) ? -1 : zext(x > y)
if (ICmpInst::isLT(Pred) && match(TV, m_AllOnes()) &&
match(FV, m_ZExt(m_c_ICmp(ExtendedCmpPredicate, m_Specific(LHS),
m_Specific(RHS)))) &&
(ExtendedCmpPredicate == ICmpInst::ICMP_NE ||
- ICmpInst::getSwappedPredicate(ExtendedCmpPredicate) == Pred))
+ ICmpInst::getSwappedPredicate(ExtendedCmpPredicate) == Pred)) {
+ FV_RHS = RHS;
Replace = true;
+ }
+
+ // (x >= y + 1) ? 1 : sext(x != y)
+ // (x >= y + 1) ? 1 : sext(x < y)
+ if (ICmpInst::isGE(Pred) && match(TV, m_One()) &&
+ match(FV, m_SExt(m_c_ICmp(ExtendedCmpPredicate, m_Specific(LHS),
+ m_Value(FV_RHS)))) &&
+ (ExtendedCmpPredicate == ICmpInst::ICMP_NE ||
+ ICmpInst::getInversePredicate(ExtendedCmpPredicate) == Pred)) {
+ if (match(RHS, m_Add(m_Specific(FV_RHS), m_One())) ||
+ match(FV_RHS, m_Add(m_Specific(RHS), m_AllOnes())))
+ Replace = true;
+ else if (auto *C = dyn_cast<ConstantInt>(RHS)) {
+ if (auto *D = dyn_cast<ConstantInt>(FV_RHS)) {
+ if ((IsSigned && C->getSExtValue() == D->getSExtValue() + 1) ||
+ (!IsSigned && C->getZExtValue() == D->getZExtValue() + 1))
+ Replace = true;
+ }
+ }
+ }
// (x > y) ? 1 : sext(x != y)
// (x > y) ? 1 : sext(x < y)
@@ -3600,8 +3653,10 @@ Instruction *InstCombinerImpl::foldSelectToCmp(SelectInst &SI) {
match(FV, m_SExt(m_c_ICmp(ExtendedCmpPredicate, m_Specific(LHS),
m_Specific(RHS)))) &&
(ExtendedCmpPredicate == ICmpInst::ICMP_NE ||
- ICmpInst::getSwappedPredicate(ExtendedCmpPredicate) == Pred))
+ ICmpInst::getSwappedPredicate(ExtendedCmpPredicate) == Pred)) {
+ FV_RHS = RHS;
Replace = true;
+ }
// (x == y) ? 0 : (x > y ? 1 : -1)
CmpPredicate FalseBranchSelectPredicate;
@@ -3624,6 +3679,7 @@ Instruction *InstCombinerImpl::foldSelectToCmp(SelectInst &SI) {
if (ICmpInst::isGT(FalseBranchSelectPredicate) && InnerTV->isOne() &&
InnerFV->isAllOnes()) {
IsSigned = ICmpInst::isSigned(FalseBranchSelectPredicate);
+ FV_RHS = RHS;
Replace = true;
}
}
@@ -3631,7 +3687,7 @@ Instruction *InstCombinerImpl::foldSelectToCmp(SelectInst &SI) {
Intrinsic::ID IID = IsSigned ? Intrinsic::scmp : Intrinsic::ucmp;
if (Replace)
return replaceInstUsesWith(
- SI, Builder.CreateIntrinsic(SI.getType(), IID, {LHS, RHS}));
+ SI, Builder.CreateIntrinsic(SI.getType(), IID, {LHS, FV_RHS}));
return nullptr;
}
diff --git a/llvm/test/Transforms/InstCombine/select-to-cmp.ll b/llvm/test/Transforms/InstCombine/select-to-cmp.ll
index 73ee037f6f22a..deaa9879394de 100644
--- a/llvm/test/Transforms/InstCombine/select-to-cmp.ll
+++ b/llvm/test/Transforms/InstCombine/select-to-cmp.ll
@@ -61,11 +61,7 @@ define i32 @scmp_x_y_from_gt_sext_lt(i32 %x, i32 %y) {
define i32 @ucmp_x_y_from_le_sub_zext_ne(i32 %x, i32 %y) {
; CHECK-LABEL: define i32 @ucmp_x_y_from_le_sub_zext_ne(
; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
-; CHECK-NEXT: [[YM1:%.*]] = add i32 [[Y]], -1
-; CHECK-NEXT: [[CMP1_NOT:%.*]] = icmp ugt i32 [[X]], [[YM1]]
-; CHECK-NEXT: [[NEQ:%.*]] = icmp ne i32 [[X]], [[Y]]
-; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[NEQ]] to i32
-; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP1_NOT]], i32 [[ZEXT]], i32 -1
+; CHECK-NEXT: [[SEL:%.*]] = call i32 @llvm.ucmp.i32.i32(i32 [[X]], i32 [[Y]])
; CHECK-NEXT: ret i32 [[SEL]]
;
%ym1 = sub i32 %y, 1
@@ -80,11 +76,7 @@ define i32 @ucmp_x_y_from_le_sub_zext_ne(i32 %x, i32 %y) {
define i32 @ucmp_x_y_from_le_sub_zext_gt(i32 %x, i32 %y) {
; CHECK-LABEL: define i32 @ucmp_x_y_from_le_sub_zext_gt(
; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
-; CHECK-NEXT: [[YM1:%.*]] = add i32 [[Y]], -1
-; CHECK-NEXT: [[CMP1_NOT:%.*]] = icmp ugt i32 [[X]], [[YM1]]
-; CHECK-NEXT: [[GT:%.*]] = icmp ugt i32 [[X]], [[Y]]
-; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[GT]] to i32
-; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP1_NOT]], i32 [[ZEXT]], i32 -1
+; CHECK-NEXT: [[SEL:%.*]] = call i32 @llvm.ucmp.i32.i32(i32 [[X]], i32 [[Y]])
; CHECK-NEXT: ret i32 [[SEL]]
;
%ym1 = sub i32 %y, 1
@@ -99,11 +91,7 @@ define i32 @ucmp_x_y_from_le_sub_zext_gt(i32 %x, i32 %y) {
define i32 @ucmp_x_y_from_ge_add_sext_ne(i32 %x, i32 %y) {
; CHECK-LABEL: define i32 @ucmp_x_y_from_ge_add_sext_ne(
; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
-; CHECK-NEXT: [[YP1:%.*]] = add i32 [[Y]], 1
-; CHECK-NEXT: [[CMP1_NOT:%.*]] = icmp ult i32 [[X]], [[YP1]]
-; CHECK-NEXT: [[NEQ:%.*]] = icmp ne i32 [[X]], [[Y]]
-; CHECK-NEXT: [[SEXT:%.*]] = sext i1 [[NEQ]] to i32
-; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP1_NOT]], i32 [[SEXT]], i32 1
+; CHECK-NEXT: [[SEL:%.*]] = call i32 @llvm.ucmp.i32.i32(i32 [[X]], i32 [[Y]])
; CHECK-NEXT: ret i32 [[SEL]]
;
%yp1 = add i32 %y, 1
@@ -118,11 +106,7 @@ define i32 @ucmp_x_y_from_ge_add_sext_ne(i32 %x, i32 %y) {
define i32 @ucmp_x_y_from_ge_add_sext_lt(i32 %x, i32 %y) {
; CHECK-LABEL: define i32 @ucmp_x_y_from_ge_add_sext_lt(
; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
-; CHECK-NEXT: [[YP1:%.*]] = add i32 [[Y]], 1
-; CHECK-NEXT: [[CMP1_NOT:%.*]] = icmp ult i32 [[X]], [[YP1]]
-; CHECK-NEXT: [[LT:%.*]] = icmp ult i32 [[X]], [[Y]]
-; CHECK-NEXT: [[SEXT:%.*]] = sext i1 [[LT]] to i32
-; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP1_NOT]], i32 [[SEXT]], i32 1
+; CHECK-NEXT: [[SEL:%.*]] = call i32 @llvm.ucmp.i32.i32(i32 [[X]], i32 [[Y]])
; CHECK-NEXT: ret i32 [[SEL]]
;
%yp1 = add i32 %y, 1
@@ -137,11 +121,7 @@ define i32 @ucmp_x_y_from_ge_add_sext_lt(i32 %x, i32 %y) {
define i32 @scmp_x_y_from_gt_sub_zext_ne(i32 %x, i32 %y) {
; CHECK-LABEL: define i32 @scmp_x_y_from_gt_sub_zext_ne(
; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
-; CHECK-NEXT: [[YM1:%.*]] = add i32 [[Y]], -1
-; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[X]], [[YM1]]
-; CHECK-NEXT: [[NE:%.*]] = icmp ne i32 [[X]], [[Y]]
-; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[NE]] to i32
-; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP1]], i32 [[ZEXT]], i32 -1
+; CHECK-NEXT: [[SEL:%.*]] = call i32 @llvm.scmp.i32.i32(i32 [[X]], i32 [[Y]])
; CHECK-NEXT: ret i32 [[SEL]]
;
%ym1 = sub i32 %y, 1
@@ -156,11 +136,7 @@ define i32 @scmp_x_y_from_gt_sub_zext_ne(i32 %x, i32 %y) {
define i32 @ucmp_x_y_from_gt_sub_zext_gt(i32 %x, i32 %y) {
; CHECK-LABEL: define i32 @ucmp_x_y_from_gt_sub_zext_gt(
; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
-; CHECK-NEXT: [[YM1:%.*]] = add i32 [[Y]], -1
-; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 [[X]], [[YM1]]
-; CHECK-NEXT: [[GT:%.*]] = icmp ugt i32 [[X]], [[Y]]
-; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[GT]] to i32
-; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP1]], i32 [[ZEXT]], i32 -1
+; CHECK-NEXT: [[SEL:%.*]] = call i32 @llvm.ucmp.i32.i32(i32 [[X]], i32 [[Y]])
; CHECK-NEXT: ret i32 [[SEL]]
;
%ym1 = sub i32 %y, 1
@@ -175,11 +151,7 @@ define i32 @ucmp_x_y_from_gt_sub_zext_gt(i32 %x, i32 %y) {
define i32 @scmp_x_y_from_lt_add_sext_ne(i32 %x, i32 %y) {
; CHECK-LABEL: define i32 @scmp_x_y_from_lt_add_sext_ne(
; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
-; CHECK-NEXT: [[YP1:%.*]] = add i32 [[Y]], 1
-; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[X]], [[YP1]]
-; CHECK-NEXT: [[NE:%.*]] = icmp ne i32 [[X]], [[Y]]
-; CHECK-NEXT: [[SEXT:%.*]] = sext i1 [[NE]] to i32
-; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP1]], i32 [[SEXT]], i32 1
+; CHECK-NEXT: [[SEL:%.*]] = call i32 @llvm.scmp.i32.i32(i32 [[X]], i32 [[Y]])
; CHECK-NEXT: ret i32 [[SEL]]
;
%yp1 = add i32 %y, 1
@@ -194,11 +166,7 @@ define i32 @scmp_x_y_from_lt_add_sext_ne(i32 %x, i32 %y) {
define i32 @ucmp_x_y_from_lt_add_sext_lt(i32 %x, i32 %y) {
; CHECK-LABEL: define i32 @ucmp_x_y_from_lt_add_sext_lt(
; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
-; CHECK-NEXT: [[YP1:%.*]] = add i32 [[Y]], 1
-; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[X]], [[YP1]]
-; CHECK-NEXT: [[LT:%.*]] = icmp ult i32 [[X]], [[Y]]
-; CHECK-NEXT: [[SEXT:%.*]] = sext i1 [[LT]] to i32
-; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP1]], i32 [[SEXT]], i32 1
+; CHECK-NEXT: [[SEL:%.*]] = call i32 @llvm.ucmp.i32.i32(i32 [[X]], i32 [[Y]])
; CHECK-NEXT: ret i32 [[SEL]]
;
%yp1 = add i32 %y, 1
@@ -214,10 +182,7 @@ define i32 @ucmp_x_y_from_lt_add_sext_lt(i32 %x, i32 %y) {
define i32 @scmp_x_0_inverted(i32 %x) {
; CHECK-LABEL: define i32 @scmp_x_0_inverted(
; CHECK-SAME: i32 [[X:%.*]]) {
-; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[X]], 0
-; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP4]] to i32
-; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i32 [[X]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 -1
+; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.scmp.i32.i32(i32 [[X]], i32 0)
; CHECK-NEXT: ret i32 [[TMP1]]
;
%2 = icmp ne i32 %x, 0
@@ -230,10 +195,7 @@ define i32 @scmp_x_0_inverted(i32 %x) {
define i32 @scmp_x_neg_6_sgt_form(i32 %x) {
; CHECK-LABEL: define i32 @scmp_x_neg_6_sgt_form(
; CHECK-SAME: i32 [[X:%.*]]) {
-; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[X]], -6
-; CHECK-NEXT: [[NE:%.*]] = icmp ne i32 [[X]], -5
-; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[NE]] to i32
-; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP1]], i32 [[ZEXT]], i32 -1
+; CHECK-NEXT: [[SEL:%.*]] = call i32 @llvm.scmp.i32.i32(i32 [[X]], i32 -5)
; CHECK-NEXT: ret i32 [[SEL]]
;
%cmp1 = icmp sgt i32 %x, -6
@@ -246,10 +208,7 @@ define i32 @scmp_x_neg_6_sgt_form(i32 %x) {
define i32 @ucmp_x_5_ult_form(i32 %x) {
; CHECK-LABEL: define i32 @ucmp_x_5_ult_form(
; CHECK-SAME: i32 [[X:%.*]]) {
-; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[X]], 6
-; CHECK-NEXT: [[NE:%.*]] = icmp ne i32 [[X]], 5
-; CHECK-NEXT: [[SEXT:%.*]] = sext i1 [[NE]] to i32
-; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP1]], i32 [[SEXT]], i32 1
+; CHECK-NEXT: [[SEL:%.*]] = call i32 @llvm.ucmp.i32.i32(i32 [[X]], i32 5)
; CHECK-NEXT: ret i32 [[SEL]]
;
%cmp1 = icmp ult i32 %x, 6
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