[llvm] [RISCV] Add new tests for RISCV zicond extension (PR #143580)

[Mikhail Gudim via llvm-commits]

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@@ -0,0 +1,181 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv32 -O2 -verify-machineinstrs -mattr=+b,+zicond < %s | FileCheck %s -check-prefix=RV32ZICOND
+; RUN: llc -mtriple=riscv64 -O2 -verify-machineinstrs -mattr=+b,+zicond < %s | FileCheck %s -check-prefix=RV64ZICOND
+
+; (and (icmp x. 0, ne), (icmp y, 0, ne)) -> (czero.eqz (icmp x, 0, ne), y)
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mgudim wrote:

the type on lhs is i1, but rhs is the type of y. So we need additional instruction to turn rhs into i1, so it will also be 3 instructions, no?

https://github.com/llvm/llvm-project/pull/143580