[llvm] a6ace28 - [X86] combineConcatVectorOps - ensure we're only concatenating v2f64 generic shuffles into vXf64 vshufpd

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2025-06-11T08:07:30+01:00
New Revision: a6ace2801e8900a6fe8c3b8295938f3b3c1e4466

URL: https://github.com/llvm/llvm-project/commit/a6ace2801e8900a6fe8c3b8295938f3b3c1e4466
DIFF: https://github.com/llvm/llvm-project/commit/a6ace2801e8900a6fe8c3b8295938f3b3c1e4466.diff

LOG: [X86] combineConcatVectorOps - ensure we're only concatenating v2f64 generic shuffles into vXf64 vshufpd

Identified while triaging #143606 - we can't concat v4f64 lhs/rhs subvecs and then expect the v2f64 operands to be in the correct place for VSHUFPD

Test coverage will follow

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 96be91256915d..8bcd8670879a9 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -59383,7 +59383,8 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
 
   // We can always convert per-lane vXf64 shuffles into VSHUFPD.
   if (!IsSplat &&
-      (VT == MVT::v4f64 || (VT == MVT::v8f64 && Subtarget.useAVX512Regs())) &&
+      ((NumOps == 2 && VT == MVT::v4f64) ||
+       (NumOps == 4 && VT == MVT::v8f64 && Subtarget.useAVX512Regs())) &&
       all_of(Ops, [](SDValue Op) { return Op.hasOneUse(); })) {
     // Collect the individual per-lane v2f64/v4f64 shuffles.
     MVT OpVT = Ops[0].getSimpleValueType();