[llvm] AMDGPU/GFX12: Fix s_barrier_signal_isfirst for single-wave workgroups (PR #143634)

[Nicolai Hähnle via llvm-commits]

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@@ -5411,6 +5411,14 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
     MI.eraseFromParent();
     return BB;
   }
+  case AMDGPU::S_BARRIER_SIGNAL_ISFIRST_IMM: {
+    // Set SCC to true, in case the barrier instruction gets converted to a NOP.
+    BuildMI(*BB, MI.getIterator(), MI.getDebugLoc(),
+            TII->get(AMDGPU::S_CMP_EQ_U32))
+        .addImm(0)
+        .addImm(0);
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nhaehnle wrote:

Perhaps the comment isn't clear enough. The point is that *hardware* at runtime can convert the barrier instructions into NOPs.

I suppose we could remove the barrier instruction ourselves if the kernel size is statically known to be too small, but I would we hope we'd do that earlier in LLVM IR since it might expose more optimization opportunities.

https://github.com/llvm/llvm-project/pull/143634