[llvm] [BPF] Report warning for some insn imm requiring int range in inline asm (PR #142989)

[via llvm-commits]

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@@ -67,12 +71,53 @@ class BPFMCCodeEmitter : public MCCodeEmitter {
 
 MCCodeEmitter *llvm::createBPFMCCodeEmitter(const MCInstrInfo &MCII,
                                             MCContext &Ctx) {
-  return new BPFMCCodeEmitter(MCII, *Ctx.getRegisterInfo(), true);
+  return new BPFMCCodeEmitter(MCII, *Ctx.getRegisterInfo(), true, Ctx);
 }
 
 MCCodeEmitter *llvm::createBPFbeMCCodeEmitter(const MCInstrInfo &MCII,
                                               MCContext &Ctx) {
-  return new BPFMCCodeEmitter(MCII, *Ctx.getRegisterInfo(), false);
+  return new BPFMCCodeEmitter(MCII, *Ctx.getRegisterInfo(), false, Ctx);
+}
+
+void BPFMCCodeEmitter::checkImmRange(const MCInst &MI, int64_t Imm) const {
+  switch (MI.getOpcode()) {
+  // ALU/ALU64 insns
+  case BPF::MOV_ri:
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eddyz87 wrote:

There are also the following `*_ri_32` instructions not listed here:

```
ADD_ri_32
AND_ri_32
DIV_ri_32
JEQ_ri_32
JNE_ri_32
JSET_ri_32
JSGE_ri_32
JSGT_ri_32
JSLE_ri_32
JSLT_ri_32
JUGE_ri_32
JUGT_ri_32
JULE_ri_32
JULT_ri_32
MOD_ri_32
MOV_32_64
MOV_ri_32
MUL_ri_32
NEG_32
OR_ri_32
SDIV_ri_32
SLL_ri_32
SMOD_ri_32
SRA_ri_32
SRL_ri_32
SUB_ri_32
XOR_ri_32
```

Are these omitted on purpose?
Also, maybe issue a warning if operand of an unsigned comparison is not in [0..UINT_MAX] range?

https://github.com/llvm/llvm-project/pull/142989