[llvm] [RISCV] Add new tests for RISCV zicond extension (PR #143580)
Ryan Buchner via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 10 13:38:18 PDT 2025
https://github.com/bababuck updated https://github.com/llvm/llvm-project/pull/143580
>From 98eed72942b21a62661d14326d3702a0f7a3bf3c Mon Sep 17 00:00:00 2001
From: bababuck <buchner.ryan at gmail.com>
Date: Sun, 25 May 2025 11:28:59 -0700
Subject: [PATCH] [RISCV] Add new tests for RISCV zicond extension
---
llvm/test/CodeGen/RISCV/zicond-opts.ll | 153 +++++++++++++++++++++++++
1 file changed, 153 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/zicond-opts.ll
diff --git a/llvm/test/CodeGen/RISCV/zicond-opts.ll b/llvm/test/CodeGen/RISCV/zicond-opts.ll
new file mode 100644
index 0000000000000..c1db993cbb30e
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/zicond-opts.ll
@@ -0,0 +1,153 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv32 -O2 -verify-machineinstrs -mattr=+b,+zicond < %s | FileCheck %s -check-prefix=RV32ZICOND
+; RUN: llc -mtriple=riscv64 -O2 -verify-machineinstrs -mattr=+b,+zicond < %s | FileCheck %s -check-prefix=RV64ZICOND
+
+; (and (icmp x. 0, ne), (icmp y, 0, ne)) -> (czero.eqz (icmp x, 0, ne), y)
+define i32 @icmp_and(i64 %0, i64 %1) {
+; RV32ZICOND-LABEL: icmp_and:
+; RV32ZICOND: # %bb.0:
+; RV32ZICOND-NEXT: or a2, a2, a3
+; RV32ZICOND-NEXT: or a0, a0, a1
+; RV32ZICOND-NEXT: snez a1, a2
+; RV32ZICOND-NEXT: snez a0, a0
+; RV32ZICOND-NEXT: and a0, a0, a1
+; RV32ZICOND-NEXT: ret
+;
+; RV64ZICOND-LABEL: icmp_and:
+; RV64ZICOND: # %bb.0:
+; RV64ZICOND-NEXT: snez a1, a1
+; RV64ZICOND-NEXT: snez a0, a0
+; RV64ZICOND-NEXT: and a0, a0, a1
+; RV64ZICOND-NEXT: ret
+ %3 = icmp ne i64 %1, 0
+ %4 = icmp ne i64 %0, 0
+ %5 = and i1 %4, %3
+ %6 = zext i1 %5 to i32
+ ret i32 %6
+}
+
+; (and (and (icmp x, 0, ne), (icmp y, 0, ne)), (icmp z, 0, ne)) -> (czero.eqo (czero.eqz (icmp x, 0, ne), y), z)
+define i32 @icmp_and_and(i64 %0, i64 %1, i64 %2) {
+; RV32ZICOND-LABEL: icmp_and_and:
+; RV32ZICOND: # %bb.0:
+; RV32ZICOND-NEXT: or a2, a2, a3
+; RV32ZICOND-NEXT: or a0, a0, a1
+; RV32ZICOND-NEXT: or a4, a4, a5
+; RV32ZICOND-NEXT: snez a1, a2
+; RV32ZICOND-NEXT: snez a0, a0
+; RV32ZICOND-NEXT: and a0, a1, a0
+; RV32ZICOND-NEXT: snez a1, a4
+; RV32ZICOND-NEXT: and a0, a1, a0
+; RV32ZICOND-NEXT: ret
+;
+; RV64ZICOND-LABEL: icmp_and_and:
+; RV64ZICOND: # %bb.0:
+; RV64ZICOND-NEXT: snez a1, a1
+; RV64ZICOND-NEXT: snez a0, a0
+; RV64ZICOND-NEXT: and a0, a1, a0
+; RV64ZICOND-NEXT: snez a1, a2
+; RV64ZICOND-NEXT: and a0, a1, a0
+; RV64ZICOND-NEXT: ret
+ %4 = icmp ne i64 %1, 0
+ %5 = icmp ne i64 %0, 0
+ %6 = and i1 %4, %5
+ %7 = icmp ne i64 %2, 0
+ %8 = and i1 %7, %6
+ %9 = zext i1 %8 to i32
+ ret i32 %9
+}
+
+; (select c, u, rotl(u, t)) -> (rotl (czero_nez t, c), u)
+define i64 @rotate_l_eqz(i64 %0, i64 %1, i64 %2, i64 %3) {
+; RV32ZICOND-LABEL: rotate_l_eqz:
+; RV32ZICOND: # %bb.0:
+; RV32ZICOND-NEXT: or a0, a6, a7
+; RV32ZICOND-NEXT: bexti a1, a4, 5
+; RV32ZICOND-NEXT: not a5, a4
+; RV32ZICOND-NEXT: czero.nez a6, a3, a1
+; RV32ZICOND-NEXT: czero.eqz a7, a2, a1
+; RV32ZICOND-NEXT: czero.nez t0, a2, a1
+; RV32ZICOND-NEXT: czero.eqz a1, a3, a1
+; RV32ZICOND-NEXT: czero.nez a2, a2, a0
+; RV32ZICOND-NEXT: czero.nez a3, a3, a0
+; RV32ZICOND-NEXT: or a6, a7, a6
+; RV32ZICOND-NEXT: or a1, a1, t0
+; RV32ZICOND-NEXT: sll a7, a6, a4
+; RV32ZICOND-NEXT: srli t0, a1, 1
+; RV32ZICOND-NEXT: sll a1, a1, a4
+; RV32ZICOND-NEXT: srli a4, a6, 1
+; RV32ZICOND-NEXT: srl a6, t0, a5
+; RV32ZICOND-NEXT: srl a4, a4, a5
+; RV32ZICOND-NEXT: or a5, a7, a6
+; RV32ZICOND-NEXT: or a1, a1, a4
+; RV32ZICOND-NEXT: czero.eqz a1, a1, a0
+; RV32ZICOND-NEXT: czero.eqz a4, a5, a0
+; RV32ZICOND-NEXT: or a0, a2, a1
+; RV32ZICOND-NEXT: or a1, a3, a4
+; RV32ZICOND-NEXT: ret
+;
+; RV64ZICOND-LABEL: rotate_l_eqz:
+; RV64ZICOND: # %bb.0:
+; RV64ZICOND-NEXT: rol a0, a1, a2
+; RV64ZICOND-NEXT: czero.nez a1, a1, a3
+; RV64ZICOND-NEXT: czero.eqz a0, a0, a3
+; RV64ZICOND-NEXT: or a0, a1, a0
+; RV64ZICOND-NEXT: ret
+ %5 = icmp eq i64 %3, 0
+ %6 = call i64 @llvm.fshl.i64(i64 %1, i64 %1, i64 %2)
+ %7 = select i1 %5, i64 %1, i64 %6
+ ret i64 %7
+}
+
+; (select cond, const, t) -> (add (czero_nez t - const, cond), const)
+define i64 @select_imm_reg(i64 %0, i64 %1) {
+; RV32ZICOND-LABEL: select_imm_reg:
+; RV32ZICOND: # %bb.0:
+; RV32ZICOND-NEXT: xori a0, a0, 2
+; RV32ZICOND-NEXT: or a1, a0, a1
+; RV32ZICOND-NEXT: li a0, 3
+; RV32ZICOND-NEXT: czero.eqz a2, a2, a1
+; RV32ZICOND-NEXT: czero.nez a0, a0, a1
+; RV32ZICOND-NEXT: or a0, a0, a2
+; RV32ZICOND-NEXT: czero.eqz a1, a3, a1
+; RV32ZICOND-NEXT: ret
+;
+; RV64ZICOND-LABEL: select_imm_reg:
+; RV64ZICOND: # %bb.0:
+; RV64ZICOND-NEXT: addi a0, a0, -2
+; RV64ZICOND-NEXT: li a2, 3
+; RV64ZICOND-NEXT: czero.eqz a1, a1, a0
+; RV64ZICOND-NEXT: czero.nez a0, a2, a0
+; RV64ZICOND-NEXT: or a0, a0, a1
+; RV64ZICOND-NEXT: ret
+ %3 = icmp eq i64 %0, 2
+ %4 = select i1 %3, i64 3, i64 %1
+ ret i64 %4
+}
+
+; (select c, (and f, ~x), f) -> (andn f, (czero_nez x, c))
+define i64 @test_inv_and_eqz(i64 %1, i64 %2, i64 %3) {
+; RV32ZICOND-LABEL: test_inv_and_eqz:
+; RV32ZICOND: # %bb.0: # %entry
+; RV32ZICOND-NEXT: or a4, a4, a5
+; RV32ZICOND-NEXT: snez a4, a4
+; RV32ZICOND-NEXT: addi a4, a4, -1
+; RV32ZICOND-NEXT: orn a3, a4, a3
+; RV32ZICOND-NEXT: orn a2, a4, a2
+; RV32ZICOND-NEXT: and a0, a2, a0
+; RV32ZICOND-NEXT: and a1, a3, a1
+; RV32ZICOND-NEXT: ret
+;
+; RV64ZICOND-LABEL: test_inv_and_eqz:
+; RV64ZICOND: # %bb.0: # %entry
+; RV64ZICOND-NEXT: czero.nez a2, a0, a2
+; RV64ZICOND-NEXT: andn a0, a0, a1
+; RV64ZICOND-NEXT: or a0, a0, a2
+; RV64ZICOND-NEXT: ret
+entry:
+ %4 = icmp ne i64 %3, 0
+ %5 = xor i64 %2, -1
+ %6 = select i1 %4, i64 %5, i64 -1
+ %7 = and i64 %6, %1
+ ret i64 %7
+}
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