[llvm] [AArch64] Fix #94909: Optimize vector fmul(sitofp(x), 0.5) -> scvtf(x, 2) (PR #141480)

[JP Hafer via llvm-commits]

jph-13 wrote:

This is incomplete, but I could really use some help. I have never touched tablegen before this and feel I am making it way too difficult. 

I am having specific issues with the smaller registers and sizes (are my matchers too restrictive?). I left in commented out vNi16 code for I can't get any of it to not conflict. The v1i32 and v1i64 are also escaping me. As for the f16 implementations, it seems I need to handle a sext, but I figure the rest should be working first. 

I could use any comments or guidance folks have.

Thanks.

https://github.com/llvm/llvm-project/pull/141480