[llvm] [NVPTX] support packed f32 instructions for sm_100+ (PR #126337)

[Alex MacLean via llvm-commits]

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@@ -1245,7 +1251,9 @@ bool NVPTXDAGToDAGISel::tryLDGLDU(SDNode *N) {
     EltVT = EltVT.getVectorElementType();
     // vectors of 8/16bits type are loaded/stored as multiples of v4i8/v2x16
     // elements.
-    if ((EltVT == MVT::f16 && OrigType == MVT::v2f16) ||
+    // Packed vector types are loaded/stored in a single register.
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AlexMaclean wrote:

I suppose this is fine but it seems like the whole chunk of code that this is part of should be removed. We should be doing this more like how we select loads and stores where the number of elements and type are derived from the types the node produces.

https://github.com/llvm/llvm-project/pull/126337