[llvm] Handle VECREDUCE intrinsics in NVPTX backend (PR #136253)

[Princeton Ferro via llvm-commits]

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@@ -83,6 +83,8 @@ class NVPTXTTIImpl : public BasicTTIImplBase<NVPTXTTIImpl> {
   }
   unsigned getMinVectorRegisterBitWidth() const { return 32; }
 
+  bool shouldExpandReduction(const IntrinsicInst *II) const { return false; }
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Prince781 wrote:

To rephrase:

There are three types of reductions possible: sequential (`a + b + c + d`), shuffle (`(a + c) + (b + d)`), and tree (`(a + b) + (c + d)`). `ExpandReductions` pass and SelectionDAG only supports the first two. If we handle reductions in the NVPTX backend, we can support all three.

https://github.com/llvm/llvm-project/pull/136253