[llvm] [LLVM][CodeGen][AArch64] Lower vector-(de)interleave to multi-register uzp/zip instructions. (PR #143128)

[Paul Walker via llvm-commits]

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@@ -29210,6 +29210,28 @@ AArch64TargetLowering::LowerVECTOR_DEINTERLEAVE(SDValue Op,
   assert(OpVT.isScalableVector() &&
          "Expected scalable vector in LowerVECTOR_DEINTERLEAVE.");
 
+  // Are multi-register uzp instructions available?
+  if (Subtarget->hasSME2() && Subtarget->isStreaming() &&
+      OpVT.getVectorElementType() != MVT::i1) {
+    Intrinsic::ID IntID;
+    switch (Op->getNumOperands()) {
+    default:
+      return SDValue();
+    case 2:
+      IntID = Intrinsic::aarch64_sve_uzp_x2;
+      break;
+    case 4:
+      IntID = Intrinsic::aarch64_sve_uzp_x4;
+      break;
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paulwalker-arm wrote:

Oh yes :(  I've updated the check to bail when the minimum SVE vector length is not known to be 256-bit or larger.

https://github.com/llvm/llvm-project/pull/143128