[llvm] [SPIRV] Add intrinsic to represent spec constants (PR #143179)
Steven Perron via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 9 11:48:00 PDT 2025
https://github.com/s-perron updated https://github.com/llvm/llvm-project/pull/143179
>From 31ebd1fc9821291c3ce43449125ddd39be3765e0 Mon Sep 17 00:00:00 2001
From: Steven Perron <stevenperron at google.com>
Date: Fri, 6 Jun 2025 09:33:01 -0400
Subject: [PATCH 1/2] [SPIRV] Add intrinsic to represent spec constants
SPIR-V has the concept of a specialization constant. See the [SPIR-V spec](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#_specialization_2)
for details.
This commit adds the ability for the SPIR-V backend to generate the base
specialization constants (OpSpecConstant, OpSpecConstantFalse, and
OpSpecConstantTrue).
This will be used by HLSL.
---
llvm/include/llvm/IR/IntrinsicsSPIRV.td | 4 +
.../Target/SPIRV/SPIRVInstructionSelector.cpp | 98 ++++++++++++++++++-
.../CodeGen/SPIRV/constant/spec-constant.ll | 81 +++++++++++++++
3 files changed, 182 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/SPIRV/constant/spec-constant.ll
diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
index 8d984d6ce58df..01f335a2ad2b9 100644
--- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td
+++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
@@ -137,6 +137,10 @@ let TargetPrefix = "spv" in {
: DefaultAttrsIntrinsic<[llvm_anyptr_ty], [llvm_any_ty, llvm_i32_ty],
[IntrNoMem]>;
+ def int_spv_get_specialization_constant
+ : DefaultAttrsIntrinsic<[llvm_any_ty], [llvm_i32_ty, LLVMMatchType<0>],
+ [IntrNoMem, IntrWillReturn]>;
+
// Read a value from the image buffer. It does not translate directly to a
// single OpImageRead because the result type is not necessarily a 4 element
// vector.
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 2dae0721886c7..f4a73f59196f3 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -296,7 +296,22 @@ class SPIRVInstructionSelector : public InstructionSelector {
bool selectImageWriteIntrinsic(MachineInstr &I) const;
bool selectResourceGetPointer(Register &ResVReg, const SPIRVType *ResType,
MachineInstr &I) const;
-
+ bool selectGetSpecializationConstant(Register &ResVReg,
+ const SPIRVType *ResType,
+ MachineInstr &I) const;
+
+ bool buildSpecConstant(llvm::MachineInstr &I, llvm::Register &ResVReg,
+ llvm::SPIRVType *ResType,
+ llvm::APInt &DefaultValue) const;
+
+ APInt getSpecConstantDefaultValue(llvm::MachineInstr &I) const;
+
+ bool buildBoolSpecConstant(Register &ResVReg, const SPIRVType *ResType,
+ bool DefaultValue, MachineInstr &I) const;
+ bool buildIntegerSpecConstant(Register &ResVReg, const SPIRVType *ResType,
+ uint32_t DefaultValue, MachineInstr &I) const;
+ bool buildIntegerSpecConstant(Register &ResVReg, const SPIRVType *ResType,
+ uint64_t DefaultValue, MachineInstr &I) const;
// Utilities
std::pair<Register, bool>
buildI32Constant(uint32_t Val, MachineInstr &I,
@@ -3192,6 +3207,9 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
case Intrinsic::spv_resource_getpointer: {
return selectResourceGetPointer(ResVReg, ResType, I);
}
+ case Intrinsic::spv_get_specialization_constant: {
+ return selectGetSpecializationConstant(ResVReg, ResType, I);
+ }
case Intrinsic::spv_discard: {
return selectDiscard(ResVReg, ResType, I);
}
@@ -3309,6 +3327,84 @@ bool SPIRVInstructionSelector::selectResourceGetPointer(
.constrainAllUses(TII, TRI, RBI);
}
+bool SPIRVInstructionSelector::buildBoolSpecConstant(Register &ResVReg,
+ const SPIRVType *ResType,
+ bool DefaultValue,
+ MachineInstr &I) const {
+ uint32_t Opc =
+ DefaultValue ? SPIRV::OpSpecConstantTrue : SPIRV::OpSpecConstantFalse;
+ return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc))
+ .addDef(ResVReg)
+ .addUse(GR.getSPIRVTypeID(ResType))
+ .constrainAllUses(TII, TRI, RBI);
+}
+
+bool SPIRVInstructionSelector::buildIntegerSpecConstant(
+ Register &ResVReg, const SPIRVType *ResType, uint32_t DefaultValue,
+ MachineInstr &I) const {
+ return BuildMI(*I.getParent(), I, I.getDebugLoc(),
+ TII.get(SPIRV::OpSpecConstant))
+ .addDef(ResVReg)
+ .addUse(GR.getSPIRVTypeID(ResType))
+ .addImm(DefaultValue)
+ .constrainAllUses(TII, TRI, RBI);
+}
+
+bool SPIRVInstructionSelector::buildIntegerSpecConstant(
+ Register &ResVReg, const SPIRVType *ResType, uint64_t DefaultValue,
+ MachineInstr &I) const {
+ return BuildMI(*I.getParent(), I, I.getDebugLoc(),
+ TII.get(SPIRV::OpSpecConstant))
+ .addDef(ResVReg)
+ .addUse(GR.getSPIRVTypeID(ResType))
+ .addImm(DefaultValue & 0xFFFFFFFF)
+ .addImm(DefaultValue >> 32)
+ .constrainAllUses(TII, TRI, RBI);
+}
+
+bool SPIRVInstructionSelector::selectGetSpecializationConstant(
+ Register &ResVReg, const SPIRVType *ResType, MachineInstr &I) const {
+ uint32_t Id = foldImm(I.getOperand(2), MRI);
+ bool R = false;
+ APInt DefaultValue = getSpecConstantDefaultValue(I);
+ if (ResType->getOpcode() == SPIRV::OpTypeBool) {
+ R = buildBoolSpecConstant(ResVReg, ResType, DefaultValue.getBoolValue(), I);
+ } else {
+ R = buildSpecConstant(I, ResVReg, ResType, DefaultValue);
+ }
+ if (!R) {
+ return false;
+ }
+ buildOpDecorate(ResVReg, I, TII, SPIRV::Decoration::SpecId, {Id});
+ return R;
+}
+
+bool SPIRVInstructionSelector::buildSpecConstant(
+ llvm::MachineInstr &I, llvm::Register &ResVReg, llvm::SPIRVType *ResType,
+ llvm::APInt &DefaultValue) const {
+ auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(),
+ TII.get(SPIRV::OpSpecConstant))
+ .addDef(ResVReg)
+ .addUse(GR.getSPIRVTypeID(ResType));
+ addNumImm(DefaultValue, MIB);
+ return MIB.constrainAllUses(TII, TRI, RBI);
+}
+
+APInt SPIRVInstructionSelector::getSpecConstantDefaultValue(
+ llvm::MachineInstr &I) const {
+ APInt DefaultValue;
+ Register DefaultValueReg = I.getOperand(3).getReg();
+ auto *D = getDefInstrMaybeConstant(DefaultValueReg, MRI);
+ const auto &MO = D->getOperand(1);
+ if (MO.isCImm()) {
+ DefaultValue = MO.getCImm()->getValue();
+ } else {
+ assert(MO.isFPImm() && "");
+ DefaultValue = MO.getFPImm()->getValue().bitcastToAPInt();
+ }
+ return DefaultValue;
+}
+
bool SPIRVInstructionSelector::extractSubvector(
Register &ResVReg, const SPIRVType *ResType, Register &ReadReg,
MachineInstr &InsertionPoint) const {
diff --git a/llvm/test/CodeGen/SPIRV/constant/spec-constant.ll b/llvm/test/CodeGen/SPIRV/constant/spec-constant.ll
new file mode 100644
index 0000000000000..a30fd326c985a
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/constant/spec-constant.ll
@@ -0,0 +1,81 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv1.6-unknown-vulkan1.3-compute %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv1.6-unknown-vulkan1.3-compute %s -o - -filetype=obj | spirv-val %}
+
+; CHECK-DAG: OpDecorate [[bool_const:%[0-9]+]] SpecId 1
+; CHECK-DAG: OpDecorate [[short_const:%[0-9]+]] SpecId 2
+; CHECK-DAG: OpDecorate [[int_const:%[0-9]+]] SpecId 3
+; CHECK-DAG: OpDecorate [[long_const:%[0-9]+]] SpecId 4
+; CHECK-DAG: OpDecorate [[float_const:%[0-9]+]] SpecId 8
+; CHECK-DAG: OpDecorate [[double_const:%[0-9]+]] SpecId 9
+; CHECK-DAG: OpDecorate [[enum_const:%[0-9]+]] SpecId 10
+
+; CHECK-DAG: [[bool_const]] = OpSpecConstantTrue {{%[0-9]+}}
+; CHECK-DAG: [[short_const]] = OpSpecConstant {{%[0-9]+}} 4
+; CHECK-DAG: [[int_const]] = OpSpecConstant {{%[0-9]+}} 5
+; CHECK-DAG: [[long_const]] = OpSpecConstant {{%[0-9]+}} 8
+; CHECK-DAG: [[float_const]] = OpSpecConstant {{%[0-9]+}} 1112014848
+; CHECK-DAG: [[double_const]] = OpSpecConstant {{%[0-9]+}} 0 1079574528
+; CHECK-DAG: [[enum_const]] = OpSpecConstant {{%[0-9]+}} 30
+
+ at _ZL10bool_const = internal addrspace(10) global i32 0, align 4
+ at _ZL11short_const = internal addrspace(10) global i16 0, align 2
+ at _ZL9int_const = internal addrspace(10) global i32 0, align 4
+ at _ZL10long_const = internal addrspace(10) global i64 0, align 8
+ at _ZL11float_const = internal addrspace(10) global float 0.000000e+00, align 4
+ at _ZL12double_const = internal addrspace(10) global double 0.000000e+00, align 8
+ at _ZL10enum_const = internal addrspace(10) global i32 0, align 4
+
+; Function Attrs: mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, argmem: none, inaccessiblemem: none)
+define void @main() local_unnamed_addr #0 {
+entry:
+ %0 = tail call spir_func i1 @llvm.spv.get.specialization.constant.i1(i32 1, i1 true)
+ %storedv.i.i = zext i1 %0 to i32
+ store i32 %storedv.i.i, ptr addrspace(10) @_ZL10bool_const, align 4, !tbaa !3
+ %1 = tail call ptr @llvm.invariant.start.p10(i64 4, ptr addrspace(10) @_ZL10bool_const)
+ %2 = tail call spir_func i16 @llvm.spv.get.specialization.constant.i16(i32 2, i16 4)
+ store i16 %2, ptr addrspace(10) @_ZL11short_const, align 2, !tbaa !7
+ %3 = tail call ptr @llvm.invariant.start.p10(i64 2, ptr addrspace(10) @_ZL11short_const)
+ %4 = tail call spir_func i32 @llvm.spv.get.specialization.constant.i32(i32 3, i32 5)
+ store i32 %4, ptr addrspace(10) @_ZL9int_const, align 4, !tbaa !9
+ %5 = tail call ptr @llvm.invariant.start.p10(i64 4, ptr addrspace(10) @_ZL9int_const)
+ %6 = tail call spir_func i64 @llvm.spv.get.specialization.constant.i64(i32 4, i64 8)
+ store i64 %6, ptr addrspace(10) @_ZL10long_const, align 8, !tbaa !11
+ %7 = tail call ptr @llvm.invariant.start.p10(i64 8, ptr addrspace(10) @_ZL10long_const)
+ %14 = tail call reassoc nnan ninf nsz arcp afn spir_func float @llvm.spv.get.specialization.constant.f32(i32 8, float 5.000000e+01)
+ store float %14, ptr addrspace(10) @_ZL11float_const, align 4, !tbaa !13
+ %15 = tail call ptr @llvm.invariant.start.p10(i64 4, ptr addrspace(10) @_ZL11float_const)
+ %16 = tail call reassoc nnan ninf nsz arcp afn spir_func double @llvm.spv.get.specialization.constant.f64(i32 9, double 1.000000e+02)
+ store double %16, ptr addrspace(10) @_ZL12double_const, align 8, !tbaa !15
+ %17 = tail call ptr @llvm.invariant.start.p10(i64 8, ptr addrspace(10) @_ZL12double_const)
+ %18 = tail call spir_func i32 @llvm.spv.get.specialization.constant.i32(i32 10, i32 30)
+ store i32 %18, ptr addrspace(10) @_ZL10enum_const, align 4, !tbaa !17
+ %19 = tail call ptr @llvm.invariant.start.p10(i64 4, ptr addrspace(10) @_ZL10enum_const)
+ ret void
+}
+
+attributes #0 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, argmem: none, inaccessiblemem: none) "approx-func-fp-math"="true" "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
+attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(none) }
+attributes #2 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
+
+!llvm.module.flags = !{!0, !1}
+!llvm.ident = !{!2}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 7, !"frame-pointer", i32 2}
+!2 = !{!"clang version 21.0.0git (git at github.com:s-perron/llvm-project.git 060dd85ac525db3606a5ec7ca12ba346a7f075af)"}
+!3 = !{!4, !4, i64 0}
+!4 = !{!"bool", !5, i64 0}
+!5 = !{!"omnipotent char", !6, i64 0}
+!6 = !{!"Simple C++ TBAA"}
+!7 = !{!8, !8, i64 0}
+!8 = !{!"short", !5, i64 0}
+!9 = !{!10, !10, i64 0}
+!10 = !{!"int", !5, i64 0}
+!11 = !{!12, !12, i64 0}
+!12 = !{!"long long", !5, i64 0}
+!13 = !{!14, !14, i64 0}
+!14 = !{!"float", !5, i64 0}
+!15 = !{!16, !16, i64 0}
+!16 = !{!"double", !5, i64 0}
+!17 = !{!18, !18, i64 0}
+!18 = !{!"_ZTS1E", !5, i64 0}
>From abbf543a65b65e122270bdbdf66b50a5be6e2ce9 Mon Sep 17 00:00:00 2001
From: Steven Perron <stevenperron at google.com>
Date: Mon, 9 Jun 2025 14:46:59 -0400
Subject: [PATCH 2/2] Use existing builtin.
---
llvm/include/llvm/IR/IntrinsicsSPIRV.td | 4 -
llvm/lib/Target/SPIRV/SPIRVBuiltins.td | 1 +
.../Target/SPIRV/SPIRVInstructionSelector.cpp | 98 +------------------
.../CodeGen/SPIRV/constant/spec-constant.ll | 23 +++--
4 files changed, 18 insertions(+), 108 deletions(-)
diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
index 01f335a2ad2b9..8d984d6ce58df 100644
--- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td
+++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
@@ -137,10 +137,6 @@ let TargetPrefix = "spv" in {
: DefaultAttrsIntrinsic<[llvm_anyptr_ty], [llvm_any_ty, llvm_i32_ty],
[IntrNoMem]>;
- def int_spv_get_specialization_constant
- : DefaultAttrsIntrinsic<[llvm_any_ty], [llvm_i32_ty, LLVMMatchType<0>],
- [IntrNoMem, IntrWillReturn]>;
-
// Read a value from the image buffer. It does not translate directly to a
// single OpImageRead because the result type is not necessarily a 4 element
// vector.
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
index 6842e5ff067cf..5fa275ac69450 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
@@ -674,6 +674,7 @@ defm : DemangledNativeBuiltin<"ndrange_3D", OpenCL_std, Enqueue, 1, 3, OpBuildND
// Spec constant builtin records:
defm : DemangledNativeBuiltin<"__spirv_SpecConstant", OpenCL_std, SpecConstant, 2, 2, OpSpecConstant>;
+defm : DemangledNativeBuiltin<"__spirv_SpecConstant", GLSL_std_450, SpecConstant, 2, 2, OpSpecConstant>;
defm : DemangledNativeBuiltin<"__spirv_SpecConstantComposite", OpenCL_std, SpecConstant, 1, 0, OpSpecConstantComposite>;
// Async Copy and Prefetch builtin records:
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index f4a73f59196f3..2dae0721886c7 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -296,22 +296,7 @@ class SPIRVInstructionSelector : public InstructionSelector {
bool selectImageWriteIntrinsic(MachineInstr &I) const;
bool selectResourceGetPointer(Register &ResVReg, const SPIRVType *ResType,
MachineInstr &I) const;
- bool selectGetSpecializationConstant(Register &ResVReg,
- const SPIRVType *ResType,
- MachineInstr &I) const;
-
- bool buildSpecConstant(llvm::MachineInstr &I, llvm::Register &ResVReg,
- llvm::SPIRVType *ResType,
- llvm::APInt &DefaultValue) const;
-
- APInt getSpecConstantDefaultValue(llvm::MachineInstr &I) const;
-
- bool buildBoolSpecConstant(Register &ResVReg, const SPIRVType *ResType,
- bool DefaultValue, MachineInstr &I) const;
- bool buildIntegerSpecConstant(Register &ResVReg, const SPIRVType *ResType,
- uint32_t DefaultValue, MachineInstr &I) const;
- bool buildIntegerSpecConstant(Register &ResVReg, const SPIRVType *ResType,
- uint64_t DefaultValue, MachineInstr &I) const;
+
// Utilities
std::pair<Register, bool>
buildI32Constant(uint32_t Val, MachineInstr &I,
@@ -3207,9 +3192,6 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
case Intrinsic::spv_resource_getpointer: {
return selectResourceGetPointer(ResVReg, ResType, I);
}
- case Intrinsic::spv_get_specialization_constant: {
- return selectGetSpecializationConstant(ResVReg, ResType, I);
- }
case Intrinsic::spv_discard: {
return selectDiscard(ResVReg, ResType, I);
}
@@ -3327,84 +3309,6 @@ bool SPIRVInstructionSelector::selectResourceGetPointer(
.constrainAllUses(TII, TRI, RBI);
}
-bool SPIRVInstructionSelector::buildBoolSpecConstant(Register &ResVReg,
- const SPIRVType *ResType,
- bool DefaultValue,
- MachineInstr &I) const {
- uint32_t Opc =
- DefaultValue ? SPIRV::OpSpecConstantTrue : SPIRV::OpSpecConstantFalse;
- return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc))
- .addDef(ResVReg)
- .addUse(GR.getSPIRVTypeID(ResType))
- .constrainAllUses(TII, TRI, RBI);
-}
-
-bool SPIRVInstructionSelector::buildIntegerSpecConstant(
- Register &ResVReg, const SPIRVType *ResType, uint32_t DefaultValue,
- MachineInstr &I) const {
- return BuildMI(*I.getParent(), I, I.getDebugLoc(),
- TII.get(SPIRV::OpSpecConstant))
- .addDef(ResVReg)
- .addUse(GR.getSPIRVTypeID(ResType))
- .addImm(DefaultValue)
- .constrainAllUses(TII, TRI, RBI);
-}
-
-bool SPIRVInstructionSelector::buildIntegerSpecConstant(
- Register &ResVReg, const SPIRVType *ResType, uint64_t DefaultValue,
- MachineInstr &I) const {
- return BuildMI(*I.getParent(), I, I.getDebugLoc(),
- TII.get(SPIRV::OpSpecConstant))
- .addDef(ResVReg)
- .addUse(GR.getSPIRVTypeID(ResType))
- .addImm(DefaultValue & 0xFFFFFFFF)
- .addImm(DefaultValue >> 32)
- .constrainAllUses(TII, TRI, RBI);
-}
-
-bool SPIRVInstructionSelector::selectGetSpecializationConstant(
- Register &ResVReg, const SPIRVType *ResType, MachineInstr &I) const {
- uint32_t Id = foldImm(I.getOperand(2), MRI);
- bool R = false;
- APInt DefaultValue = getSpecConstantDefaultValue(I);
- if (ResType->getOpcode() == SPIRV::OpTypeBool) {
- R = buildBoolSpecConstant(ResVReg, ResType, DefaultValue.getBoolValue(), I);
- } else {
- R = buildSpecConstant(I, ResVReg, ResType, DefaultValue);
- }
- if (!R) {
- return false;
- }
- buildOpDecorate(ResVReg, I, TII, SPIRV::Decoration::SpecId, {Id});
- return R;
-}
-
-bool SPIRVInstructionSelector::buildSpecConstant(
- llvm::MachineInstr &I, llvm::Register &ResVReg, llvm::SPIRVType *ResType,
- llvm::APInt &DefaultValue) const {
- auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(),
- TII.get(SPIRV::OpSpecConstant))
- .addDef(ResVReg)
- .addUse(GR.getSPIRVTypeID(ResType));
- addNumImm(DefaultValue, MIB);
- return MIB.constrainAllUses(TII, TRI, RBI);
-}
-
-APInt SPIRVInstructionSelector::getSpecConstantDefaultValue(
- llvm::MachineInstr &I) const {
- APInt DefaultValue;
- Register DefaultValueReg = I.getOperand(3).getReg();
- auto *D = getDefInstrMaybeConstant(DefaultValueReg, MRI);
- const auto &MO = D->getOperand(1);
- if (MO.isCImm()) {
- DefaultValue = MO.getCImm()->getValue();
- } else {
- assert(MO.isFPImm() && "");
- DefaultValue = MO.getFPImm()->getValue().bitcastToAPInt();
- }
- return DefaultValue;
-}
-
bool SPIRVInstructionSelector::extractSubvector(
Register &ResVReg, const SPIRVType *ResType, Register &ReadReg,
MachineInstr &InsertionPoint) const {
diff --git a/llvm/test/CodeGen/SPIRV/constant/spec-constant.ll b/llvm/test/CodeGen/SPIRV/constant/spec-constant.ll
index a30fd326c985a..030eb1264ed66 100644
--- a/llvm/test/CodeGen/SPIRV/constant/spec-constant.ll
+++ b/llvm/test/CodeGen/SPIRV/constant/spec-constant.ll
@@ -28,31 +28,40 @@
; Function Attrs: mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, argmem: none, inaccessiblemem: none)
define void @main() local_unnamed_addr #0 {
entry:
- %0 = tail call spir_func i1 @llvm.spv.get.specialization.constant.i1(i32 1, i1 true)
+ %0 = tail call spir_func i1 @_Z20__spirv_SpecConstantib(i32 1, i1 true)
%storedv.i.i = zext i1 %0 to i32
store i32 %storedv.i.i, ptr addrspace(10) @_ZL10bool_const, align 4, !tbaa !3
%1 = tail call ptr @llvm.invariant.start.p10(i64 4, ptr addrspace(10) @_ZL10bool_const)
- %2 = tail call spir_func i16 @llvm.spv.get.specialization.constant.i16(i32 2, i16 4)
+ %2 = tail call spir_func i16 @_Z20__spirv_SpecConstantis(i32 2, i16 4)
store i16 %2, ptr addrspace(10) @_ZL11short_const, align 2, !tbaa !7
%3 = tail call ptr @llvm.invariant.start.p10(i64 2, ptr addrspace(10) @_ZL11short_const)
- %4 = tail call spir_func i32 @llvm.spv.get.specialization.constant.i32(i32 3, i32 5)
+ %4 = tail call spir_func i32 @_Z20__spirv_SpecConstantii(i32 3, i32 5)
store i32 %4, ptr addrspace(10) @_ZL9int_const, align 4, !tbaa !9
%5 = tail call ptr @llvm.invariant.start.p10(i64 4, ptr addrspace(10) @_ZL9int_const)
- %6 = tail call spir_func i64 @llvm.spv.get.specialization.constant.i64(i32 4, i64 8)
+ %6 = tail call spir_func i64 @_Z20__spirv_SpecConstantix(i32 4, i64 8)
store i64 %6, ptr addrspace(10) @_ZL10long_const, align 8, !tbaa !11
%7 = tail call ptr @llvm.invariant.start.p10(i64 8, ptr addrspace(10) @_ZL10long_const)
- %14 = tail call reassoc nnan ninf nsz arcp afn spir_func float @llvm.spv.get.specialization.constant.f32(i32 8, float 5.000000e+01)
+ %14 = tail call reassoc nnan ninf nsz arcp afn spir_func float @_Z20__spirv_SpecConstantif(i32 8, float 5.000000e+01)
store float %14, ptr addrspace(10) @_ZL11float_const, align 4, !tbaa !13
%15 = tail call ptr @llvm.invariant.start.p10(i64 4, ptr addrspace(10) @_ZL11float_const)
- %16 = tail call reassoc nnan ninf nsz arcp afn spir_func double @llvm.spv.get.specialization.constant.f64(i32 9, double 1.000000e+02)
+ %16 = tail call reassoc nnan ninf nsz arcp afn spir_func double @_Z20__spirv_SpecConstantid(i32 9, double 1.000000e+02)
store double %16, ptr addrspace(10) @_ZL12double_const, align 8, !tbaa !15
%17 = tail call ptr @llvm.invariant.start.p10(i64 8, ptr addrspace(10) @_ZL12double_const)
- %18 = tail call spir_func i32 @llvm.spv.get.specialization.constant.i32(i32 10, i32 30)
+ %18 = tail call spir_func i32 @_Z20__spirv_SpecConstantii(i32 10, i32 30)
store i32 %18, ptr addrspace(10) @_ZL10enum_const, align 4, !tbaa !17
%19 = tail call ptr @llvm.invariant.start.p10(i64 4, ptr addrspace(10) @_ZL10enum_const)
ret void
}
+
+declare i1 @_Z20__spirv_SpecConstantib(i32, i1)
+declare i8 @_Z20__spirv_SpecConstantia(i32, i8)
+declare i16 @_Z20__spirv_SpecConstantis(i32, i16)
+declare i32 @_Z20__spirv_SpecConstantii(i32, i32)
+declare i64 @_Z20__spirv_SpecConstantix(i32, i64)
+declare float @_Z20__spirv_SpecConstantif(i32, float)
+declare double @_Z20__spirv_SpecConstantid(i32, double)
+
attributes #0 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, argmem: none, inaccessiblemem: none) "approx-func-fp-math"="true" "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(none) }
attributes #2 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
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