[lld] [llvm] [feature][riscv] handle target address calculation in llvm-objdump disassembly for riscv (PR #109914)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 9 11:15:58 PDT 2025
================
@@ -0,0 +1,111 @@
+# RUN: llvm-objdump -d %p/Inputs/riscv-ar-coverage | FileCheck %s
+
+# CHECK: 0000000000001000 <_start>:
+# CHECK-NEXT: 1000: 00001517 auipc a0, 0x1
+# CHECK-NEXT: 1004: 00450513 addi a0, a0, 0x4 <target>
+# CHECK-NEXT: 1008: 00001517 auipc a0, 0x1
+# CHECK-NEXT: 100c: 1571 addi a0, a0, -0x4 <target>
+# CHECK-NEXT: 100e: 6509 lui a0, 0x2
+# CHECK-NEXT: 1010: 0045059b addiw a1, a0, 0x4 <target>
+# CHECK-NEXT: 1014: 6509 lui a0, 0x2
+# CHECK-NEXT: 1016: 2511 addiw a0, a0, 0x4 <target>
+# CHECK-NEXT: 1018: 00102537 lui a0, 0x102
+# CHECK-NEXT: 101c: c50c sw a1, 0x8(a0) <far_target>
+# CHECK-NEXT: 101e: 00102537 lui a0, 0x102
+# CHECK-NEXT: 1022: 4508 lw a0, 0x8(a0) <far_target>
+# CHECK-NEXT: 1024: 6509 lui a0, 0x2
+# CHECK-NEXT: 1026: 6585 lui a1, 0x1
+# CHECK-NEXT: 1028: 0306 slli t1, t1, 0x1
+# CHECK-NEXT: 102a: 0511 addi a0, a0, 0x4 <target>
+# CHECK-NEXT: 102c: 0505 addi a0, a0, 0x1
+# CHECK-NEXT: 102e: 00200037 lui zero, 0x200
+# CHECK-NEXT: 1032: 00a02423 sw a0, 0x8(zero)
+# CHECK-NEXT: 1036: 00101097 auipc ra, 0x101
+# CHECK-NEXT: 103a: fd6080e7 jalr -0x2a(ra) <func>
+# CHECK-NEXT: 103e: 00102437 lui s0, 0x102
+# CHECK-NEXT: 1042: 8800 sb s0, 0x0(s0) <target+0xffffc>
+# CHECK-NEXT: 1044: 00102137 lui sp, 0x102
+# CHECK-NEXT: 1048: 4522 lw a0, 0x8(sp) <far_target>
+
+.global _start
+.text
+
+# The core of the feature being added was address resolution for instruction
+# sequences where an register is populated by immediate values via two
----------------
topperc wrote:
```suggestion
# sequences where a register is populated by immediate values via two
```
https://github.com/llvm/llvm-project/pull/109914
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