[llvm] [RISCV] Select (add C, x) -> (add.uw C|0xffffffff00000000, x) (PR #143375)

[Craig Topper via llvm-commits]

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@@ -704,9 +704,13 @@ def : CSImm12MulBy4Pat<SH2ADD>;
 def : CSImm12MulBy8Pat<SH3ADD>;
 } // Predicates = [HasStdExtZba]
 
+def zExtImm32 : ComplexPattern<i64, 1, "selectZExtImm32", [], [], 0>;
+
 multiclass ADD_UWPat<Instruction add_uw> {
   def : Pat<(i64 (add_like_non_imm12 (and GPR:$rs1, 0xFFFFFFFF), GPR:$rs2)),
             (add_uw GPR:$rs1, GPR:$rs2)>;
+  def : Pat<(i64 (add_like zExtImm32:$rs1, GPR:$rs2)),
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topperc wrote:

We're using `add_like` here, but the code in `RISCVDAGToDAGISel::selectZExtImm32` doesn't allow `or`.

https://github.com/llvm/llvm-project/pull/143375