[llvm] 592e596 - [TableGen] Move getSuperRegForSubReg into CodeGenRegBank. NFC. (#142979)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 9 04:03:32 PDT 2025
Author: Jay Foad
Date: 2025-06-09T12:03:29+01:00
New Revision: 592e59667a04cf9a35a9b040772e08cb67902463
URL: https://github.com/llvm/llvm-project/commit/592e59667a04cf9a35a9b040772e08cb67902463
DIFF: https://github.com/llvm/llvm-project/commit/592e59667a04cf9a35a9b040772e08cb67902463.diff
LOG: [TableGen] Move getSuperRegForSubReg into CodeGenRegBank. NFC. (#142979)
This method doesn't use anything from CodeGenTarget, so it seems to
belong in CodeGenRegBank.
Added:
Modified:
llvm/utils/TableGen/Common/CodeGenRegisters.cpp
llvm/utils/TableGen/Common/CodeGenRegisters.h
llvm/utils/TableGen/Common/CodeGenTarget.cpp
llvm/utils/TableGen/Common/CodeGenTarget.h
llvm/utils/TableGen/GlobalISelEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index 8132f996e9632..5ec9b35379fa4 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -2623,6 +2623,55 @@ CodeGenRegBank::getMinimalPhysRegClass(const Record *RegRecord,
return BestRC;
}
+const CodeGenRegisterClass *
+CodeGenRegBank::getSuperRegForSubReg(const ValueTypeByHwMode &ValueTy,
+ const CodeGenSubRegIndex *SubIdx,
+ bool MustBeAllocatable) const {
+ std::vector<const CodeGenRegisterClass *> Candidates;
+ auto &RegClasses = getRegClasses();
+
+ // Try to find a register class which supports ValueTy, and also contains
+ // SubIdx.
+ for (const CodeGenRegisterClass &RC : RegClasses) {
+ // Is there a subclass of this class which contains this subregister index?
+ const CodeGenRegisterClass *SubClassWithSubReg =
+ RC.getSubClassWithSubReg(SubIdx);
+ if (!SubClassWithSubReg)
+ continue;
+
+ // We have a class. Check if it supports this value type.
+ if (!llvm::is_contained(SubClassWithSubReg->VTs, ValueTy))
+ continue;
+
+ // If necessary, check that it is allocatable.
+ if (MustBeAllocatable && !SubClassWithSubReg->Allocatable)
+ continue;
+
+ // We have a register class which supports both the value type and
+ // subregister index. Remember it.
+ Candidates.push_back(SubClassWithSubReg);
+ }
+
+ // If we didn't find anything, we're done.
+ if (Candidates.empty())
+ return nullptr;
+
+ // Find and return the largest of our candidate classes.
+ llvm::stable_sort(Candidates, [&](const CodeGenRegisterClass *A,
+ const CodeGenRegisterClass *B) {
+ if (A->getMembers().size() > B->getMembers().size())
+ return true;
+
+ if (A->getMembers().size() < B->getMembers().size())
+ return false;
+
+ // Order by name as a tie-breaker.
+ return StringRef(A->getName()) < B->getName();
+ });
+
+ return Candidates[0];
+}
+
BitVector
CodeGenRegBank::computeCoveredRegisters(ArrayRef<const Record *> Regs) {
SetVector<const CodeGenRegister *> Set;
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.h b/llvm/utils/TableGen/Common/CodeGenRegisters.h
index 75d9a3f7a2c0f..3f4c157fab69a 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.h
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.h
@@ -831,6 +831,13 @@ class CodeGenRegBank {
getMinimalPhysRegClass(const Record *RegRecord,
ValueTypeByHwMode *VT = nullptr);
+ /// Return the largest register class which supports \p Ty and covers \p
+ /// SubIdx if it exists.
+ const CodeGenRegisterClass *
+ getSuperRegForSubReg(const ValueTypeByHwMode &Ty,
+ const CodeGenSubRegIndex *SubIdx,
+ bool MustBeAllocatable = false) const;
+
// Get the sum of unit weights.
unsigned getRegUnitSetWeight(const std::vector<unsigned> &Units) const {
unsigned Weight = 0;
diff --git a/llvm/utils/TableGen/Common/CodeGenTarget.cpp b/llvm/utils/TableGen/Common/CodeGenTarget.cpp
index 303589d7a934a..f519582387db9 100644
--- a/llvm/utils/TableGen/Common/CodeGenTarget.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenTarget.cpp
@@ -160,54 +160,6 @@ CodeGenRegBank &CodeGenTarget::getRegBank() const {
return *RegBank;
}
-const CodeGenRegisterClass *CodeGenTarget::getSuperRegForSubReg(
- const ValueTypeByHwMode &ValueTy, CodeGenRegBank &RegBank,
- const CodeGenSubRegIndex *SubIdx, bool MustBeAllocatable) const {
- std::vector<const CodeGenRegisterClass *> Candidates;
- auto &RegClasses = RegBank.getRegClasses();
-
- // Try to find a register class which supports ValueTy, and also contains
- // SubIdx.
- for (const CodeGenRegisterClass &RC : RegClasses) {
- // Is there a subclass of this class which contains this subregister index?
- const CodeGenRegisterClass *SubClassWithSubReg =
- RC.getSubClassWithSubReg(SubIdx);
- if (!SubClassWithSubReg)
- continue;
-
- // We have a class. Check if it supports this value type.
- if (!llvm::is_contained(SubClassWithSubReg->VTs, ValueTy))
- continue;
-
- // If necessary, check that it is allocatable.
- if (MustBeAllocatable && !SubClassWithSubReg->Allocatable)
- continue;
-
- // We have a register class which supports both the value type and
- // subregister index. Remember it.
- Candidates.push_back(SubClassWithSubReg);
- }
-
- // If we didn't find anything, we're done.
- if (Candidates.empty())
- return nullptr;
-
- // Find and return the largest of our candidate classes.
- llvm::stable_sort(Candidates, [&](const CodeGenRegisterClass *A,
- const CodeGenRegisterClass *B) {
- if (A->getMembers().size() > B->getMembers().size())
- return true;
-
- if (A->getMembers().size() < B->getMembers().size())
- return false;
-
- // Order by name as a tie-breaker.
- return StringRef(A->getName()) < B->getName();
- });
-
- return Candidates[0];
-}
-
/// getRegisterByName - If there is a register with the specific AsmName,
/// return it.
const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const {
diff --git a/llvm/utils/TableGen/Common/CodeGenTarget.h b/llvm/utils/TableGen/Common/CodeGenTarget.h
index da2f3e060591a..52871f33a301a 100644
--- a/llvm/utils/TableGen/Common/CodeGenTarget.h
+++ b/llvm/utils/TableGen/Common/CodeGenTarget.h
@@ -122,13 +122,6 @@ class CodeGenTarget {
/// getRegBank - Return the register bank description.
CodeGenRegBank &getRegBank() const;
- /// Return the largest register class on \p RegBank which supports \p Ty and
- /// covers \p SubIdx if it exists.
- const CodeGenRegisterClass *
- getSuperRegForSubReg(const ValueTypeByHwMode &Ty, CodeGenRegBank &RegBank,
- const CodeGenSubRegIndex *SubIdx,
- bool MustBeAllocatable = false) const;
-
/// getRegisterByName - If there is a register with the specific AsmName,
/// return it.
const CodeGenRegister *getRegisterByName(StringRef Name) const;
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp
index 5b61d6e3f6561..413ca52e40057 100644
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -2019,7 +2019,7 @@ const CodeGenRegisterClass *GlobalISelEmitter::inferSuperRegisterClass(
// Use the information we found above to find a minimal register class which
// supports the subregister and type we want.
- return Target.getSuperRegForSubReg(Ty.getValueTypeByHwMode(), CGRegs, SubIdx,
+ return CGRegs.getSuperRegForSubReg(Ty.getValueTypeByHwMode(), SubIdx,
/*MustBeAllocatable=*/true);
}
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