[llvm] 03f616e - [llvm] Compare std::optional<T> to values directly (NFC) (#143340)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Jun 8 22:38:02 PDT 2025
Author: Kazu Hirata
Date: 2025-06-08T22:37:59-07:00
New Revision: 03f616eb3acf1ae5a219ea247d9efe3cbfd41b59
URL: https://github.com/llvm/llvm-project/commit/03f616eb3acf1ae5a219ea247d9efe3cbfd41b59
DIFF: https://github.com/llvm/llvm-project/commit/03f616eb3acf1ae5a219ea247d9efe3cbfd41b59.diff
LOG: [llvm] Compare std::optional<T> to values directly (NFC) (#143340)
This patch transforms:
X && *X == Y
to:
X == Y
where X is of std::optional<T>, and Y is of T or similar.
Added:
Modified:
llvm/lib/Analysis/LoopAccessAnalysis.cpp
llvm/lib/DebugInfo/DWARF/DWARFExpression.cpp
llvm/lib/ObjCopy/MachO/MachOObject.h
llvm/lib/Object/ELFObjectFile.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/lib/Transforms/IPO/OpenMPOpt.cpp
llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
llvm/lib/Transforms/Utils/Debugify.cpp
llvm/tools/llvm-cov/SourceCoverageViewText.cpp
llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
llvm/unittests/Support/ARMAttributeParser.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Analysis/LoopAccessAnalysis.cpp b/llvm/lib/Analysis/LoopAccessAnalysis.cpp
index c7baf288838c9..00cdb66d8b779 100644
--- a/llvm/lib/Analysis/LoopAccessAnalysis.cpp
+++ b/llvm/lib/Analysis/LoopAccessAnalysis.cpp
@@ -1622,7 +1622,7 @@ bool llvm::isConsecutiveAccess(Value *A, Value *B, const DataLayout &DL,
std::optional<int64_t> Diff =
getPointersDiff(ElemTyA, PtrA, ElemTyB, PtrB, DL, SE,
/*StrictCheck=*/true, CheckType);
- return Diff && *Diff == 1;
+ return Diff == 1;
}
void MemoryDepChecker::addAccess(StoreInst *SI) {
diff --git a/llvm/lib/DebugInfo/DWARF/DWARFExpression.cpp b/llvm/lib/DebugInfo/DWARF/DWARFExpression.cpp
index 3f6695ef25663..08fd8a9cf263a 100644
--- a/llvm/lib/DebugInfo/DWARF/DWARFExpression.cpp
+++ b/llvm/lib/DebugInfo/DWARF/DWARFExpression.cpp
@@ -499,7 +499,7 @@ static bool printCompactDWARFExpr(
break;
}
case dwarf::DW_OP_LLVM_user: {
- assert(Op.getSubCode() && *Op.getSubCode() == dwarf::DW_OP_LLVM_nop);
+ assert(Op.getSubCode() == dwarf::DW_OP_LLVM_nop);
break;
}
default:
diff --git a/llvm/lib/ObjCopy/MachO/MachOObject.h b/llvm/lib/ObjCopy/MachO/MachOObject.h
index 79eb0133c2802..13ac87ed3ed06 100644
--- a/llvm/lib/ObjCopy/MachO/MachOObject.h
+++ b/llvm/lib/ObjCopy/MachO/MachOObject.h
@@ -71,7 +71,7 @@ struct Section {
}
bool hasValidOffset() const {
- return !(isVirtualSection() || (OriginalOffset && *OriginalOffset == 0));
+ return !(isVirtualSection() || OriginalOffset == 0);
}
};
diff --git a/llvm/lib/Object/ELFObjectFile.cpp b/llvm/lib/Object/ELFObjectFile.cpp
index bf6d51919b5ca..dd240550cba0f 100644
--- a/llvm/lib/Object/ELFObjectFile.cpp
+++ b/llvm/lib/Object/ELFObjectFile.cpp
@@ -736,8 +736,7 @@ void ELFObjectFileBase::setARMSubArch(Triple &TheTriple) const {
case ARMBuildAttrs::v7: {
std::optional<unsigned> ArchProfileAttr =
Attributes.getAttributeValue(ARMBuildAttrs::CPU_arch_profile);
- if (ArchProfileAttr &&
- *ArchProfileAttr == ARMBuildAttrs::MicroControllerProfile)
+ if (ArchProfileAttr == ARMBuildAttrs::MicroControllerProfile)
Triple += "v7m";
else
Triple += "v7";
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 379f07e14948c..121720e7defd4 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -5870,19 +5870,19 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
// If the operand is an higher half itself, rewrite it to
// extract_high_v2i64; this way aarch64_neon_pmull64 could
// re-use the dag-combiner function with aarch64_neon_{pmull,smull,umull}.
- if (NLane && *NLane == 1)
+ if (NLane == 1)
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v1i64,
N.getOperand(0), DAG.getConstant(1, dl, MVT::i64));
// Operand N is not a higher half but the other operand is.
- if (OtherLane && *OtherLane == 1) {
+ if (OtherLane == 1) {
// If this operand is a lower half, rewrite it to
// extract_high_v2i64(duplane(<2 x Ty>, 0)). This saves a roundtrip to
// align lanes of two operands. A roundtrip sequence (to move from lane
// 1 to lane 0) is like this:
// mov x8, v0.d[1]
// fmov d0, x8
- if (NLane && *NLane == 0)
+ if (NLane == 0)
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v1i64,
DAG.getNode(AArch64ISD::DUPLANE64, dl, MVT::v2i64,
N.getOperand(0),
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 5daa39abee8be..e8dff85064383 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -4263,7 +4263,7 @@ static bool isNot(const MachineRegisterInfo &MRI, const MachineInstr &MI) {
if (MI.getOpcode() != TargetOpcode::G_XOR)
return false;
auto ConstVal = getIConstantVRegSExtVal(MI.getOperand(2).getReg(), MRI);
- return ConstVal && *ConstVal == -1;
+ return ConstVal == -1;
}
// Return the use branch instruction, otherwise null if the usage is invalid.
diff --git a/llvm/lib/Transforms/IPO/OpenMPOpt.cpp b/llvm/lib/Transforms/IPO/OpenMPOpt.cpp
index b2d409a74c326..dd7ae7e66e350 100644
--- a/llvm/lib/Transforms/IPO/OpenMPOpt.cpp
+++ b/llvm/lib/Transforms/IPO/OpenMPOpt.cpp
@@ -5232,8 +5232,7 @@ struct AAFoldRuntimeCallCallSiteReturned : AAFoldRuntimeCall {
IRPosition::callsite_returned(CB),
[&](const IRPosition &IRP, const AbstractAttribute *AA,
bool &UsedAssumedInformation) -> std::optional<Value *> {
- assert((isValidState() ||
- (SimplifiedValue && *SimplifiedValue == nullptr)) &&
+ assert((isValidState() || SimplifiedValue == nullptr) &&
"Unexpected invalid state!");
if (!isAtFixpoint()) {
diff --git a/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp b/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
index cbad5dd357687..2786d81773ed9 100644
--- a/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
+++ b/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
@@ -1010,9 +1010,9 @@ void State::addInfoForInductions(BasicBlock &BB) {
auto IncUnsigned = SE.getMonotonicPredicateType(AR, CmpInst::ICMP_UGT);
auto IncSigned = SE.getMonotonicPredicateType(AR, CmpInst::ICMP_SGT);
bool MonotonicallyIncreasingUnsigned =
- IncUnsigned && *IncUnsigned == ScalarEvolution::MonotonicallyIncreasing;
+ IncUnsigned == ScalarEvolution::MonotonicallyIncreasing;
bool MonotonicallyIncreasingSigned =
- IncSigned && *IncSigned == ScalarEvolution::MonotonicallyIncreasing;
+ IncSigned == ScalarEvolution::MonotonicallyIncreasing;
// If SCEV guarantees that AR does not wrap, PN >= StartValue can be added
// unconditionally.
if (MonotonicallyIncreasingUnsigned)
diff --git a/llvm/lib/Transforms/Utils/Debugify.cpp b/llvm/lib/Transforms/Utils/Debugify.cpp
index 3e323ccffcd99..729813a92f516 100644
--- a/llvm/lib/Transforms/Utils/Debugify.cpp
+++ b/llvm/lib/Transforms/Utils/Debugify.cpp
@@ -705,7 +705,7 @@ bool diagnoseMisSizedDbgValue(Module &M, DbgValTy *DbgVal) {
bool HasBadSize = false;
if (Ty->isIntegerTy()) {
auto Signedness = DbgVal->getVariable()->getSignedness();
- if (Signedness && *Signedness == DIBasicType::Signedness::Signed)
+ if (Signedness == DIBasicType::Signedness::Signed)
HasBadSize = ValueOperandSize < *DbgVarSize;
} else {
HasBadSize = ValueOperandSize != *DbgVarSize;
diff --git a/llvm/tools/llvm-cov/SourceCoverageViewText.cpp b/llvm/tools/llvm-cov/SourceCoverageViewText.cpp
index 765f8bbbd8d1b..df8eb1d871878 100644
--- a/llvm/tools/llvm-cov/SourceCoverageViewText.cpp
+++ b/llvm/tools/llvm-cov/SourceCoverageViewText.cpp
@@ -186,8 +186,8 @@ void SourceCoverageViewText::renderLine(raw_ostream &OS, LineRef L,
if (getOptions().Debug && Highlight)
HighlightedRanges.push_back(std::make_pair(Col, End));
Col = End;
- if ((!S->IsGapRegion || (Highlight && *Highlight == raw_ostream::RED)) &&
- S->HasCount && S->Count == 0)
+ if ((!S->IsGapRegion || Highlight == raw_ostream::RED) && S->HasCount &&
+ S->Count == 0)
Highlight = raw_ostream::RED;
else if (Col == ExpansionCol)
Highlight = raw_ostream::CYAN;
diff --git a/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp b/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
index 67a0d948dcace..1b590aa33bd86 100644
--- a/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
+++ b/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
@@ -567,7 +567,7 @@ struct VPMatchContext : public SDPatternMatch::BasicMatchContext {
return OpVal->getOpcode() == Opc;
auto BaseOpc = ISD::getBaseOpcodeForVP(OpVal->getOpcode(), false);
- return BaseOpc.has_value() && *BaseOpc == Opc;
+ return BaseOpc == Opc;
}
unsigned getNumOperands(SDValue N) const {
diff --git a/llvm/unittests/Support/ARMAttributeParser.cpp b/llvm/unittests/Support/ARMAttributeParser.cpp
index e06f7fab85fa7..305f4b3d1d0ef 100644
--- a/llvm/unittests/Support/ARMAttributeParser.cpp
+++ b/llvm/unittests/Support/ARMAttributeParser.cpp
@@ -38,7 +38,7 @@ bool testBuildAttr(unsigned Tag, unsigned Value,
cantFail(Parser.parse(Bytes, llvm::endianness::little));
std::optional<unsigned> Attr = Parser.getAttributeValue("", ExpectedTag);
- return Attr && *Attr == ExpectedValue;
+ return Attr == ExpectedValue;
}
void testParseError(ArrayRef<uint8_t> bytes, const char *msg) {
More information about the llvm-commits
mailing list