[llvm] 0583297 - [AArch64][GlobalISel] Add patterns for FPR i8 G_DUP
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sun Jun 8 13:38:13 PDT 2025
Author: David Green
Date: 2025-06-08T21:38:09+01:00
New Revision: 0583297f37f94fef1bb95e173226617fdb240160
URL: https://github.com/llvm/llvm-project/commit/0583297f37f94fef1bb95e173226617fdb240160
DIFF: https://github.com/llvm/llvm-project/commit/0583297f37f94fef1bb95e173226617fdb240160.diff
LOG: [AArch64][GlobalISel] Add patterns for FPR i8 G_DUP
This adds missing patterns for i8 G_DUP from FPR registers, not present from
the other fp patterns like f16/f32 etc.
Added:
Modified:
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/test/CodeGen/AArch64/dup.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 5214b9bb3bbac..0dbce01d7092d 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -7156,6 +7156,16 @@ def : Pat<(v8bf16 (AArch64dup (bf16 FPR16:$Rn))),
(INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
(i64 0)))>;
+// Patterns for importing fpr i8 G_DUP under GISel.
+def : Pat<(v8i8 (AArch64dup (i8 FPR8:$Rn))),
+ (v8i8 (DUPv8i8lane
+ (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR8:$Rn, bsub),
+ (i64 0)))>;
+def : Pat<(v16i8 (AArch64dup (i8 FPR8:$Rn))),
+ (v16i8 (DUPv16i8lane
+ (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR8:$Rn, bsub),
+ (i64 0)))>;
+
def : Pat<(v4f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
(DUPv4i16lane V128:$Rn, VectorIndexH:$imm)>;
def : Pat<(v8f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
diff --git a/llvm/test/CodeGen/AArch64/dup.ll b/llvm/test/CodeGen/AArch64/dup.ll
index bdeab033ce084..26e070f2a0acd 100644
--- a/llvm/test/CodeGen/AArch64/dup.ll
+++ b/llvm/test/CodeGen/AArch64/dup.ll
@@ -6,11 +6,6 @@
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for duplane0_v2i8
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for loaddup_v2i8
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for loaddup_str_v2i8
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for loaddup_str_v3i8
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for loaddup_str_v4i8
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for loaddup_str_v8i8
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for loaddup_str_v16i8
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for loaddup_str_v32i8
define <2 x i8> @dup_v2i8(i8 %a) {
; CHECK-LABEL: dup_v2i8:
@@ -127,14 +122,25 @@ entry:
}
define <3 x i8> @loaddup_str_v3i8(ptr %p) {
-; CHECK-LABEL: loaddup_str_v3i8:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov x8, x0
-; CHECK-NEXT: ldrb w0, [x0]
-; CHECK-NEXT: strb wzr, [x8]
-; CHECK-NEXT: mov w1, w0
-; CHECK-NEXT: mov w2, w0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: loaddup_str_v3i8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: mov x8, x0
+; CHECK-SD-NEXT: ldrb w0, [x0]
+; CHECK-SD-NEXT: strb wzr, [x8]
+; CHECK-SD-NEXT: mov w1, w0
+; CHECK-SD-NEXT: mov w2, w0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: loaddup_str_v3i8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ldr b0, [x0]
+; CHECK-GI-NEXT: mov x8, x0
+; CHECK-GI-NEXT: strb wzr, [x8]
+; CHECK-GI-NEXT: dup v0.8b, v0.b[0]
+; CHECK-GI-NEXT: umov w0, v0.b[0]
+; CHECK-GI-NEXT: umov w1, v0.b[1]
+; CHECK-GI-NEXT: umov w2, v0.b[2]
+; CHECK-GI-NEXT: ret
entry:
%a = load i8, ptr %p
%b = insertelement <3 x i8> poison, i8 %a, i64 0
@@ -201,12 +207,21 @@ entry:
}
define <4 x i8> @loaddup_str_v4i8(ptr %p) {
-; CHECK-LABEL: loaddup_str_v4i8:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ldrb w8, [x0]
-; CHECK-NEXT: strb wzr, [x0]
-; CHECK-NEXT: dup v0.4h, w8
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: loaddup_str_v4i8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ldrb w8, [x0]
+; CHECK-SD-NEXT: strb wzr, [x0]
+; CHECK-SD-NEXT: dup v0.4h, w8
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: loaddup_str_v4i8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ldr b0, [x0]
+; CHECK-GI-NEXT: strb wzr, [x0]
+; CHECK-GI-NEXT: dup v0.8b, v0.b[0]
+; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
entry:
%a = load i8, ptr %p
%b = insertelement <4 x i8> poison, i8 %a, i64 0
@@ -250,11 +265,18 @@ entry:
}
define <8 x i8> @loaddup_str_v8i8(ptr %p) {
-; CHECK-LABEL: loaddup_str_v8i8:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ld1r { v0.8b }, [x0]
-; CHECK-NEXT: strb wzr, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: loaddup_str_v8i8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ld1r { v0.8b }, [x0]
+; CHECK-SD-NEXT: strb wzr, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: loaddup_str_v8i8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ldr b0, [x0]
+; CHECK-GI-NEXT: strb wzr, [x0]
+; CHECK-GI-NEXT: dup v0.8b, v0.b[0]
+; CHECK-GI-NEXT: ret
entry:
%a = load i8, ptr %p
%b = insertelement <8 x i8> poison, i8 %a, i64 0
@@ -297,11 +319,18 @@ entry:
}
define <16 x i8> @loaddup_str_v16i8(ptr %p) {
-; CHECK-LABEL: loaddup_str_v16i8:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ld1r { v0.16b }, [x0]
-; CHECK-NEXT: strb wzr, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: loaddup_str_v16i8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ld1r { v0.16b }, [x0]
+; CHECK-SD-NEXT: strb wzr, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: loaddup_str_v16i8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ldr b0, [x0]
+; CHECK-GI-NEXT: strb wzr, [x0]
+; CHECK-GI-NEXT: dup v0.16b, v0.b[0]
+; CHECK-GI-NEXT: ret
entry:
%a = load i8, ptr %p
%b = insertelement <16 x i8> poison, i8 %a, i64 0
@@ -353,12 +382,20 @@ entry:
}
define <32 x i8> @loaddup_str_v32i8(ptr %p) {
-; CHECK-LABEL: loaddup_str_v32i8:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ld1r { v0.16b }, [x0]
-; CHECK-NEXT: strb wzr, [x0]
-; CHECK-NEXT: mov v1.16b, v0.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: loaddup_str_v32i8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ld1r { v0.16b }, [x0]
+; CHECK-SD-NEXT: strb wzr, [x0]
+; CHECK-SD-NEXT: mov v1.16b, v0.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: loaddup_str_v32i8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ldr b1, [x0]
+; CHECK-GI-NEXT: strb wzr, [x0]
+; CHECK-GI-NEXT: dup v0.16b, v1.b[0]
+; CHECK-GI-NEXT: dup v1.16b, v1.b[0]
+; CHECK-GI-NEXT: ret
entry:
%a = load i8, ptr %p
%b = insertelement <32 x i8> poison, i8 %a, i64 0
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