[compiler-rt] [llvm] [RISCV] Allocate feature bits for Zifencei and Zmmul (PR #143306)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Luke Wren (Wren6991)

<details>
<summary>Changes</summary>

As proposed in https://github.com/riscv-non-isa/riscv-c-api-doc/pull/110.

No real compiler-rt implementation as Linux does not list these extensions in hwprobe.

---
Full diff: https://github.com/llvm/llvm-project/pull/143306.diff


2 Files Affected:

- (modified) compiler-rt/lib/builtins/cpu_model/riscv.c (+4) 
- (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+4-2) 


``````````diff
diff --git a/compiler-rt/lib/builtins/cpu_model/riscv.c b/compiler-rt/lib/builtins/cpu_model/riscv.c
index 4d0fda473c87e..5a334a122583a 100644
--- a/compiler-rt/lib/builtins/cpu_model/riscv.c
+++ b/compiler-rt/lib/builtins/cpu_model/riscv.c
@@ -134,6 +134,10 @@ struct {
 #define ZCLSD_BITMASK (1ULL << 9)
 #define ZCMP_GROUPID 1
 #define ZCMP_BITMASK (1ULL << 10)
+#define ZIFENCEI_GROUPID 1
+#define ZIFENCEI_BITMASK (1ULL << 11)
+#define ZMMUL_GROUPID 1
+#define ZMMUL_BITMASK (1ULL << 12)
 
 #if defined(__linux__)
 
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 690068d05aaab..c756d5cb76eee 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -134,7 +134,8 @@ def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
                           "(Integer Conditional Operations)">;
 
 def FeatureStdExtZifencei
-    : RISCVExtension<2, 0, "fence.i">;
+    : RISCVExtension<2, 0, "fence.i">,
+      RISCVExtensionBitmask<1, 11>;
 def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
                         AssemblerPredicate<(all_of FeatureStdExtZifencei),
                                            "'Zifencei' (fence.i)">;
@@ -192,7 +193,8 @@ def NoHasStdExtZilsd : Predicate<"!Subtarget->hasStdExtZilsd()">;
 // Multiply Extensions
 
 def FeatureStdExtZmmul
-    : RISCVExtension<1, 0, "Integer Multiplication">;
+    : RISCVExtension<1, 0, "Integer Multiplication">,
+      RISCVExtensionBitmask<1, 12>;
 def HasStdExtZmmul : Predicate<"Subtarget->hasStdExtZmmul()">,
                      AssemblerPredicate<(all_of FeatureStdExtZmmul),
                      "'Zmmul' (Integer Multiplication)">;

``````````

</details>


https://github.com/llvm/llvm-project/pull/143306