[llvm] [X86][FP16] Do not generate X86 FMIN/FMAX for FP16 when VLX not enabled (PR #143100)

[Phoebe Wang via llvm-commits]

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@@ -55357,10 +55357,17 @@ static SDValue combineFMinNumFMaxNum(SDNode *N, SelectionDAG &DAG,
 
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
 
+  auto IsMinMaxLegal = [&](EVT VT) {
+    if (!TLI.isTypeLegal(VT))
+      return false;
+    return VT.getScalarType() != MVT::f16 ||
+           (Subtarget.hasFP16() && (VT == MVT::v32f16 || Subtarget.hasVLX()));
+  };
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phoebewang wrote:

There's a blocker issue. The general combiner always combines `extract_subvector(insert_subvector(BinOP X, Y))` to `BinOP X, Y`. I created #143298 to show the problem.

OTOH, the AVX512FP16 w/o AVX512VL case doesn't occur in any real HW. We just need to make sure no crash here. Performance is not a concern.

https://github.com/llvm/llvm-project/pull/143100