[llvm] [X86][GlobalIsel] support G_FABS (PR #136718)

[via llvm-commits]

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@@ -835,6 +841,43 @@ bool X86LegalizerInfo::legalizeNarrowingStore(MachineInstr &MI,
   return true;
 }
 
+bool X86LegalizerInfo::legalizeFAbs(MachineInstr &MI,
+                                         MachineRegisterInfo &MRI,
+                                         LegalizerHelper &Helper) const {
+
+  MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
+  Register SrcReg = MI.getOperand(1).getReg();
+  Register DstReg = MI.getOperand(0).getReg();
+  LLT Ty = MRI.getType(DstReg);
+  if (Subtarget.is32Bit()) {
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mahesh-attarde wrote:

For functionality of abs we are using mask, in 64 bit we have masks spans 64 bit. From ISA spec, we can only encode 32 bit immediate in instruction. so we need to load 64 bit into reg and then use reg.
Are you suggesting we only use it to double type?


https://github.com/llvm/llvm-project/pull/136718