[llvm] [RISCV] Fix coalescing vsetvlis when AVL and vl registers are the same (PR #141941)

Luke Lau via llvm-commits llvm-commits at lists.llvm.org
Fri Jun 6 08:34:35 PDT 2025

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https://github.com/lukel97 closed https://github.com/llvm/llvm-project/pull/141941

Previous message: [llvm] [RISCV] Fix coalescing vsetvlis when AVL and vl registers are the same (PR #141941)
Next message: [llvm] [ConstantFolding] Fold sqrt poison -> poison (PR #141821)
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