[llvm] [AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (PR #140694)

[Janek van Oirschot via llvm-commits]

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@@ -18,8 +18,8 @@ define amdgpu_kernel void @or_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %in)
 ; GFX6-NEXT:    s_mov_b32 s4, s0
 ; GFX6-NEXT:    s_mov_b32 s5, s1
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
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JanekvO wrote:

> But I don't understand the historical reasons for setting that flag in some bitwise op tests and not others.

I assume it has to do with the fact that the vectors are materialized in the IR through the `ptr addrspace(1)` (i.e., global addrspace). To me it still feels a bit counter-intuitive to see these changes if `-amdgpu-scalarize-global-loads=true` but that it could also be that my intuition is plainly wrong.

I was just expecting to be able to see the result of the legalization in these or/xor/and tests

https://github.com/llvm/llvm-project/pull/140694