[llvm] [AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (PR #140694)

[Chris Jackson via llvm-commits]

================
@@ -5047,8 +5066,24 @@ SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N,
   }
   case ISD::SELECT: {
     // fneg (select c, a, b) -> select c, (fneg a), (fneg b)
+    // This combine became necessary recently to prevent a regression caused by
+    // this patch legalising v2i32 xor. When adding this combine a case was
+    // added to performFNEGCombine to prevent this combine from being undone
+    // under certain conditions.
----------------
chrisjbris wrote:

Yep I'll improve these, ty.

https://github.com/llvm/llvm-project/pull/140694